CN119382707A - Input sparsity adaptive ADC circuit and module - Google Patents
Input sparsity adaptive ADC circuit and module Download PDFInfo
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Abstract
The invention relates to the technical field of analog-digital conversion circuit design, in particular to an input sparsity self-adaptive ADC circuit and a module. The invention discloses an input sparsity self-adaptive ADC circuit which comprises a sparsity detection circuit part, a sparsity control circuit part, a time sequence generation circuit part and an SAR-ADC main circuit part. The invention increases the sparsity detection of the input array, can detect the input sparsity of the array, adaptively reduces the comparison period and shortens the quantization time, thereby reducing the power consumption waste and improving the quantization efficiency under the condition of unchanged precision. The invention solves the problem that the prior ADC processes the array input and has a redundancy comparison process.
Description
Technical Field
The invention relates to the technical field of analog-digital conversion circuit design, in particular to an input sparsity self-adaptive ADC circuit and an input sparsity self-adaptive ADC module.
Background
The power consumption and area of the analog-to-digital converter (Analog to Digital Converter, ADC) as a core module of the in-memory computational quantization circuit affect the energy efficiency ratio and integration of the memory-integrated chip.
The ADC and digital-to-analog converter (Digital to Analog Converter, DAC) account for about 15% of the area and about 50% of the power consumption, respectively, in the CIM design. CIM still faces a significant challenge because of the large power and area overhead that the ADC incurs. If the ADC with lower power consumption and suitable for in-memory calculation can be researched, the overall performance of the memory calculation circuit can be greatly improved.
When the existing ADC processes array input, the same number of comparison cycles can be performed regardless of the array input sparseness. However, the inventors believe that in some cases, a partial comparison period is not required. Therefore, the inventor designs an input sparsity self-adaptive ADC circuit and module, which can pre-judge the output of the ADC in advance according to the sparsity of the array input, and reduce the comparison period, the quantization time and the power consumption waste under the condition of unchanged precision.
Disclosure of Invention
Based on this, it is necessary to provide an input sparsity adaptive ADC circuit and module for solving the problem of redundant comparison process when the existing ADC processes the array input.
The invention is realized by adopting the following technical scheme:
in a first aspect, the invention provides an input sparsity adaptive ADC circuit, which comprises a sparsity detection circuit part, a sparsity control circuit part, a time sequence generation circuit part and a SAR-ADC main circuit part.
The sparsity detection circuit part is used for sparsity detection of array inputs IN <0:63> according to an enable signal SAEN, a regulation signal CAP_RST and reference signals VREF 1-VREF 2, and generates control signals OUTN 1-OUTN 2 and control signals OUTP 1-OUTP 2.
The sparsity control circuit unit processes OUTN1 to OUTN2 in combination with the timing signal CLK and the reset signal RST, and generates an enable signal SAEN5, an enable signal SAENB5, and a reset signal RST5.
The timing generation circuit unit processes OUTP1 to OUTP2 in combination with RST5, RST, SAEN5 to generate SAEN, signal sequence DB <1:2>, and signal sequence D <3:4>.
The SAR-ADC main circuit part is used for combining array voltages VCAL, SAEN5, SAENB5, OUTN 1-OUTN 2 and OUTP 1-OUTP 2 to process DB <1:2> and D <3:4> so as to generate ADC outputs OUT 1-OUT 2.
If the sparsity of IN <0:63> is less than 50%, outn1=1, outp1=0, outn2=1, outp2=0, and the sar-ADC main circuit generates OUT1 to OUT2 after 5 comparison periods;
If the sparsity of IN <0:63> is 50% -75%, OUTN1=0, OUTP1=1, OUTN2=1, OUTP2=0, and the SAR-ADC main circuit part generates OUT 1-OUT 2 after 4 comparison periods;
If the sparseness of IN <0:63> is greater than 75%, outn1=0, outp1=1, outn2=0, outp2=1, and the sar-ADC main circuit generates OUT1 to OUT2 after 3 comparison cycles.
Implementation of such an input sparsity adaptive ADC circuit is in accordance with a method or process of an embodiment of the present disclosure.
In a second aspect, the present invention discloses an input sparsity adaptive ADC module employing the layout of the input sparsity adaptive ADC circuit as disclosed in the first aspect.
Implementation of such a memory circuit built based on an input sparsity adaptive ADC circuit is in accordance with a method or process of an embodiment of the present disclosure.
Compared with the prior art, the invention has the following beneficial effects:
The invention designs the input sparsity self-adaptive ADC, which increases the sparsity detection of an input array, can detect the input sparsity of the array, adaptively reduces the comparison period and shortens the quantization time, thereby reducing the power consumption waste and improving the quantization efficiency under the condition of unchanged precision.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a block diagram of an input sparsity adaptive ADC circuit provided in embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of input/output signals of various portions of the circuit of FIG. 1;
fig. 3 is a circuit diagram of the sparsity detection circuit section of fig. 2;
FIG. 4 is a circuit diagram of the comparator SA 0,1 of FIG. 3;
FIG. 5 is a circuit diagram of the comparator SA 0,2 of FIG. 3;
fig. 6 is a circuit diagram of the sparsity control circuit section of fig. 2;
FIG. 7 is a timing diagram of the enable signal SAEN corresponding to the array input with different sparsity;
FIG. 8 is a circuit diagram of the timing generation circuit of FIG. 2;
FIG. 9 is a circuit diagram of the SAR-ADC main circuit portion of FIG. 2;
FIG. 10 is a circuit diagram of the comparator SA1 of FIG. 9;
FIG. 11 is a timing diagram of a corresponding signal sequence D <1:4> when the sparsity of the array input is less than 50%;
FIG. 12 is a timing diagram of a corresponding signal sequence D <1:4> when the sparsity of the array inputs is between 50% -75%;
FIG. 13 is a timing diagram of the corresponding signal sequence D <1:4> when the sparsity of the array input is greater than 75%.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is noted that when an element is referred to as being "mounted to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "secured to" another element, it can be directly secured to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or/and" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1, a schematic diagram of the structure and signal flow of an input sparsity adaptive ADC circuit according to embodiment 1 is shown. More specifically, referring to FIG. 2, a schematic diagram of the input and output signals of the various components of FIG. 1 is shown.
As shown in fig. 1 and 2, the input sparsity adaptive ADC circuit can be functionally divided into 4 parts, namely a sparsity detection circuit part, a sparsity control circuit part, a timing generation circuit part, and a SAR-ADC main circuit part.
The following circuit structure description is performed one by one:
1. The sparsity detection circuit part is used for sparsity detection of array inputs IN <0:63> according to an enable signal SAEN, a regulation signal CAP_RST and reference signals VREF 1-VREF 2, and generates control signals OUTN 1-OUTN 2 and control signals OUTP 1-OUTP 2.
Specifically, referring to FIG. 3, the sparsity detection circuit portion may be designed to include a capacitance array CIN 0~CIN63, a switch array S 0~S63, and 2 comparators SA 0,1~SA0,2.
As shown IN FIG. 3, the (m+1) th signal IN < m > IN the upper plate connection IN <0:63> of CIN m, mE [0,63].
S m is a single-pole double-throw switch, the control end of S m is connected with CAP_RST, the fixed end is connected with the lower polar plate of CIN m, the first switching end forms a signal INN1, and the second switching end is connected with VSS.
The control method comprises the steps that when CAP_RST is 1, S m is connected with a second switching end, the lower substrate of CIN m is connected with VSS to reset the capacitor array, and when CAP_RST is 0, S m is connected with a first switching end, and the lower substrate of CIN m is connected with INN1.
The positive input end of SA 0,1 is connected with VREF1, the negative input end is connected with INN1, the control end is connected with SAEN, the output end I is used for outputting OUTN1, and the output end II is used for outputting OUTP1;
the positive input end of SA 0,2 is connected with VREF2, the negative input end is connected with INN1, the control end is connected with SAEN, the output end I is used for outputting OUTN2, and the output end II is used for outputting OUTP2.
SAEN uniformly controls SA 0,1~SA0,2, wherein SA 0,1~SA0,2 is reset when SAEN is 1, and SA 0,1~SA0,2 works when SAEN is 0.
Note that OUTP1 and OUTN1 are opposite signals, OUTP2 and OUTN2 are opposite signals, VREF 1=vdd/2, and vref2=vdd/4.
It should be noted that the SA 0,1~SA0,2 may be implemented using a conventional comparator design, or the circuit designs of FIGS. 4 and 5.
Specifically, referring to FIG. 4, SA 0,1 is designed to include 12 PMOS tubes PM 1-PM 12, 8 NMOS tubes NM 1-NM 8, 1 transmission gate GM1, 1 inverter INVM1.
The grid electrode of NM1 is connected with SAEN, and the source electrode is connected with VSS;
The grid electrode of NM2 is connected with SAEN, and the source electrode is connected with VSS;
The drain electrode of NM3 is used as the output end I of SA 0,1, and the source electrode is connected with VSS;
the drain electrode of NM4 is used as the second output end of SA 0,1, and the source electrode is connected with VSS;
the grid electrode of NM5 is connected with the drain electrode of NM 1;
The grid electrode of NM6 is connected with the drain electrode of NM 2;
The drain electrode of NM7 is connected with the source electrode of NM5, the source electrode is connected with VSS, and the grid electrode is connected with the drain electrode of NM 6;
the drain electrode of NM8 is connected with the source electrode of NM6, the source electrode is connected with VSS, and the grid electrode is connected with the drain electrode of NM 5;
the gate of PM1 is connected with VSS;
the grid electrode of PM2 is connected with VREF1, and the source electrode is connected with the drain electrode of PM 1;
the grid electrode of PM3 is connected with INN1, and the source electrode is connected with the drain electrode of PM 1;
PM4 has its gate connected to SAEN, its source connected to VDD, and its drain connected to PM 1's source;
the grid electrode of PM5 is connected with VSS, the drain electrode is connected with the drain electrode of NM1, the grid electrode of PM9 and the grid electrode of NM5, and the source electrode is connected with the drain electrode of PM 2;
The grid electrode of PM6 is connected with VSS, the drain electrode is connected with the drain electrode of NM2, the grid electrode of PM10 and the grid electrode of NM6, and the source electrode is connected with the drain electrode of PM 3;
The grid electrode of PM7 is connected with the grid electrode of NM3, the source electrode is connected with VDD, and the drain electrode is connected with the drain electrode of NM 3;
The grid electrode of PM8 is connected with the grid electrode of NM4, the source electrode is connected with VDD, and the drain electrode is connected with the drain electrode of NM 4;
The grid electrode of PM9 is connected with the grid electrode of NM5, the source electrode is connected with VDD, and the drain electrode is connected with the grid electrode of PM 7;
the grid electrode of PM10 is connected with the grid electrode of NM6, the source electrode is connected with VDD, and the drain electrode is connected with the grid electrode of PM 8;
The gate of PM11 is connected with the gate of NM7, the source is connected with VDD, and the drain is connected with the gate of PM 7;
The grid electrode of PM12 is connected with the grid electrode of NM8, the source electrode is connected with VDD, and the drain electrode is connected with the grid electrode of PM 8;
The input end of INVM1 is connected with SAEN;
the control end of GM1 is connected with the drain electrode of PM2, the control end II is connected with the drain electrode of PM3, the in-out end is connected with SAEN, and the in-out end II is connected with the output end of INVM 1.
Referring to FIG. 5, SA 0,2 is designed to include 12 PMOS tubes PN 1-PN 12, 8 NMOS tubes NN 1-NN 8, 1 transmission gate GN1, 1 inverter INVN1.
NN1 has its gate connected to SAEN and its source connected to VSS;
NN2 has its gate connected to SAEN and its source connected to VSS;
The drain electrode of NN3 is used as the first output end of SA 0,2, and the source electrode is connected with VSS;
The drain electrode of NN4 is used as the second output end of SA 0,2, and the source electrode is connected with VSS;
The grid electrode of NN5 is connected with the drain electrode of NN 1;
the grid electrode of NN6 is connected with the drain electrode of NN 2;
the drain electrode of NN7 is connected with the source electrode of NN5, the source electrode is connected with VSS, and the grid electrode is connected with the drain electrode of NN 6;
the drain electrode of NN8 is connected with the source electrode of NN6, the source electrode is connected with the VSS gate, and the grid electrode is connected with the drain electrode of NN 5;
the grid electrode of PN1 is connected with VSS;
the grid electrode of PN2 is connected with VREF2, and the source electrode is connected with the drain electrode of PN 1;
The grid electrode of PN3 is connected with INN1, and the source electrode is connected with the drain electrode of PN 1;
PN4 has its gate connected to SAEN, source connected to VDD and drain connected to PN1 source;
The grid electrode of PN5 is connected with VSS, the drain electrode is connected with the drain electrode of NN1, the grid electrode of PN9 and the grid electrode of NN5, and the source electrode is connected with the drain electrode of PN 2;
the grid electrode of PN6 is connected with VSS, the drain electrode is connected with the drain electrode of NN2, the grid electrode of PN10 and the grid electrode of NN6, and the source electrode is connected with the drain electrode of PN 3;
PN7 has its gate connected to NN3 gate, source connected to VDD and drain connected to NN3 drain;
PN8 has its gate connected to NN4 gate, source connected to VDD and drain connected to NN4 drain;
PN9 has its gate connected to NN5, source connected to VDD and drain connected to PN 7;
PN10 has its gate connected to NN6, source connected to VDD and drain connected to PN 8;
the grid electrode of PN11 is connected with the grid electrode of NN7, the source electrode is connected with VDD, and the drain electrode is connected with the grid electrode of PN 7;
PN12 has its gate connected to NN8 gate, source connected to VDD, and drain connected to PN8 gate;
the input end of INVN is connected with SAEN;
The control end of GN1 is connected with the drain electrode of PN2, the control end is connected with the drain electrode of PN3, the in-out end is connected with SAEN, and the in-out end is connected with the output end of INVN.
Since the structures of SA 0,1 and SA 0,2 are the same, the detailed description of the comparator principle is given by taking SA 0,1 as an example:
If INN1> VREF1, PM3 drain voltage is less than PM2, and then PM6 drain voltage is less than PM5, and then PM9 is turned off in advance, NM5 is turned on in advance, and PM 11-PM 12, NM 5-NM 8 form a latch structure (PM 11 drain forms P node, PM12 drain forms N node), N node voltage drop rate is less than P node, P node becomes 0 first, so that OUTN1 is 1, OUTP1 is 0.
Similarly, if INN1< VREF1, outn1=0, outp1=1.
Likewise, for SA 0,2:
if inn1< VREF2, outn2=0, outp2=1;
If INN1> VREF2, outn2=1, outp2=0.
Based on the circuit structure of the sparsity detection circuit, IN < m > is input IN the form of square wave, n is set as n when the number of signals of IN <0:63> is "1", n is 0,64, and then the voltage at INN1 is n is VDD/64.
① If the sparsity of IN <0:63> is less than 50%, then n e [33,64], then INN1> VREF1, INN1> VREF2, then outn1=1, outp1=0, outn2=1, outp2=0.
② If the sparsity of IN <0:63> is between 50% -75%, then n e [16,32], then INN1> VREF2, INN1< VREF1, then outn1=0, outp1=1, outn2=1, outp2=0;
③ If the sparsity of IN <0:63> is greater than 75%, then n e [0,15], then INN1< VREF1, INN1< VREF2, then outn1=0, outp1=1, outn2=0, outp2=1.
2. The sparsity control circuit unit processes OUTP1 to OUTP2 in combination with the timing signal CLK and the reset signal RST, and generates an enable signal SAEN5, an enable signal SAENB5, and a reset signal RST5.
Specifically, referring to FIG. 6, the sparsity control circuit section may be designed to include 6D flip-flops D0 to D5, 3 AND gates AND1 to AND3.
The input end of the AND1 is connected with the OUTN1, the output end of the AND1 is connected with the Q output end of the D1, AND the output end of the AND1 is electrically connected with the D input end of the D2;
The input end of the AND2 is connected with the OUTN2, the output end of the AND2 is connected with the Q output end of the D2, AND the output end of the AND2 is electrically connected with the D input end of the D3;
The Clk end of D0 is connected with CLK, the reverse phase Q output end is used for outputting SAENB5 and is connected with the D input end, and the Q output end is used for outputting SAEN5;
The Clk end of D1-D5 is connected with SAEN5, and the reset end is connected with RST;
The D input end of the D1 is connected with VSS;
The Q output end of D3 is connected with the D input end of D4, the Q output end of D4 is connected with the D input end of D5, and the Q output end of D5 is used for outputting RST5;
AND the input end of the AND3 is connected with the RST, the input end of the AND3 is connected with the RST5, AND the output end of the AND3 is connected with the reset end of the D0.
SAEN5 is a frequency division signal generated based on CLK;
the RST uniformly controls the D1-D5, wherein when the RST is 0, the D1-D5 are reset, and when the RST is 1, the D1-D5 work.
Referring to fig. 7, the circuit configuration of the control circuit section is based on the sparsity described above:
① If the sparseness of IN <0:63> is less than 50%, outn1=1, outp1=0, outn2=1, outp2=0, the output of and1 depends on the Q output of D1, the output of AND2 depends on the Q output of D2, RST5 goes to 0 after 5 clock cycles T of SAEN5, AND the and3 goes to 0, i.e., D0 goes to high after 5 clock cycles T, i.e., D0 goes to reset after 5 clock cycles T.
② If the sparseness of IN <0:63> is between 50% and 75%, outn1=0, outp1=1, outn2=1, outp2=0, and1 outputs 0, and2 outputs depending on the Q output terminal of D2, RST5 goes to 0 after 4 clock cycles T of SAEN5, and3 outputs 0, i.e., D0 goes to high reset after 4 clock cycles T of SAEN 5.
③ If the sparseness of IN <0:63> is greater than 75%, outn1=0, outp1=1, outn2=0, outp2=1, and1, AND2 all output 0, rst5 goes to 0 after 3 clock cycles T of SAEN5, and3 goes to 0, i.e., D0 goes to reset after 3 clock cycles T, SAEN5 goes to high level reset after 3 clock cycles T.
3. The timing generation circuit unit processes OUTP1 to OUTP2 in combination with RST5, RST, SAEN5 to generate SAEN, signal sequence DB <1:2>, and signal sequence D <3:4>.
Specifically, referring to FIG. 8, the timing generation circuit part may be designed to include 5D flip-flops D6 to D10, 2 OR gates OR1 to OR2, 1 NAND gate 1,1 inverter INV1.
The input end of the NAND1 is connected with the RST, the input end of the NAND1 is connected with the RST5, and the output end of the NAND1 is used for outputting SAEN;
the input end of the INV1 is connected with the SAEN, and the output end is used for outputting a reset signal rst;
the Clk end of D6-D10 is connected with SAEN5, and the reset end is connected with rst;
the D input end of the D6 is connected with the Q output end of the D10, and the Q output end is connected with the D input end of the D7;
The Q output end of D7 is connected with the first input end of OR1, and the reverse Q output end is used for outputting a signal DB <1>;
The input end II of OR1 is connected with OUTP1, and the output end is used for outputting a signal D <1>;
The D input end of D8 is connected with D <1>, the Q output end is connected with the input end I of OR2, and the inverted Q output end is used for outputting a signal DB <2>;
the input end II of OR2 is connected with OUTP2, and the output end is used for outputting a signal D <2>;
the D input end of D9 is connected with D <2>, and the Q output end is used for outputting a signal D <3>;
The D input end of D10 is connected with D <3>, and the Q output end is used for outputting signal D <4>.
Wherein, rst uniformly controls D6-D10, D6-D10 resets when rst is 0, and D6-D10 works when rst is 1.
Finally, DB <1>, DB <2> constitute DB <1:2>, D <3>, D <4> constitute D <3:4>.
Of course, D <1>, D <2>, D <3>, D <4> also constitute the signal sequence D <1:4>.
4. The SAR-ADC main circuit part is used for combining array voltages VCAL, SAEN5, SAENB5, OUTN 1-OUTN 2 and OUTP 1-OUTP 2 to process DB <1:2> and D <3:4> so as to generate ADC outputs OUT 1-OUT 2.
Specifically, referring to FIG. 9, the SAR-ADC main circuit portion may be designed to include 1 comparator SA1, 8D flip-flops D11-D18, 10 capacitors C11-C20, 2 exclusive OR gates XOR 1-XOR 2,1 NAND gate 0, 1 inverter NAND0, 7 OR gates OR 11-OR 17, 2 NOR gates NOR 11-NOR 12, and 1 transfer gate G0.
It should be noted that the capacitance ratio of C11-C20 is 8:8:4:4:2:2:1:1:1, so that the ADC comparison dichotomy can be applied later.
The upper plates of C11-C20 are connected together to form a signal INN2;
the positive input end of SA1 is connected with VCAL, the negative input end is connected with the first control ends INN2 and G0, the first output end is used for outputting OUT1, and the second output end is used for outputting OUT2;
The lower plate of C11 is connected with the output end of OR11, and the lower plate of C12 is connected with the output end of OR 12;
The lower plate of C13 is connected with the output end of OR13, the lower plate of C14 is connected with the output end of OR14, the lower plate of C15 is connected with the reverse Q output end of D15, the lower plate of C16 is connected with the output end of OR15, the lower plate of C17 is connected with the reverse Q output end of D17, the lower plate of C18 is connected with the output end of OR16, the lower plate of C19 is connected with VSS, and the lower plate of C20 is connected with the output end of OR 17;
The input end of OR11 is connected with OUTP1, the input end of OR11 is connected with enable signal EN, and the input end of OR11 is connected with the reverse Q output end of D11;
The input end of OR12 is connected with OUTP1, the input end of OR12 is connected with EN, and the input end of OR12 is connected with the Q output end of D12;
The input end of OR13 is connected with OUTP2, the input end of OR13 is connected with EN, and the input end of OR13 is connected with the reverse Q output end of D13;
the input end of OR14 is connected with OUTP2, the input end of OR14 is connected with EN, and the input end of OR14 is connected with the Q output end of D14;
The input end of OR15 is connected with the Q output end of D16, and the input end II is connected with EN;
the input end of OR16 is connected with the Q output end of D18, and the input end II is connected with EN;
the input end of OR17 is connected with VSS, and the input end II is connected with EN;
The reset ends of D11-D18 are connected with RST;
the input end of D11 is connected with OUT2, and the Clk end is connected with the output end of NOR 11;
the input end of D12 is connected with OUT1, and the Clk end is connected with the output end of NOR 11;
the input end of D13 is connected with OUT2, and the Clk end is connected with the output end of NOR 12;
the input end of D14 is connected with OUT1, and the Clk end is connected with the output end of NOR 12;
the input end of D15 is connected with OUT2, and the Clk end is connected with D <3>;
the input end of D16 is connected with OUT1, and the Clk end is connected with D <3>;
The input end of D17 is connected with OUT2, and the Clk end is connected with D <4>;
the input end of D18 is connected with OUT1, and the Clk end is connected with D <4>;
NOR11 has an input connected to DB <1>, and an input connected to OUTP1;
NOR12 has input one connected to DB <2>, and input two connected to OUTP2;
the input end of the INV0 is connected with the RST, and the output end of the INV0 is connected with the I of the G0;
the second inlet and outlet end of G0 is connected with RST, and the second control end is connected with VDD;
The input end of the XOR1 is connected with OUTP1, and the input end of the XOR1 is connected with OUTN1;
the input end of the XOR2 is connected with OUTP2, and the input end of the XOR2 is connected with OUTN2;
The input end of NAND0 is connected with the output end of XOR1, the input end of NAND0 is connected with the output end of XOR2, and the output end is used for outputting EN.
Wherein EN is controlled by OUTP1, OUTP2, OUTN1, OUTP2;
The lower polar plate of C11 is controlled by the output of OR11, and the lower polar plate of C12 is controlled by the output of OR 12;
The lower polar plate of C13 is controlled by the output of OR13, the lower polar plate of C14 is controlled by the output of OR 14;
the lower polar plate of C15 is controlled by the reverse Q output end of D15, the lower polar plate of C16 is controlled by the output of OR 15;
the lower polar plate of C17 is controlled by the reverse Q output end of D17, and the lower polar plate of C18 is controlled by the output of OR 16;
The lower polar plate of C19 is always connected with VSS, and the lower polar plate of C20 is controlled by output of OR 17.
It should be noted that SA1 is proposed to adopt the circuit design of FIG. 10, which includes 12 PMOS transistors P1-P12, 16 NNOS transistors N1-N16, and 1 transmission gate G1.
The grid electrode of N1 is connected with VDD, the source electrode is connected with the drain electrode of N6, the drain electrode is connected with the source electrode of N2 and the source electrode of N3;
the source electrode of N2 is connected with the drain electrode of N1 and the source electrode of N3, the grid electrode is used as the negative input end of SA1, and the drain electrode is connected with the source electrode of N4 and the control end I of G2;
the grid electrode of N3 is used as the positive input end of SA1, and the drain electrode is connected with the source electrode of the second control end N5 of G2;
the grid electrode of the N4 is connected with the grid electrode of the N5, the source electrode is connected with the drain electrode of the N2, and the drain electrode is used as an A node;
The drain electrode of N5 is used as a node B;
the grid electrode of N6 is connected with SAEN5, and the source electrode is connected with VSS;
The source electrode of N7 is connected with VSS, the drain electrode is connected with control signal ON_LATCH, and the grid electrode is connected with the grid electrode of P6;
the grid electrode of N8 is connected with the grid electrode of P1, the drain electrode is connected with the control signal OP_LATCH, and the source electrode is connected with VSS;
N9 has its source connected to VSS, its gate connected to A, and its drain connected to ON_LATCH;
The source electrode of N10 is connected with VSS, the drain electrode is connected with OP_LATCH, and the grid electrode is connected with B;
The source electrode of N11 is connected with VSS, the drain electrode is connected with ON_LATCH, and the grid electrode is connected with a control signal ON;
the grid electrode of N12 is connected with ON_LATCH, the drain electrode is connected with a control signal OP, and the source electrode is connected with VSS;
the source electrode of N13 is connected with VSS, the grid electrode is connected with OP, and the drain electrode is used for outputting OUT2;
the source electrode of N14 is connected with VSS, the grid electrode is connected with OP, and the drain electrode is connected with OP_LATCH;
n15 has its source connected to VSS, its drain connected to ON, and its gate connected to OP_LATCH;
The source electrode of N16 is connected with VSS, the grid electrode is connected with ON, and the drain electrode is used for outputting OUT1;
the source electrode of P1 is connected with VDD, the grid electrode is connected with ON_LATCH, and the drain electrode is connected with the source electrode of P3;
The grid electrode of P2 is connected with A, the drain electrode is connected with ON_LATCH, and the source electrode is connected with the drain electrode of P6;
the grid electrode of P3 is connected with B, and the drain electrode is connected with OP_LATCH;
p4 has its source connected to VDD, its drain connected to A, and its gate connected to SAENB5;
P5 has its source connected to VDD, its gate connected to SAENB5, and its drain connected to B;
The source electrode of P6 is connected with VDD, and the grid electrode is connected with OP_LATCH;
The source electrode of P7 is connected with VDD, the grid electrode is connected with ON, and the drain electrode is connected with the source electrode of P8;
the grid electrode of P8 is connected with ON_LATCH, and the drain electrode is connected with OP;
The source electrode of P9 is connected with VDD, the grid electrode is connected with OP, and the drain electrode is connected with the drain electrode of N13;
the source electrode of P10 is connected with VDD, the drain electrode is connected with the source electrode of P11, and the grid electrode is connected with OP;
the grid electrode of P11 is connected with OP_LATCH, and the drain electrode is connected with ON;
the source electrode of P12 is connected with VDD, the drain electrode is connected with the drain electrode of N16, and the grid electrode is connected with ON;
The input end and the output end of G2 are connected with SAEN5, and the input end and the output end are connected with SAENB5.
Based on the circuit structure of the SAR-ADC main circuit part:
RST is used as an operation start signal of the SAR-ADC main circuit part, wherein when RST is 1, the SAR-ADC main circuit part is in a reset stage, and when RST is 0, the SAR-ADC main circuit part is operated.
When the SAR-ADC main circuit part is in a reset stage, RST is 1, G0 is opened, INN2 is connected with VDD, the voltages of the upper electrode plates of C11-C20 are reset to VDD, and the voltages of the lower electrode plates of C11-C20 except for the lower electrode plate of C19, namely direct VSS, and the lower electrode plates of the other capacitors are reset to VDD.
When the sparsity detection circuit part starts to work, RST is 0, G0 is closed, INN2 is disconnected from VDD, and the upper electrode plates of C11-C20 are disconnected from VDD.
After the sparsity detection circuit is finished:
① Referring to fig. 11, if the sparsity of IN <0:63> is less than 50%, outn1=1, outp1=0, outn2=1, outp2=0, then, based on ADC comparison dichotomy, C12, C14, C16, C18, C20, their lower plate voltages become 0, the upper plate voltages decrease VDD/2;
After the first comparison of SA1 is finished, D <1> starts to rise, C11 and C12 are switched according to the output result of the first comparison of SA1, then the voltages of polar plates on C11 and C12 are correspondingly increased or decreased by VDD/4, and after the switching is finished, the second comparison of SA1 is carried out;
After the second comparison of SA1 is finished, D <2> starts to rise, C13 and C14 are switched according to the output result of the second comparison of SA1, then the voltages of polar plates on C13 and C14 are correspondingly increased or decreased by VDD/8, and after the switching is finished, SA1 is compared for the third time;
After the third comparison of SA1 is finished, D <3> starts to rise, C15 and C16 are switched according to the third comparison output result of SA1, then the voltages of polar plates on C15 and C16 are correspondingly increased or decreased by VDD/16, and after the switching is finished, the fourth comparison of SA1 is performed;
after the fourth comparison of SA1 is finished, D <4> starts to rise, C17 and C18 are switched according to the fourth comparison output result of SA1, then the voltages of polar plates on C17 and C18 are correspondingly increased or decreased by VDD/32, and the fifth comparison of SA1 is carried out after the switching is finished;
And after the fifth comparison of SA1 is finished, the operation of the SAR-ADC main circuit part is finished, namely the quantification of IN <0:63> is finished.
② Referring to fig. 12, if the sparsity of the input signal is between 50% -75%, outn1=0, outp1=1, outn2=1, outp2=0, then the lower plate voltages of C11, C12 remain unchanged, the lower plate voltages of C14, C16, C18, C20 become 0, the upper plate voltage decreases VDD/4 based on ADC comparison dichotomy;
After the first comparison of SA1 is finished, D <2> starts to rise, C13 and C14 are switched according to the output result of the first comparison of SA1, then the voltages of polar plates on C13 and C14 are correspondingly increased or decreased by VDD/8, and after the switching is finished, the second comparison of SA1 is carried out;
After the second comparison of SA1 is finished, D <3> starts to rise, C15 and C16 are switched according to the output result of the second comparison of SA1, then the voltages of the polar plates on C15 and C16 are correspondingly increased or decreased by VDD/16, and after the switching is finished, the third comparison of SA1 is carried out;
After the third comparison of SA1 is finished, D <4> starts to rise, C17 and C18 are switched according to the output result of the third comparison of SA1, then the voltages of the polar plates on C17 and C18 are correspondingly increased or decreased by VDD/32, and the fourth comparison of SA1 is finished after the switching;
and after the fourth comparison of SA1 is finished, the operation of the SAR-ADC main circuit part is finished, namely the quantification of IN <0:63> is finished.
③ Referring to fig. 13, if the sparseness of the input signal is greater than 75%, outn1=0, outp1=1, outn2=0, outp2=1, then the lower plate voltages of C11, C12, C13, C14 remain unchanged, the lower plate voltages of C16, C18, C20 become 0, the upper plate voltage decreases VDD/8, based on the ADC comparison dichotomy;
after the first comparison of SA1 is finished, D <3> starts to rise, C15 and C16 are switched according to the output result of the first comparison of SA1, then the voltages of polar plates on C15 and C16 are correspondingly increased or decreased by VDD/16, and after the switching is finished, the second comparison of SA1 is carried out;
After the second comparison of SA1 is finished, D <4> starts to rise, C17 and C18 are switched according to the output result of the second comparison of SA1, then the voltages of polar plates on C17 and C18 are correspondingly increased or decreased by VDD/32, and the third comparison of SA1 is finished after the switching;
And (3) finishing the third comparison of SA1, and finishing the operation of the SAR-ADC main circuit part, namely finishing the quantification of IN <0:63 >.
In sum, the input sparsity self-adaptive ADC circuit based on the circuit design can adaptively reduce the comparison period and the quantization time according to the detected array input sparsity, thereby reducing the power consumption waste and improving the quantization efficiency under the condition of unchanged precision.
Example 2
This embodiment 2 discloses an input sparsity adaptive ADC module employing the layout of the input sparsity adaptive ADC circuit as disclosed in embodiment 1. The packaging mode is a module mode, so that the popularization and the application of the circuit are easier.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. An input sparsity adaptive ADC circuit, comprising:
The sparsity detection circuit part is used for sparsity detection of array inputs IN <0:63> according to an enable signal SAEN, a regulation signal CAP_RST and reference signals VREF 1-VREF 2, and generates control signals OUTN 1-OUTN 2 and control signals OUTP 1-OUTP 2;
A sparsity control circuit unit for processing OUTN1 to OUTN2 in combination with the timing signal CLK and the reset signal RST to generate an enable signal SAEN5, an enable signal SAENB5, and a reset signal RST5;
A timing generation circuit section for processing OUTP1 to OUTP2 in combination with RST5, RST, SAEN5 to generate SAEN, signal sequence DB <1:2>, signal sequence D <3:4>, and
SAR-ADC main circuit part for combining array voltages VCAL, SAEN5, SAENB5, OUTN 1-OUTN 2, OUTP 1-OUTP 2 to process DB <1:2>, D <3:4> to generate ADC output OUT 1-OUT 2;
If the sparsity of IN <0:63> is less than 50%, outn1=1, outp1=0, outn2=1, outp2=0, and the sar-ADC main circuit generates OUT1 to OUT2 after 5 comparison periods;
If the sparsity of IN <0:63> is 50% -75%, OUTN1=0, OUTP1=1, OUTN2=1, OUTP2=0, and the SAR-ADC main circuit part generates OUT 1-OUT 2 after 4 comparison periods;
If the sparseness of IN <0:63> is greater than 75%, outn1=0, outp1=1, outn2=0, outp2=1, and the sar-ADC main circuit generates OUT1 to OUT2 after 3 comparison cycles.
2. The input sparsity adaptive ADC circuit according to claim 1, wherein the sparsity detection circuit section includes a capacitor array CIN 0~CIN63, a switch array S 0~S63, and 2 comparators SA 0,1~SA0,2;
the m+1th signal IN < m > IN CIN m upper plate connections IN <0:63>, m ε [0,63];
S m is a single-pole double-throw switch, the control end of S m is connected with CAP_RST, the fixed end is connected with the lower polar plate of CIN m, the first switching end forms a signal INN1, and the second switching end is connected with VSS;
The positive input end of SA 0,1 is connected with VREF1, the negative input end is connected with INN1, the control end is connected with SAEN, the output end I is used for outputting OUTN1, and the output end II is used for outputting OUTP1;
the positive input end of SA 0,2 is connected with VREF2, the negative input end is connected with INN1, the control end is connected with SAEN, the output end I is used for outputting OUTN2, and the output end II is used for outputting OUTP2.
3. The input sparsity adaptive ADC circuit of claim 2, wherein the SA 0,1 includes 12 PMOS transistors PM1 to PM12, 8 NMOS transistors NM1 to NM8, 1 transfer gate GM1, 1 inverter INVM1;
The grid electrode of NM1 is connected with SAEN, and the source electrode is connected with VSS;
The grid electrode of NM2 is connected with SAEN, and the source electrode is connected with VSS;
The drain electrode of NM3 is used as the output end I of SA 0,1, and the source electrode is connected with VSS;
the drain electrode of NM4 is used as the second output end of SA 0,1, and the source electrode is connected with VSS;
the grid electrode of NM5 is connected with the drain electrode of NM 1;
The grid electrode of NM6 is connected with the drain electrode of NM 2;
The drain electrode of NM7 is connected with the source electrode of NM5, the source electrode is connected with VSS, and the grid electrode is connected with the drain electrode of NM 6;
the drain electrode of NM8 is connected with the source electrode of NM6, the source electrode is connected with VSS, and the grid electrode is connected with the drain electrode of NM 5;
the gate of PM1 is connected with VSS;
the grid electrode of PM2 is connected with VREF1, and the source electrode is connected with the drain electrode of PM 1;
the grid electrode of PM3 is connected with INN1, and the source electrode is connected with the drain electrode of PM 1;
PM4 has its gate connected to SAEN, its source connected to VDD, and its drain connected to PM 1's source;
the grid electrode of PM5 is connected with VSS, the drain electrode is connected with the drain electrode of NM1, the grid electrode of PM9 and the grid electrode of NM5, and the source electrode is connected with the drain electrode of PM 2;
The grid electrode of PM6 is connected with VSS, the drain electrode is connected with the drain electrode of NM2, the grid electrode of PM10 and the grid electrode of NM6, and the source electrode is connected with the drain electrode of PM 3;
The grid electrode of PM7 is connected with the grid electrode of NM3, the source electrode is connected with VDD, and the drain electrode is connected with the drain electrode of NM 3;
The grid electrode of PM8 is connected with the grid electrode of NM4, the source electrode is connected with VDD, and the drain electrode is connected with the drain electrode of NM 4;
The grid electrode of PM9 is connected with the grid electrode of NM5, the source electrode is connected with VDD, and the drain electrode is connected with the grid electrode of PM 7;
the grid electrode of PM10 is connected with the grid electrode of NM6, the source electrode is connected with VDD, and the drain electrode is connected with the grid electrode of PM 8;
The gate of PM11 is connected with the gate of NM7, the source is connected with VDD, and the drain is connected with the gate of PM 7;
The grid electrode of PM12 is connected with the grid electrode of NM8, the source electrode is connected with VDD, and the drain electrode is connected with the grid electrode of PM 8;
The input end of INVM1 is connected with SAEN;
the control end of GM1 is connected with the drain electrode of PM2, the control end II is connected with the drain electrode of PM3, the in-out end is connected with SAEN, and the in-out end II is connected with the output end of INVM 1.
4. The input sparsity adaptive ADC circuit of claim 2, wherein the SA 0,2 includes 12 PMOS transistors PN 1-PN 12, 8 NMOS transistors NN 1-NN 8, 1 transfer gate GN1, 1 inverter INVN1;
NN1 has its gate connected to SAEN and its source connected to VSS;
NN2 has its gate connected to SAEN and its source connected to VSS;
The drain electrode of NN3 is used as the first output end of SA 0,2, and the source electrode is connected with VSS;
The drain electrode of NN4 is used as the second output end of SA 0,2, and the source electrode is connected with VSS;
The grid electrode of NN5 is connected with the drain electrode of NN 1;
the grid electrode of NN6 is connected with the drain electrode of NN 2;
the drain electrode of NN7 is connected with the source electrode of NN5, the source electrode is connected with VSS, and the grid electrode is connected with the drain electrode of NN 6;
the drain electrode of NN8 is connected with the source electrode of NN6, the source electrode is connected with the VSS gate, and the grid electrode is connected with the drain electrode of NN 5;
the grid electrode of PN1 is connected with VSS;
the grid electrode of PN2 is connected with VREF2, and the source electrode is connected with the drain electrode of PN 1;
The grid electrode of PN3 is connected with INN1, and the source electrode is connected with the drain electrode of PN 1;
PN4 has its gate connected to SAEN, source connected to VDD and drain connected to PN1 source;
The grid electrode of PN5 is connected with VSS, the drain electrode is connected with the drain electrode of NN1, the grid electrode of PN9 and the grid electrode of NN5, and the source electrode is connected with the drain electrode of PN 2;
the grid electrode of PN6 is connected with VSS, the drain electrode is connected with the drain electrode of NN2, the grid electrode of PN10 and the grid electrode of NN6, and the source electrode is connected with the drain electrode of PN 3;
PN7 has its gate connected to NN3 gate, source connected to VDD and drain connected to NN3 drain;
PN8 has its gate connected to NN4 gate, source connected to VDD and drain connected to NN4 drain;
PN9 has its gate connected to NN5, source connected to VDD and drain connected to PN 7;
PN10 has its gate connected to NN6, source connected to VDD and drain connected to PN 8;
the grid electrode of PN11 is connected with the grid electrode of NN7, the source electrode is connected with VDD, and the drain electrode is connected with the grid electrode of PN 7;
PN12 has its gate connected to NN8 gate, source connected to VDD, and drain connected to PN8 gate;
the input end of INVN is connected with SAEN;
The control end of GN1 is connected with the drain electrode of PN2, the control end is connected with the drain electrode of PN3, the in-out end is connected with SAEN, and the in-out end is connected with the output end of INVN.
5. The input sparsity adaptive ADC circuit according to claim 1, wherein the sparsity control circuit section includes 6D flip-flops D0 to D5, 3 AND gates AND1 to AND3;
The input end of the AND1 is connected with the OUTN1, the output end of the AND1 is connected with the Q output end of the D1, AND the output end of the AND1 is electrically connected with the D input end of the D2;
The input end of the AND2 is connected with the OUTN2, the output end of the AND2 is connected with the Q output end of the D2, AND the output end of the AND2 is electrically connected with the D input end of the D3;
The Clk end of D0 is connected with CLK, the reverse phase Q output end is used for outputting SAENB5 and is connected with the D input end, and the Q output end is used for outputting SAEN5;
The Clk end of D1-D5 is connected with SAEN5, and the reset end is connected with RST;
The D input end of the D1 is connected with VSS;
The Q output end of D3 is connected with the D input end of D4, the Q output end of D4 is connected with the D input end of D5, and the Q output end of D5 is used for outputting RST5;
AND the input end of the AND3 is connected with the RST, the input end of the AND3 is connected with the RST5, AND the output end of the AND3 is connected with the reset end of the D0.
6. The input sparsity adaptive ADC circuit according to claim 1, wherein the timing generation circuit section includes 5D flip-flops D6 to D10, 2 OR gates OR1 to OR2, 1 NAND gate NAND1, 1 inverter INV1;
the input end of the NAND1 is connected with the RST, the input end of the NAND1 is connected with the RST5, and the output end of the NAND1 is used for outputting SAEN;
the input end of the INV1 is connected with the SAEN, and the output end is used for outputting a reset signal rst;
the Clk end of D6-D10 is connected with SAEN5, and the reset end is connected with rst;
the D input end of the D6 is connected with the Q output end of the D10, and the Q output end is connected with the D input end of the D7;
The Q output end of D7 is connected with the first input end of OR1, and the reverse Q output end is used for outputting a signal DB <1>;
The input end II of OR1 is connected with OUTP1, and the output end is used for outputting a signal D <1>;
The D input end of D8 is connected with D <1>, the Q output end is connected with the input end I of OR2, and the inverted Q output end is used for outputting a signal DB <2>;
the input end II of OR2 is connected with OUTP2, and the output end is used for outputting a signal D <2>;
the D input end of D9 is connected with D <2>, and the Q output end is used for outputting a signal D <3>;
the D input end of D10 is connected with D <3>, and the Q output end is used for outputting a signal D <4>;
Wherein DB <1>, DB <2> constitute DB <1:2>, D <3>, D <4> constitute D <3:4>.
7. The input sparsity adaptive ADC circuit according to claim 1, wherein the SAR-ADC main circuit portion includes 1 comparator SA1, 8D flip-flops D11 to D18, 10 capacitors C11 to C20, 2 exclusive-OR gates XOR1 to XOR2, 1 NAND gate NAND0, 1 inverter NAND0, 7 OR gates OR11 to OR17, 2 NOR gates NOR11 to NOR12, 1 transfer gate G0;
the upper plates of C11-C20 are connected together to form a signal INN2;
the positive input end of SA1 is connected with VCAL, the negative input end is connected with the first control ends INN2 and G0, the first output end is used for outputting OUT1, and the second output end is used for outputting OUT2;
The lower plate of C11 is connected with the output end of OR11, and the lower plate of C12 is connected with the output end of OR 12;
The lower plate of C13 is connected with the output end of OR13, the lower plate of C14 is connected with the output end of OR14, the lower plate of C15 is connected with the reverse Q output end of D15, the lower plate of C16 is connected with the output end of OR15, the lower plate of C17 is connected with the reverse Q output end of D17, the lower plate of C18 is connected with the output end of OR16, the lower plate of C19 is connected with VSS, and the lower plate of C20 is connected with the output end of OR 17;
The input end of OR11 is connected with OUTP1, the input end of OR11 is connected with enable signal EN, and the input end of OR11 is connected with the reverse Q output end of D11;
The input end of OR12 is connected with OUTP1, the input end of OR12 is connected with EN, and the input end of OR12 is connected with the Q output end of D12;
The input end of OR13 is connected with OUTP2, the input end of OR13 is connected with EN, and the input end of OR13 is connected with the reverse Q output end of D13;
the input end of OR14 is connected with OUTP2, the input end of OR14 is connected with EN, and the input end of OR14 is connected with the Q output end of D14;
The input end of OR15 is connected with the Q output end of D16, and the input end II is connected with EN;
the input end of OR16 is connected with the Q output end of D18, and the input end II is connected with EN;
the input end of OR17 is connected with VSS, and the input end II is connected with EN;
The reset ends of D11-D18 are connected with RST;
the input end of D11 is connected with OUT2, and the Clk end is connected with the output end of NOR 11;
the input end of D12 is connected with OUT1, and the Clk end is connected with the output end of NOR 11;
the input end of D13 is connected with OUT2, and the Clk end is connected with the output end of NOR 12;
the input end of D14 is connected with OUT1, and the Clk end is connected with the output end of NOR 12;
the input end of D15 is connected with OUT2, and the Clk end is connected with D <3>;
the input end of D16 is connected with OUT1, and the Clk end is connected with D <3>;
The input end of D17 is connected with OUT2, and the Clk end is connected with D <4>;
the input end of D18 is connected with OUT1, and the Clk end is connected with D <4>;
NOR11 has an input connected to DB <1>, and an input connected to OUTP1;
NOR12 has input one connected to DB <2>, and input two connected to OUTP2;
the input end of the INV0 is connected with the RST, and the output end of the INV0 is connected with the I of the G0;
the second inlet and outlet end of G0 is connected with RST, and the second control end is connected with VDD;
The input end of the XOR1 is connected with OUTP1, and the input end of the XOR1 is connected with OUTN1;
the input end of the XOR2 is connected with OUTP2, and the input end of the XOR2 is connected with OUTN2;
The input end of NAND0 is connected with the output end of XOR1, the input end of NAND0 is connected with the output end of XOR2, and the output end is used for outputting EN.
8. The input sparsity adaptive ADC circuit of claim 7, wherein the capacitance ratio of C11 to C20 is 8:8:4:4:2:2:1:1:1.
9. The input sparsity adaptive ADC circuit according to claim 7, wherein SA1 comprises 12 PMOS tubes P1 to P12, 16 NNOS tubes N1 to N16, and 1 transmission gate G1;
the grid electrode of N1 is connected with VDD, the source electrode is connected with the drain electrode of N6, the drain electrode is connected with the source electrode of N2 and the source electrode of N3;
the source electrode of N2 is connected with the drain electrode of N1 and the source electrode of N3, the grid electrode is used as the negative input end of SA1, and the drain electrode is connected with the source electrode of N4 and the control end I of G2;
the grid electrode of N3 is used as the positive input end of SA1, and the drain electrode is connected with the source electrode of the second control end N5 of G2;
the grid electrode of the N4 is connected with the grid electrode of the N5, the source electrode is connected with the drain electrode of the N2, and the drain electrode is used as an A node;
The drain electrode of N5 is used as a node B;
the grid electrode of N6 is connected with SAEN5, and the source electrode is connected with VSS;
The source electrode of N7 is connected with VSS, the drain electrode is connected with control signal ON_LATCH, and the grid electrode is connected with the grid electrode of P6;
the grid electrode of N8 is connected with the grid electrode of P1, the drain electrode is connected with the control signal OP_LATCH, and the source electrode is connected with VSS;
N9 has its source connected to VSS, its gate connected to A, and its drain connected to ON_LATCH;
The source electrode of N10 is connected with VSS, the drain electrode is connected with OP_LATCH, and the grid electrode is connected with B;
The source electrode of N11 is connected with VSS, the drain electrode is connected with ON_LATCH, and the grid electrode is connected with a control signal ON;
the grid electrode of N12 is connected with ON_LATCH, the drain electrode is connected with a control signal OP, and the source electrode is connected with VSS;
the source electrode of N13 is connected with VSS, the grid electrode is connected with OP, and the drain electrode is used for outputting OUT2;
the source electrode of N14 is connected with VSS, the grid electrode is connected with OP, and the drain electrode is connected with OP_LATCH;
n15 has its source connected to VSS, its drain connected to ON, and its gate connected to OP_LATCH;
The source electrode of N16 is connected with VSS, the grid electrode is connected with ON, and the drain electrode is used for outputting OUT1;
the source electrode of P1 is connected with VDD, the grid electrode is connected with ON_LATCH, and the drain electrode is connected with the source electrode of P3;
The grid electrode of P2 is connected with A, the drain electrode is connected with ON_LATCH, and the source electrode is connected with the drain electrode of P6;
the grid electrode of P3 is connected with B, and the drain electrode is connected with OP_LATCH;
p4 has its source connected to VDD, its drain connected to A, and its gate connected to SAENB5;
P5 has its source connected to VDD, its gate connected to SAENB5, and its drain connected to B;
The source electrode of P6 is connected with VDD, and the grid electrode is connected with OP_LATCH;
The source electrode of P7 is connected with VDD, the grid electrode is connected with ON, and the drain electrode is connected with the source electrode of P8;
the grid electrode of P8 is connected with ON_LATCH, and the drain electrode is connected with OP;
The source electrode of P9 is connected with VDD, the grid electrode is connected with OP, and the drain electrode is connected with the drain electrode of N13;
the source electrode of P10 is connected with VDD, the drain electrode is connected with the source electrode of P11, and the grid electrode is connected with OP;
the grid electrode of P11 is connected with OP_LATCH, and the drain electrode is connected with ON;
the source electrode of P12 is connected with VDD, the drain electrode is connected with the drain electrode of N16, and the grid electrode is connected with ON;
The input end and the output end of G2 are connected with SAEN5, and the input end and the output end are connected with SAENB5.
10. An input sparsity adaptive ADC module, characterized in that it employs a layout of an input sparsity adaptive ADC circuit according to any one of claims 1-9.
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