CN119415468A - Device Driver - Google Patents

Abstract

The present invention provides a device driving device, which can send and receive commands to operate without setting addresses separately when connected to the same bus interface. The device includes a master device connected to a bus interface having a clock signal line and a data signal line and at least one slave device; each of the slave devices includes a first terminal connected to one of the clock signal line and the data signal line, and a second terminal connected to the other of the clock signal line and the data signal line; according to the signal of the master device input from the first terminal and the second terminal, the connection direction of the clock signal line is determined, and a separate address is allocated to the slave device connected in reverse.

Description

Device driving apparatus

Technical Field

The present invention relates to the technical field of device driving apparatuses, and in particular, to a device driving apparatus that enables a device to perform transmission, reception, and operation of commands through the same bus interface without separately setting an address.

The present application claims priority, its priority date is 2024, 05, 21 and priority number is 10-2024-0065749, the present application refers to the priority file mentioned above.

Background

In general, in electrical systems, interconnections are often used when information or signals are transferred between components of the system. Such an interconnection is made up of one or more signal lines, also known as buses.

For example, some systems use an I2C bus as an Inter-integrated circuit (Inter-INTEGRATED CIRCUIT; I2C) bus, i.e., bus protocol, to provide an environment for multiple ICs to communicate using fewer communication lines. The I2C bus is composed of a Serial Clock Line (SCL) for transmitting a clock and a serial data line (SDA) for serially transmitting data, which are transmitted and received according to the clock.

The I2C bus exchanges data between the IC chips using two wires, and devices connected to the I2C bus communicate through a master device and a slave device. As shown in fig. 1, the I2C bus is a serial bus protocol that can communicate with a plurality of slave devices 21, 22, 23, 24, which are connected to the master device 10 via a power line VDD and twin lines SCL, SDA, and can transmit and receive data. Thus, the I2C bus can control multiple chips in parallel with two lines.

The master device generates a clock signal that controls the transfer of data between the master device and the slave device. The master device then designates the slave address assigned by each slave device to communicate with the desired slave device. The master device specifies the address of the slave device by sending multiple bits (typically 1 byte) of information on the bus, including specifying an N-bit slave device bus address, and command bits for specifying a read or write operation. In this case, if two or more slave devices having the same address are connected to the bus, these slave devices will not be individually accessible through the master device. Thus, each device connected to the bus must have its own unique bus address to ensure proper operation of the bus. I.e. the master device and the slave device each have independent addresses. The master device sends a specified address over a data line (SDA) to invoke a particular slave device.

For example, the master device may output the address of the slave device of the communication object after creating the start condition on the bus. The slave device having the corresponding address responds with an acknowledgement signal (ACK) to start communication. During communication, the device receiving the data replies with an ACK signal. The master terminates communication with the slave by way of a stop condition being built on the bus. Thus, the master device may communicate with a particular slave device by way of a slave device address assigned to each slave device. However, when individual slave devices composed of different chips communicate data through the I2C bus, they are assigned different addresses and thus can communicate with the master device. But if two or more slave devices consisting of the same manufactured chips are connected to the bus, they may be assigned to the same slave device address, resulting in a collision.

In addition, the slave device generally uses a data signal line SDA which can be both input and output, while a clock signal line SCL is mainly used as an input. However, if these signal lines are cross-connected by mistake due to an operator's error or the like, it may result in that data transferred from the master device is not normally received. That is, since the characteristics of the I2C protocol require that the clock terminal (SCL terminal) and the data terminal (SDA terminal) must be connected in a well-defined direction to communicate, in the I2C communication, the SCL terminal and the SDA terminal of all the slave devices must be connected in the same manner.

If the SCL terminal of the slave device is connected to the data line SDA and the SDA terminal is connected to the clock line SCL, a clock and data signal connection error may result. Because the SCL terminal requires an output line to generate the clock signal, such erroneous connection may result in an inability to properly perform both data input and output operations in I2C communications. Therefore, conventionally, IC chips having different addresses are required to be used, or if IC chips having the same structure are used, difficulties in connection and address allocation are encountered, and the addresses are required to be modified by means of an internal memory so as to be correctly used. Particularly, when a plurality of slave devices are driven, the option of simultaneously using IC chips of the same configuration is limited, so that it is necessary to prepare a plurality of chips, which also causes problems in terms of inventory management. In addition, although the circuit configuration can be changed to set the address at the manufacturing stage, it is very difficult to implement structural modification for the circuit structure that has been manufactured, and thus there are manufacturing limitation difficulties.

Disclosure of Invention

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a device driving apparatus that can individually perform address assignment for slave devices connected in reverse.

In one embodiment, the present invention is directed to a device driving apparatus that can easily perform address assignment even if a plurality of slave devices of the same configuration are simultaneously employed.

In order to achieve the above object, the device driving apparatus provided by the present invention is a system including a master device and at least one slave device connected to a bus interface having a clock signal line and a data signal line, each of the slave devices including a first terminal connected to one of the clock signal line and the data signal line and a second terminal connected to the other of the clock signal line and the data signal line, determining a connection orientation of the clock signal line based on signals of the master device inputted from the first terminal and the second terminal, and assigning an individual address to the slave device connected in reverse.

Optionally, the slave device is configured such that if the first terminal is connected to the clock signal line and the second terminal is connected to the data signal line, the slave device is configured as a normally connected slave device;

If the first terminal is connected to the data signal line and the second terminal is connected to the clock signal line, the slave device is set as a reverse-connected slave device.

Alternatively, the slave device is provided with an input line and an output line at the first terminal and the second terminal, respectively, and the input and output of the data signal are normally performed in a state of normal connection or reverse connection.

Optionally, the slave device further includes an input-output switching decision module, and the input-output switching decision module determines the reverse connection state of the slave device by identifying a specific mode within a given holding time period.

Compared with the prior art, the device driving device provided by the invention has the following beneficial effects:

The device driving apparatus provided by the invention can allocate individual addresses to the slave devices connected in reverse. In addition, by adopting the device driving apparatus provided by the present invention, even if a plurality of slave devices having the same configuration are simultaneously used, address allocation can be easily performed, and thus there is an advantage in terms of inventory management.

Drawings

Fig. 1 is a block diagram of a general device driving apparatus;

FIG. 2 is a block diagram of a device driving apparatus according to an embodiment of the present invention;

Fig. 3 is a diagram showing an integrated circuit configuration of a slave device in a device driving apparatus according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating operation of a device driver apparatus according to an embodiment of the present invention;

fig. 5 is a timing diagram of the I2C protocol.

Reference numerals illustrate:

100-device driving means;

110-a master device;

120-slave device;

121a, 123 a-first terminals;

121b, 123 b-second terminals.

Detailed Description

Advantages and features of the present invention and methods of accomplishing the same may become apparent by reference to the following detailed description of embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be embodied in various different forms.

The terminology used in the description presented herein is for the purpose of describing various embodiments only and is not intended to be limiting of the invention. In this specification, the singular forms include the plural unless specifically stated otherwise. The terms "comprising" and/or "including" as used in this specification do not exclude the presence or addition of one or more other components than the described components. Throughout the specification, like reference numerals refer to like components, "and/or" encompass each of the components and any combination thereof. Although the terms "first," "second," etc. are used to describe various elements, these elements are not limited by these terms, which are merely used to distinguish one element from another element. Thus, the first component mentioned hereinafter may also be the second component within the technical concept of the present invention.

In this specification, the term "exemplary" is used to mean "used as an example or evidence. Any embodiment described as "exemplary" in this specification should not be construed as necessarily ideal or advantageous over other embodiments. Furthermore, in the terms used in this specification, "part" refers to a hardware element, such as software, FPGA or ASIC, and the "part" can take on many different roles. However, the "part" is not limited to only software or hardware. It can be configured in an addressable storage medium and also configured to regenerate one or more processors. Thus, for example, a "portion" can encompass software elements, object-oriented software elements, class elements, and task elements, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. The functionality provided for "portions" can be integrated into a fewer number of elements and "portions" or broken down into a greater number of elements and "portions. ( For example, in practice, a complex software system may contain multiple "parts" that cooperate to perform the functions of the entire system. Just like a large e-commerce platform, the user management module can be considered as a "part" and the order processing module is another "part". Sometimes, to improve the system performance, some functions that are originally scattered may be integrated into a "part", and when the system is upgraded or optimized, the functions of a "part" may be separated, so as to perform management and optimization more finely. For another example, in a hardware design of an electronic device, different circuit components may also be considered as different "parts". For example, the power management circuit is one "part" and the signal processing circuit is another "part". With the development of technology, some of the originally independent circuits may be integrated into a "part" with higher integration level, or a complex circuit "part" may be separated into several simpler parts for maintenance convenience. )

In this specification, all "parts" can be controlled by at least one processor, and operations performed by "parts" in the present invention can be performed by at least one processor. Embodiments in this specification can be described in terms of modules performing the functions or operations. A module, referred to as a "portion" or "module" in this specification, may be physically implemented in analog or digital circuitry, such as logic gates, integrated circuits, microprocessors, microcontrollers, memories, passive electronic elements, active electronic elements, optical components, hardwired circuitry, etc., and may be selectively driven by firmware and software. For example, in an advanced communication device, the module responsible for signal processing may be composed of a high-performance microprocessor and an application specific integrated circuit, and cooperatively driven by optimized firmware and software to achieve efficient data transmission and processing. For another example, in a control system of an intelligent household appliance, a module for controlling temperature regulation is perhaps implemented by a digital circuit formed by a logic gate and a microcontroller, and an accurate temperature control function is implemented by specific software and firmware.

Embodiments herein may be executed on at least one hardware device using at least one software program, and may perform network management functions to control elements. Unless defined otherwise, all terms (including technical and scientific terms) used in this specification can be understood to have meanings that are commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, there are generally terms defined in a dictionary, and in the case where no explicit specific definition is given, it should ideally not be interpreted excessively or beyond its reasonable scope.

The technical features of the present invention will be described in detail below with reference to the accompanying drawings.

The present invention aims to provide a device driving apparatus capable of assigning individual addresses to slave devices connected in reverse. In an embodiment, the present invention can easily accomplish address assignment even if a plurality of slave devices having the same configuration are simultaneously used. Specifically, fig. 2 is a block diagram of a device driving apparatus according to an embodiment of the present invention. As shown in fig. 2, the device driving apparatus provided by the present invention is a device connected to a bus interface having a clock signal line SCL and a data signal line SDA, and may be composed of an I2C communication system.

The device driver 100 may include a Master device (Master) 110 and at least one Slave device (Slave) 120 connected through a serial bus. In the present embodiment, the slave device 120 is presented as being constituted by four devices, but is not limited thereto.

Wherein the master device and the slave device are each composed of an independent integrated circuit (IC chip), each device being provided with a serial clock terminal and a serial data terminal. These devices can be connected to the clock signal line SCL and the data signal line SDA, respectively, to access the I2C bus interface. For example, in a complex industrial automation control system, such a device driver capable of assigning individual addresses to slave devices is particularly important. A plurality of sensors of the same configuration as slave devices can be accurately assigned addresses by the device driving apparatus, thereby ensuring stable and efficient operation of the system. In another example, in a network of smart home, various smart home appliances are used as slave devices, and by means of such a device driving apparatus, even if a plurality of home appliances of the same type exist at the same time, address allocation and effective communication control can be smoothly realized.

In this case, the device driving apparatus provided by the present invention may configure each device with respective terminals connectable to the clock signal line SCL and the data signal line SDA. Each terminal can have the functions of a clock terminal and a data terminal. In other words, each device can have a first terminal connected to one of the clock signal line SCL and the data signal line SDA, and a second terminal connected to the other of the clock signal line SCL and the data signal line SDA.

In general, the first terminal can be connected to the clock signal line SCL, and the second terminal can be connected to the data signal line SDA. This connection may be referred to as a normal connection. Conversely, a structure in which the first terminal is connected to the data signal line SDA and the second terminal is connected to the clock signal line SCL may be referred to as a cross-connect (or reverse-connect). In conventional systems, cross-connection may render the system inoperable if the terminals are cross-connected without the intervention of other equipment or structures. That is, the clock signal line SCL is responsible for transmitting clock signals and synchronizing data, and the data signal line SDA is responsible for transmitting actual data. If these two terminals are cross-connected, this will lead to errors in the flow of clock signals and data signals, which will likely lead to a significantly higher risk of communication failure. Therefore, the operator needs to pay attention to ensure the correctness of the normal connection mode.

As an embodiment, the device driving apparatus provided by the present invention can enable a part of slave devices to normally operate even if the slave devices are connected to each signal line by a cross connection method. The relevant content will be explained in detail later. Thus, each terminal is connected to a respective signal line, enabling the master device 110 and the plurality of slave devices 120 to communicate via the I2C bus. Further, the clock signal line SCL and the data signal line SDA can be connected to the power supply voltage VDD through a pull-up resistor Rpu.

The device driving apparatus provided by the present invention transmits a clock signal on the clock signal line SCL and transmits and receives a data signal on the data signal line SDA. In other words, the master device 110 and the slave device 120 can transmit and receive clock signals and data signals through the clock signal line SCL and the data signal line SDA. Thus, the master device 110 and the plurality of slave devices 120 are capable of operating in accordance with the I2C bus.

The master device 110 can control the plurality of slave devices 120 by means of I2C bus communication, and the plurality of slave devices 120 controlled by the master device 110 can act as drivers for external devices. However, if two or more slave devices are made up of the same IC chip (same model), these devices may have the same address. Therefore, at the time of starting up the device driving apparatus, it is necessary to assign each device a different address.

As an embodiment, the present invention provides a device driving apparatus which is characterized in that devices can be assigned to different addresses without separately setting the addresses even if connected to the same bus interface, and can transmit and receive commands to operate. For this reason, as shown in fig. 2, the first and second terminals of the first and second slave devices 121 and 122 of the plurality of slave devices 120 are normally connected to each signal line, and the connection positions of the first and second terminals of the third and fourth slave devices 123 and 124 cross and are connected to each signal line. The first slave device 121 and the third slave device 123 will be described below with emphasis on an example.

First, the first terminal 121a of the first slave device 121 can be connected to the clock signal line SCL, and the second terminal 121b can be connected to the data signal line SDA. In contrast, the first terminal 123a of the third slave device 123 can be connected to the data signal line SDA, and the second terminal 123b can be connected to the clock signal line SCL. In this way, the terminals can be connected in a cross manner by stitch exchange. The second slave device 122 and the fourth slave device 124 can also be connected in the same way. Subsequently, the device driving apparatus provided by the present invention can determine to which of the first terminal and the second terminal the clock signal line SCL is connected, and assign individual addresses to the slave devices (the third slave device 123 and the fourth slave device 124) connected in reverse, based on the signals of the master device 110 input from the first terminal and the second terminal.

According to the device driving apparatus provided by the present invention, when it is judged that the first terminal 121a of the first slave device 121 is connected to the clock signal line SCL and the second terminal 121b is connected to the data signal line SDA, the first address can be automatically set as the address of the first slave device 121.

In contrast, if it is determined that the first terminal 121a of the first slave device 121 is connected to the data signal line SDA and the second terminal 121b is connected to the clock signal line SCL, the device driving apparatus provided by the present invention can automatically set the address using the second address as the first slave device 121. If there is an assigned address, other user address values may be automatically assigned.

These first address, second address, and other user addresses can be stored in address registers within the interface module of each slave device. According to fig. 2, the first terminal 121a of the first slave device 121 is connected to the clock signal line SCL, and the second terminal 121b is connected to the data signal line SDA, so that the first address can be allocated as a normal connection configuration. Next, the device driving apparatus provided by the present invention can assign an address to the third slave device 123, as in the first slave device 121. That is, if it is determined that the first terminal 123a of the third slave device 123 is connected to the clock signal line SCL and the second terminal 123b is connected to the data signal line SDA, the device driving apparatus provided by the present invention can automatically assign the first address to the third slave device 123.

In contrast, if it is determined that the first terminal 123a of the third slave device 123 is connected to the data signal line SDA and the second terminal 123b is connected to the clock signal line SCL, the device driving apparatus of the present invention can automatically assign the second address to the third slave device 123. According to fig. 2, the first terminal 123a of the third slave device 123 is connected to the data signal line SDA, and the second terminal 123b is connected to the clock signal line SCL, so that the second address can be allocated as a cross-connection configuration. If there is an assigned address, other user address values may be automatically assigned.

Here, the first slave device 121 and the third slave device 123 are each composed of the same IC chip, although they are different in terms of whether each terminal is a normal connection or a cross connection. Similarly, the device driving apparatus provided by the present invention is capable of assigning a different address to each of the first slave device 121, the second slave device 122, the third slave device 123, and the fourth slave device 124. That is, by cross-connecting the signal lines to which the respective terminals of the devices are connected in the conventional connection manner, the third and fourth slave devices 123, 124 connected in reverse are configured and identified, and it is possible to assign individual addresses to the third and fourth slave devices 123, 124 connected in reverse.

Therefore, the device driving apparatus provided by the invention can allocate respective addresses to a plurality of slave devices using the same IC chip, thereby avoiding address collision and ensuring stable transmission of control signals.

Fig. 3 is a block diagram of an integrated circuit constituting a slave device of a device driving apparatus provided by the present invention. In other words, it shows the configuration of the device for address control. As an embodiment, the device driving apparatus provided by the present invention can be configured such that each terminal connected to the clock signal line SCL and the data signal line SDA can be connected to an input line and an output line. In general, the clock terminal (or pin) connected to the clock signal line SCL is used to receive the clock signal of the master device 110, so that the clock terminal of the slave device 120 does not need to generate a separate clock signal. The clock terminal of the slave device 120 simply receives the clock signal generated and controlled by the master device 110, so the design is relatively simple. Therefore, in most devices, the clock terminal connected to the clock signal line SCL generally does not need an output line, so that the hardware design can be simplified.

As an embodiment, the device driving apparatus provided by the present invention permits the use of existing clock terminals as data terminals at the time of cross-connection, so that both terminals are provided with an input line and an output line. As shown in fig. 3, the first terminal P1 and the second terminal P2 each connected to the clock signal line SCL and the data signal line SDA can be connected to the input line IL and the output line OL. In this case, the first terminal P1 functions as a clock terminal connected to the clock signal line SCL, and the second terminal P2 functions as a data terminal connected to the data signal line SDA. When the slave device makes the cross connection, the connection of the signal lines becomes the reverse connection, so the first terminal P1 can function as a data terminal, and the second terminal P2 can function as a clock terminal. Since the device driving apparatus provided by the present invention is provided with the input line IL and the output line OL on both the first terminal P1 and the second terminal P2, input of an output signal and input/output of a data signal can be performed. Therefore, the present invention can achieve the normal operation of the device by means of the normal signal input/output of the slave device 120 even in the case of the reverse connection by adding the connection line to the terminal, not being limited to only the position of the normal connection.

Meanwhile, the invention can normally transmit clock signals and data signals even under the reverse connection condition by connecting the connecting line with each terminal on the integrated circuit, even if other signal lines are connected with the initial terminal. As shown in fig. 3, the integrated circuit is connected to the signal lines SCL and SDA via the first and second terminals P1 and P2, and can be connected to a master device. A noise filter (GLLTCH FILTER) F, a multiplexer MUX and an interface module IB can also be connected in the circuit. The noise filter F can be designed as a pulse filter for detecting and handling signal anomalies such as power supply or signal noise.

A multiplexer MUX is a device that can selectively switch multiple input signals to a single output and that can function like a switch. Such a multiplexer can be set to connect to a specific device and disconnect from other devices according to the demand, thereby controlling the communication path. The interface module IB is capable of acting as an I2C slave controller managing communication between devices, control clock and timing signals, and managing status and control registers. As one embodiment, the interface module IB may encompass an I2C slave engine (I2C SLAVE ENGINE) and an input-output switching decision module (IO Swap Decision Block).

The I2C slave engine essentially assumes the responsibility of receiving commands from the master and providing data. In other words, it can detect the address of the slave device and maintain the required state for transmission or reception of the data signal. The partial I2C slave engine may contain a data shift register (DATA SHIFT REGISTER), an address comparator (Address Comparator), and a plurality of address registers (ADDRESS REGISTER) and be capable of transmitting and receiving data with the memory portion. The data shift register can store data transmitted or received in the I2C communication. It is used to buffer data received from the master device or to leave data to be transmitted in the slave device. The address comparator is capable of detecting the addresses and comparing the addresses from the master device with the addresses of the slave devices to determine if they match. The method is used for the slave device to receive the address sent by the master device and judge whether the slave device is called.

The address register is capable of storing an address of the slave device. When an address from the device is received, it uses the address stored in the register to compare with the received address to confirm whether itself is called. When an address is allocated, a newly allocated address can be stored. These addresses are stored in user-defined address register areas. In this embodiment, the input output switching decision module is capable of making decisions to switch data signals in the I2C communication. The input-output switching decision module can judge IO configuration, namely, determine whether the input-output direction needs to be switched. For example, the I/O switching decision block can function in the case where the third slave device 123 is cross-connected, i.e., its terminals are cross-connected to each signal line, the I/O switching decision block can decide to perform I/O switching to ensure that signals are normally transmitted and received through each terminal in the case of cross-connection of the signal lines. The input-output switching decision module may encompass an input-output management register (IO Config Register). The input/output management register is used for managing input/output directions, and can set and manage the operation of the input/output terminals.

The data may be stored in a memory.

As an embodiment, the device driving apparatus provided by the present invention is capable of identifying and assigning individual addresses to slave devices whose terminal positions to which those slave devices are connected are in a cross-connection state instead of a normal connection state. In this case, according to the device driving apparatus provided by the present invention, since the first terminal and the second terminal each have the input-output line, even in the terminal exchange state, the clock terminal is connected to the data signal line, and the data terminal is connected to the clock signal line, the transmission and reception of signals can be normally performed. Finally, the invention enables the device to be driven normally also when used in a cross-connect state.

According to the present invention, even if a plurality of IC chips of the same configuration are used as slave devices, each device can be assigned a different address. In this way, the same chip can be used instead of different chips when the driver is required. Compared with the traditional stock mode which needs to have and manage chips in various forms, the stock management can be carried out more easily. Further, according to the present invention, even in a state where the terminals of the IC chip are cross-connected, the clock signal and the data signal can be normally transmitted and received. Therefore, the equipment can be ensured to normally operate under the condition that the equipment is not caused by operator errors or intentional errors, and the working efficiency is improved.

The present invention relates to a method for easily identifying devices and assigning independent addresses in a two-wire system sharing an I2C clock signal and a data signal. Even in the case of cross-connection (i.e. address is inserted upside down) thus enabling the former normal connection and operation, the terminals of the slave device are connected to the signal lines. Fig. 4 is a flowchart of an embodiment of the present invention. Fig. 5 is a sequence diagram of the operation of the I2C protocol. With reference to these drawings, described below is a process of performing input/output configuration change condition setting by the apparatus of the present invention.

First, after the start signal is recognized, a period of time is waited (held). At this time, if the holding time is confirmed to exceed a certain target, it is recognized as an IO configuration exchange. At this time, when 1 to N times of start, hold, stop operations are performed, and when 1 to N times of start, hold, reload start, hold, stop operations are performed, they are recognized as an address exchange state, and an input/output direction is changed by changing the function of the terminal, thereby realizing normal communication in a reverse connection state. Therefore, the device driving apparatus provided by the invention can identify the specific mode, and judge whether to perform operations such as IO exchange or not by distributing a certain duration of holding time. It accesses the input-output management registers of the associated slave devices, requests a change in input-output direction, and writes values to the registers to save and apply the change settings made. Here, the device driving apparatus provided by the present invention is provided with an input-output line for each slave device terminal, and can perform normal operation even if an input-output configuration is changed. In other words, in general, if a change occurs in the function of a terminal, normal communication is likely to be impossible, however, the present invention configures an input-output line for each terminal, so that normal operation can be achieved also in the reverse connection state. Thus, according to the present invention, for a cross-connected slave device, the I/O configuration can be changed and can normally operate in a cross-connected state. In some embodiments, in case the IO Config settings have been swapped, different addresses will be allocated, so normal operation can be performed in case of a reverse connection, regardless of address.

As described above, the device driving apparatus provided by the present invention can assign individual addresses to slave devices connected in reverse. In addition, by adopting the device driving apparatus provided by the invention, even if the slave devices with the same configuration are used at the same time, address allocation can be easily performed, so that the problem of stock management that a plurality of chips are required to be prepared conventionally is solved, and the advantage in stock management is brought about.

Various embodiments of the invention can be implemented in the form of software containing one or more instructions stored on a storage medium (e.g., memory) readable by a processor of a device (e.g., a vehicle-generated data recording device or computer). For example, a processor of the device may be capable of invoking and executing at least one instruction stored in a storage medium. This enables the device to perform at least one function in accordance with the invoked at least one instruction. These one or more instructions may encompass code generated by a compiler or code executable by an interpreter. The readable device storage medium can be provided in the form of a non-volatile storage medium. Herein, a "nonvolatile storage medium" refers to a device that actually exists, merely that no signal (e.g., electromagnetic wave) is contained, and it is not distinguished whether data is permanently stored or temporarily stored in the storage medium. For example, a "non-volatile storage medium" can include a buffer for temporarily storing data.

Methods according to various embodiments disclosed herein can be embodied in a computer program product and can be used as an article of commerce for transactions between sellers and buyers. The computer program product can be distributed in the form of a device readable storage medium, such as a compact disc read only memory (CD-ROM), or can be distributed (e.g., downloaded or uploaded) directly between two user devices, such as a smart phone, or online, through an application Store, such as a Play Store ^TM. For online distribution, at least a portion of the computer program product (e.g., the downloadable application) can be stored or temporarily generated in a device readable storage medium (e.g., memory) of a manufacturer's server, an application store's server, or a relay server.

The above description is merely illustrative of the technical idea of the present invention, and a person having ordinary skill in the art can make various modifications and variations within the general knowledge of the technical field to which the present invention pertains without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed according to the present invention are not intended to limit the technical idea of the present invention, but are intended to be illustrative. These examples do not limit the scope of the technical idea of the present invention.

Claims (3)

1. A device driving device, characterized in that it includes a master device and at least one slave device connected to a bus interface having a clock signal line and a data signal line; each of the slave devices includes a first terminal connected to one of the clock signal line and the data signal line, and a second terminal connected to the other of the clock signal line and the data signal line; based on the signal of the master device input from the first terminal and the second terminal, the connection direction of the clock signal line is determined, and a separate address is allocated to the reversely connected slave device. 2. The device driving apparatus according to claim 1, wherein the slave device is set according to the following characteristics: If the first terminal is connected to the clock signal line and the second terminal is connected to the data signal line, the slave device is set as a normally connected slave device; If the first terminal is connected to the data signal line and the second terminal is connected to the clock signal line, the slave device is set as a reversely connected slave device. 3. The device driver according to claim 1 is characterized in that the slave device also includes an input-output exchange decision module, and the input-output exchange decision module determines the reverse connection state of the slave device by identifying a specific pattern within a given holding time.