CN119415472A - A memory management communication interface and method for on-chip network and SRIO protocol - Google Patents

Abstract

The present invention relates to a memory management communication interface and method for on-chip network and SRIO protocol. The memory management communication interface comprises a master interface module, a slave interface module and an output control module. On one hand, the memory management communication interface can receive a request in the form of an AXI bus from SRIO, pack it into a request packet in the form of an on-chip network, send it to storage particles through the on-chip network, control the storage particles to perform memory management and read-write operations, and after completion, receive a response packet of whether the operation is successful through the on-chip network, unpack it into a response in the form of an AXI bus, and send it to SRIO; on the other hand, the memory management communication interface can accept a read-write request packet sent by a host through the on-chip network, unpack it into a request in the form of an AXI bus, and send it to SRIO. After completion, receive a response in the form of an AXI bus from SRIO, convert it into a response packet in the form of an on-chip network, and send it to the host that initiates the request through the on-chip network.

Description

Memory management communication interface and method for network-on-chip and SRIO protocol

Technical Field

The invention relates to the technical field of integrated circuit communication, in particular to a memory management communication interface and method oriented to network on chip and SRIO protocol.

Background

In recent years, the development cost of integrated circuit chips has been dramatically increased due to moore's law, and the cycle of chip design and manufacturing has been greatly shortened due to the advent of chip technology in specific fields. The technology relies on the network-on-chip to integrate different bare chips, and SRIO accesses the remote storage particles through the communication interface and the network-on-chip to perform read-write operation;

However, at present, the communication interface has the problem of low storage resource utilization rate when accessing the far-end storage particles, and when a plurality of hosts access the storage particles through the network-on-chip, the written data are easy to be illegally accessed and changed, so that the memory management communication interface facing the network-on-chip and SRIO protocol is needed to be provided, the problem is solved, the storage resource utilization rate can be improved when the network-on-chip transmits a multi-host request, and the performance of the multi-core interconnection network system is improved.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides a memory management communication interface oriented to network on chip and SRIO protocol, where the memory management communication interface is connected to SRIO and connected to storage particles and a host respectively through the network on chip, and the memory management communication interface includes:

the slave interface module comprises a slave logic judging unit and a slave data converting unit, wherein the slave data converting unit receives application, sharing, releasing, reading and writing requests through AW and W channels in an AXI bus form, analyzes information necessary for one-time request events such as event types, event codes, event addresses, writing data and the like, packages the information into a specified format, and writes the information into the slave logic judging unit;

The system comprises a main interface module, a first data conversion unit, a second data conversion unit, a third data conversion unit, a first data conversion unit, a second data conversion unit and a third data conversion unit, wherein the main interface module comprises a main logic judgment unit and a main data conversion unit, the main data conversion unit receives necessary information of a write request from the main logic judgment unit, initiates transmission to a write request address through a AXImAW channel, writes write data into an SRIO through a AXImW channel, initiates transmission to an AXI address notified by write request information given in initial configuration through a AXImAW channel after the write request is completed, and sends the content notified by the write request information to the SRIO through a AXImW channel;

The system comprises a master interface module, an output control module, a request packet from the slave interface module, a confirmation packet from the master interface module, a request response packet, a memory access response packet, a write response packet and a read confirmation packet, wherein the request packet comprises an application, sharing, releasing, writing and reading request packet, and the read response packet from the master interface module is subjected to multiplexing gating to solve output conflicts.

In one embodiment of the invention, the memory management communication interface receives an AXI bus type request from an SRIO, packages the request into an AXI bus type request packet, sends the request packet to a storage granule through an on-chip network, controls the storage granule to perform memory management and read-write operation, receives a response packet of whether the operation is successful or not through the on-chip network after the completion, unpacks the response packet into the AXI bus type request, sends the response packet to the SRIO, and receives a read-write request packet sent by a host through the on-chip network, unpacks the request into the AXI bus type request, sends the request to the SRIO, receives the AXI bus type response from the SRIO after the completion, converts the response packet into an on-chip network type response packet, and sends the response packet to the host which initiates the request through the on-chip network.

In one embodiment of the invention, the data input/output port in the form of an AXI bus in the slave interface module is connected with the SRIO, the data output port in the form of a network-on-chip facing is connected with the output control module, the data input/output port in the form of an AXI bus in the master interface module is connected with the SRIO, the data output port in the form of a network-on-chip facing is connected with the output control module, and the data input port in the form of a network-on-chip facing is connected with the network-on-chip.

In one embodiment of the invention, the data input/output port in the form of an AXI bus in the slave interface module is connected with the SRIO, the data output port in the form of a network-on-chip facing is connected with the output control module, the data input/output port in the form of an AXI bus in the master interface module is connected with the SRIO, the data output port in the form of a network-on-chip facing is connected with the output control module, and the data input port in the form of a network-on-chip facing is connected with the network-on-chip.

In one embodiment of the present invention, the slave logic judging unit is composed of address mapping logic, data encapsulation logic, retransmission logic and readout control state machine;

the method comprises the steps of receiving network-on-chip coding configuration information from a data conversion unit from a logic judgment unit, completing configuration of the network-on-chip, wherein the information is used as coding of a transmitting end network-on-chip and is necessary information for address mapping and data packet encapsulation, receiving information necessary for request events of application, sharing, release, reading and writing from the data conversion unit, completing address mapping according to the information obtained through analysis, encapsulating the data packet into a request packet in a form facing the network-on-chip, outputting the request packet, buffering the output request packet into a retransmission buffer area, timing after the output is completed, triggering retransmission, outputting the data packet in the retransmission buffer area again, timing again after retransmission, and sending a retransmission failure notification signal only when the occupation of the retransmission buffer area is finished, continuing to receive the request information from the data conversion unit from the logic judgment unit, and encapsulating and outputting the next data packet.

In one embodiment of the present invention, a master port of an AXI bus in the master data conversion unit is interconnected with a slave port of the SRIO, the master data conversion unit is interconnected with an input/output port of the slave data conversion unit, the master data conversion unit is interconnected with an input/output port of the master logic determination unit, the master logic determination unit is interconnected with an input/output port of the slave logic determination unit, an output port of the master logic determination unit is connected with the output control module, and an input port of the master logic determination unit is connected with an output port of the network on chip.

In one embodiment of the invention, the main logic judging unit consists of check logic, memory management logic, unpacking and data encapsulation logic, acknowledgement packet generation logic, read response generation logic, occupation/retransmission handshake logic and main interface logic judging control state machine, wherein the main logic judging unit receives acknowledgement packets through an input port of the network on chip, the acknowledgement packets comprise application response packets, memory access response packets, write response packets and read acknowledgement packets, after unpacking and verification, occupation release notification information is sent to the slave logic judging unit, so that occupation of a retransmission buffer area in the slave logic judging unit is released, the release notification information is written into the main data converting unit, the read response packets and the shared interrupt packets are received through an input port of the network on chip, necessary information is written into the main data converting unit after unpacking and verification, the necessary information is written into the main data converting unit through an input port of the network on chip, the necessary information is written into the main data converting unit after unpacking and verification, the write response packets and the read acknowledgement packets are sent through an output port of the network on chip, the read response packets from the main data converting unit are received, the data from the main data converting unit is read into the necessary information receiving failure notification packet after the read response packets are received and the read response packets are received from the main data converting unit and the main data converting unit is read failure information and the necessary data packet is read from the main data converting unit.

In one embodiment of the present invention, the main data conversion unit is composed of a AXImAW channel control state machine, a AXImW channel control state machine, a AXIm B channel control state machine, a AXImAR channel control state machine, a AXIm R channel control state machine, data encapsulation logic, IO interrupt logic, data analysis logic, and a main interface data conversion control state machine, and the main data conversion unit receives necessary information of a read request from the main logic judgment unit, initiates transmission to a read request address through a AXImAR channel, then reads back the read data through a AXIm R channel, encapsulates the read data into a specific format and writes the read request into the main logic judgment unit, receives the necessary information of the read response from the main logic judgment unit, sends the read response information and the read response data to an initial configuration through a AXImAW channel to an AXI address, receives notification information including retransmission failure notification information, shared write notification information, and occupation release notification information from the main logic judgment unit, sends the corresponding notification information of the type to the initial configuration to an AXI address through a AXIm W channel, sends the corresponding information to the SRXI address through a AXIm W channel, and sends the received request to the SRIO through a AXIm W from the initial configuration to the SRIO.

In one embodiment of the invention, the output control module performs arbitration and multi-path gating by taking the data packet as a unit, performs arbitration according to the pre-priority when two or more packet header flits are received simultaneously, and takes the output port for the path with higher priority before the whole data packet is output, and waits for the next arbitration for the data packet with lower priority, wherein the arbitration policy is that the request with the least recently obtained output authority has the highest priority.

The invention also provides a memory management communication method facing the network on chip and the SRIO protocol, which is realized according to a memory management communication interface and comprises the following steps:

Step S1, after each reset, the memory management communication interface receives initial configuration information from SRIO through AXIs AW channels and AXIs W channels, and completes network-on-chip coding configuration, reading response receiving address, interrupt information receiving address, retransmission failure receiving address, occupation release receiving address, shared writing notification receiving address, writing request notification receiving address and request received notification receiving address;

Step S2, receiving memory management and read-write requests through AXIs AW channels and AXIs W channels, and packaging the requests into request packets in a network-on-chip-oriented form, wherein the request packets comprise application, sharing, release, read-write request packets;

Step S3, completing the transmission of write response, read data and various notification information through AXImAW channels and AXIm W channels, wherein the notification information comprises retransmission failure notification, occupation release notification, shared write notification, write request information notification and request received notification;

s4, receiving a read-write request packet through an on-chip network-oriented input port, and executing corresponding operation according to the request type after unpacking and verification;

Step S5, receiving response packets including application response packets, access response packets, write response packets, read confirmation packets, read response packets and shared interrupt packets through the network-on-chip input port, and executing corresponding operations according to response types after unpacking and verification;

And S6, setting a time-out retransmission function by the memory management communication interface, wherein a retransmission buffer zone caches a last request packet sent by a network-on-chip output port, and triggering retransmission and sending out the request packet in the retransmission buffer zone again if the corresponding response packet is not received within a set time after the request packet is sent out.

Compared with the prior art, the memory management communication interface has the advantages that the memory management communication interface adopts a parallel processing structure, and can not only send memory management and read-write requests, but also receive read-write requests of a host in the communication of a multi-core internet system.

Drawings

In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings.

Fig. 1 is an application scenario diagram of a memory management communication interface facing a network on chip and SRIO protocol provided by the present invention.

Fig. 2 is a schematic structural diagram of a memory management communication interface facing a network on chip and an SRIO protocol provided by the present invention.

Fig. 3 is a schematic diagram of the structure of the slave logic conversion unit according to the present invention.

Fig. 4 is a schematic structural diagram of the slave data conversion unit according to the present invention.

Fig. 5 is a schematic diagram of the structure of the main logic conversion unit provided by the present invention.

Fig. 6 is a schematic structural diagram of the main data conversion unit provided by the present invention.

Detailed Description

Example 1

As shown in fig. 1 and fig. 2, the present embodiment provides a memory management communication method for a network on chip and an SRIO protocol, which is implemented according to a memory management communication interface, and includes the following steps:

Step S1, after each reset, the memory management communication interface receives initial configuration information from SRIO through AXIsAW channels and AXIs W channels, and completes network-on-chip coding configuration, reading response receiving address, interrupt information receiving address, retransmission failure receiving address, occupation release receiving address, shared writing notification receiving address, writing request notification receiving address and request received notification receiving address;

step S2, receiving memory management and read-write requests through AXIsAW channels and AXIsW channels, and packaging the requests into request packets in a network-on-chip-oriented form, wherein the request packets comprise application, sharing, release, read-write request packets;

Step S3, completing the transmission of write response, read data and various notification information through AXImAW channels and AXImW channels, wherein the notification information comprises retransmission failure notification, occupation release notification, shared write notification, write request information notification and request received notification;

s4, receiving a read-write request packet through an on-chip network-oriented input port, and executing corresponding operation according to the request type after unpacking and verification;

Step S5, receiving response packets including application response packets, access response packets, write response packets, read confirmation packets, read response packets and shared interrupt packets through the network-on-chip input port, and executing corresponding operations according to response types after unpacking and verification;

And S6, setting a time-out retransmission function by the memory management communication interface, wherein a retransmission buffer zone caches a last request packet sent by a network-on-chip output port, and triggering retransmission and sending out the request packet in the retransmission buffer zone again if the corresponding response packet is not received within a set time after the request packet is sent out.

Example two

The invention also provides a memory management communication interface oriented to the network-on-chip and the SRIO protocol, which realizes transfer transmission between the network-on-chip and the SRIO. Referring to the application scenario diagram shown in fig. 1, the memory management communication interface is connected to the SRIO, and is connected to the storage granule and the host through the network on chip, respectively.

The memory management communication interface can receive requests in an AXI bus form from SRIOs, package the requests into request packets in an AXI bus form facing the network on chip, send the request packets to the storage granules through the network on chip, control the storage granules to carry out memory management and read-write operation, receive response packets whether the operation is successful or not through the network on chip after the completion, unpack the response packets into the AXI bus form and send the response packets to the SRIOs, can receive the read-write request packets sent by a host through the network on chip, unpack the request packets into the AXI bus form and send the request packets to the SRIOs, receive the response packets in the AXI bus form from the SRIOs after the completion, convert the response packets into response packets facing the network on chip type and send the response packets to the host which initiates the requests through the network on chip.

Referring to fig. 2, the internal structure diagram of the memory management communication interface is shown, where the memory management communication interface mainly includes a slave interface module, a master interface module and an output control module.

Next, the following are specifically introduced to the three modules in the memory management communication interface respectively:

1. Slave interface module

Specifically, the slave interface module mainly comprises a slave logic judging unit and a slave data converting unit.

Specifically, the slave data conversion unit mainly comprises AXIsAW channel control state machine, AXIs W channel control state machine, AXIs B channel control state machine and data encapsulation logic, please refer to the structure diagram of the slave data conversion unit shown in fig. 3. And receiving application, sharing, releasing, reading and writing requests through AW and W channels in an AXI bus form, analyzing information necessary for one-time request events such as event types, event codes, event addresses, writing data and the like, packaging the information into a specified format, and writing the information into a slave logic judging unit. The AXIsAW channel control state machine, AXIs W channel control state machine, AXIs B channel control state machine and data encapsulation logic are described as follows:

(one) AXIsAW channel control state machine

The AXIsAW channel control state machine is responsible for controlling the AXIsAW channel to process data, outputting control signals to the AXIs W channel and receiving control signals from the AXIs B channel. After reset, the initialization of the relevant signals is completed, and the sawready and AXIs AW channel completion signals are pulled low. If it is detected in this state that the AXIs B-channel transmission completion signal is pulled high, the AXIsAW-channel transmission is started, and the sawready signal is pulled high. If the AXIsAW channel handshake is detected to be successful, AXIsAW channel transmission is completed, the awready signal is pulled down, the AXIsAW channel completion signal is pulled up, and the next AXIsAW channel transmission is waited to be started.

(Two) AXIs W channel control State machine

The AXIs W channel control state machine is responsible for controlling the AXIs W channel to process data, outputting control signals to the AXIs B channel and receiving control signals from the AXIs AW channel. And finishing the receiving and analyzing of the AXI writing data, outputting initial configuration information and a notification that the initiating request is received to the main data conversion unit, and controlling the data encapsulation logic to finish the data encapsulation and the data writing of the slave logic judgment unit.

After reset, the initialization of the relevant signals is completed, and the swready signals are pulled up. If the AXIs W-channel handshake is detected to be successful, initial configuration data are written into the main data conversion unit, and the read response AXI address, the IO interrupt enable bit, the IPCGR interrupt enable bit and the duration period number of the IO interrupt high-level pulse are registered. If the successful writing is detected and the AXIs W channel handshake is successful in this state, the retransmission failure notification AXI address and the occupancy release notification AXI address are registered. If it is detected that AXIs W channel handshakes are successful, the DMA end notification AXI address and the sharing notification AXI address are registered. If AXIs W channel handshake is detected to be successful and burst transmission is finished, the AXI address is informed of the register write request information and the AXI address is informed of the request received. If AXIs W channel handshake is detected to be successful and burst transmission is finished, the swready signal is pulled down, an AXI transmitting address of IPCGR interrupt information is registered, and initialization configuration is completed.

Initializing AXIs W the channel related signal and the write control signal, and if detecting that the AXIs W channel transmission completion signal is pulled high, starting AXIs W channel transmission and pulling up swready signal. If the AXIs W channels handshake is detected to be successful, AXIs W channels transmission is completed, swready signals are pulled down, AXIs W channels transmission completion signals are pulled up, and the next AXIs W channel transmission is waited for.

(III) AXIs B channel control State machine

The AXIs B channel control state machine is responsible for controlling the AXIs B channel to process data, outputting control signals to the AXIsAW channel and receiving control signals from the AXIs W channel. After resetting, initializing the related signals, and if detecting that the signal of AXIs W channels is transmitted to be high, starting AXIs B channels to transmit and pulling up sbvalid signals. If the AXIs B channels handshake is detected to be successful, AXIs B channels transmission is completed, sbvalid signals are pulled down, AXIs B channels transmission completion signals are pulled up, and the next AXIs B channel transmission is waited for.

(IV) data encapsulation logic

The data packing logic packs the data from the AXIs W channels in a specific format and outputs the write data to the slave logic judging unit.

Specifically, the slave logic judging unit mainly comprises address mapping logic, data encapsulation logic, retransmission logic and a read control state machine, and please refer to the structure diagram of the slave data converting unit shown in fig. 3. The method comprises the steps of receiving network-on-chip coding configuration information from a data conversion unit from a logic judgment unit, completing configuration of the network-on-chip, wherein the information is used as coding of a transmitting end network-on-chip and is necessary information for address mapping and data packet encapsulation, receiving information necessary for request events of application, sharing, release, reading and writing from the data conversion unit, completing address mapping according to the information obtained through analysis, encapsulating the data packet into a request packet in a form facing the network-on-chip, outputting the request packet, buffering the output request packet into a retransmission buffer area, timing after the output is completed, triggering retransmission, outputting the data packet in the retransmission buffer area again, timing again after retransmission, and sending a retransmission failure notification signal only when the occupation of the retransmission buffer area is finished, continuing to receive the request information from the data conversion unit from the logic judgment unit, and encapsulating and outputting the next data packet. Address mapping logic, data encapsulation logic, retransmission logic, and read control state machine are respectively described as follows:

(one) Address mapping logic

The address mapping logic receives the read data from the data conversion unit, parses the read data into routing information required for encapsulating the network-on-chip data packet according to a specific format, and outputs the parsed routing information to the data encapsulation logic.

(II) memory management logic

The data encapsulation logic encapsulates the routing information from the address mapping logic and the read data from the data conversion unit according to a specific format, and the read control state machine controls the encapsulation of the data encapsulation logic and the output direction of the encapsulation packet, and outputs the encapsulation packet to the retransmission logic on one hand and the output control module on the other hand.

(III) retransmission logic

The retransmission logic receives the package output by the data package logic and writes the package into the retransmission buffer area, receives the occupation release notification signal and the retransmission failure signal to time, and controls the data writing and the data reading of the retransmission buffer area after a certain time is exceeded. And outputting the data read out by the retransmission buffer area to an output control module, and generating a retransmission failure signal to be output to a main logic judging unit if the data still fails after retransmission.

(IV) readout control State machine

The read control state machine receives the occupation release signal and the retransmission failure signal from the main logic judging unit, controls the slave data converting unit to read data, and controls the data packaging of the data packaging logic and the output direction of the packaging package.

2. Main interface module

Specifically, the main interface module mainly comprises a main logic judging unit and a main data converting unit.

The main logic judging unit receives a response packet through an input port of the network on chip, and comprises an application response packet, a memory response packet, a write response packet, a read acknowledgement packet, a read response packet and a shared interrupt packet, and after checking and unpacking the application response packet, the memory response packet, the write response packet and the read acknowledgement packet, handshake is completed through the occupation release/retransmission failure handshake logic and the slave logic judging unit, so that occupation of a retransmission buffer area in the slave logic judging unit is released, information required by retransmission failure notification is written into the main data converting unit, and after checking and unpacking the read response packet and the shared interrupt packet, necessary information is written into the main data converting unit. The check logic, the unpacking logic, the occupation release/retransmission failure handshake logic and the main interface logic judgment control state machine are respectively introduced as follows:

First check logic

The check logic receives response packets from the network on chip, including an application response packet, a memory access response packet, a write response packet and a read acknowledgement packet, a read response packet and a shared interrupt packet. And checking the integrity of the data packet format of all the response packets, directly discarding the response packets with non-format integrity, and informing a main interface logic to judge and control the state machine to interrupt the unpacking of the response packets.

(II) unpacking logic

The unpacking logic receives response packets from the network on chip, including an application response packet, a memory access response packet, a write response packet and a read acknowledgement packet, a read response packet and a shared interrupt packet. And after unpacking the application response packet, the access response packet, the write response packet and the read confirmation packet, outputting the response packet type to the main interface logic judgment control state machine, checking and unpacking the read response packet and the shared interrupt packet, and writing necessary information into the main data conversion unit. And receiving interrupt unpacking information from the main interface logic judgment control state machine, and performing next unpacking.

(III) occupy Release/retransmission failure handshake logic

The occupation release/retransmission failure handshake logic receives control information from the master interface logic judging control state machine and completes handshake with an occupation release signal from the slave logic judging unit, so that occupation of a retransmission buffer area in the slave logic judging unit is released. Handshake is completed with the retransmission failure signal from the slave logic judging unit, thereby writing information required for retransmission failure notification into the master data converting unit.

(IV) the main interface logic judges and controls the state machine

The master interface logic judges and controls the state machine to receive interrupt unpacking information from the check logic and control the process and interrupt of the unpacking logic, receives necessary information from the unpacking logic and controls the handshake between the occupation release/retransmission failure handshake logic and the slave logic judging unit, receives successful handshake information from the occupation release/retransmission failure handshake logic and controls the information required by retransmission failure notification to be written into the master data conversion unit.

Specifically, the main data conversion unit mainly comprises a AXIm AW channel control state machine, a AXIm W channel control state machine, data encapsulation logic and a main interface data conversion control state machine, and the main data conversion unit receives necessary information of a read response from the main logic judgment unit, initiates transmission to a read response AXI address through a AXIm AW channel, sends the read response information and the read response data to the SRIO in a specified format through a AXIm W channel, receives notification information including retransmission failure notification information and shared write notification information from the main logic judgment unit, initiates transmission to a notification information AXI address corresponding to a notification type through a AXIm AW channel, and sends the notification information corresponding to the notification type to the SRIO in a specified format through a AXIm W channel. The AXIm AW channel control state machine, AXIm W channel control state machine, data encapsulation logic, and main interface data conversion control state machine are described as follows:

(one) AXIm AW channel control state machine

The AXIm AW channel control state machine controls the necessary information and notification information of the read response to initiate transmission to the corresponding AXI address. After reset, initializing each signal of AXIm AW channels, pulling up mawvalid signals, starting AXIm AW channel transmission, if AXIm AW channel handshake is detected to be successful, finishing AXIm AW channel transmission, pulling down mawvalid signals, and waiting for next starting AXIm AW channel transmission.

(Two) AXIm W channel control State machine

The AXIm W channel control state machine controls to send the read response information, the read response data and the notification information of the corresponding notification type to the SRIO in a prescribed format. After reset, initializing each signal of AXIm W channels, pulling up mwvalid signals, starting AXIm W channel transmission, if AXIm W channel handshake is detected to be successful, finishing AXIm W channel transmission, pulling down mwvalid signals, and waiting for next starting AXIm W channel transmission.

(III) data encapsulation logic

The data encapsulation logic receives the notification information from the main interface logic judging unit and the necessary information of the read response, encapsulates the information according to a specific format and outputs the information to the AXIm W channel control state machine.

(IV) Main interface data conversion control State machine

The main interface data conversion control state machine receives the notification information from the main interface logic judging unit and the necessary information of the read response packet, and controls AXImAW the channel control state machine to initiate transmission to the notification information AXI address and the read response AXI address corresponding to the notification type.

3. Output control module

The output control unit is used for feeding back the received memory management response packet or the response packet from the DDR storage grain to the network on chip, when the memory management response packet and the response packet from the DDR storage grain are received at the same time, priority arbitration is carried out on the response packet according to the pre-priority, the response packet with higher priority is fed back to the network on chip, the response packet with lower priority waits for the next priority arbitration, wherein the pre-priority is a fixed priority, and the response packet from the DDR storage grain has higher priority.

The memory management communication interface and the memory management communication method provided by the embodiment solve the relocation problem caused by the fact that the multi-core interconnection network system needs to allocate the free space and the free position is uncertain due to multi-event access, improve the access efficiency, solve the conflict problem of large-data-volume access of a plurality of events of the multi-core interconnection network system, improve the resource utilization rate of the system, solve the data loss and even system breakdown caused by the interaction among different access events of the multi-core interconnection network system due to the fact that the address space is not isolated, and improve the safety and the stability of the system.

It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.

Claims (10)

1. The memory management communication interface is connected with the SRIO and is respectively connected with the storage particles and the host through the network on chip, and the memory management communication interface comprises:

the slave interface module comprises a slave logic judging unit and a slave data converting unit, wherein the slave data converting unit receives application, sharing, releasing, reading and writing requests through AW and W channels in an AXI bus form, analyzes information necessary for one-time request events such as event types, event codes, event addresses, writing data and the like, packages the information into a specified format, and writes the information into the slave logic judging unit;

The system comprises a main interface module, a first data conversion unit, a second data conversion unit, a third data conversion unit, a first data conversion unit, a second data conversion unit and a third data conversion unit, wherein the main interface module comprises a main logic judgment unit and a main data conversion unit, the main data conversion unit receives necessary information of a write request from the main logic judgment unit, initiates transmission to a write request address through a AXImAW channel, writes write data into an SRIO through a AXIm W channel, initiates transmission to an AXI address notified by write request information given in initial configuration through a AXImAW channel after the write request is completed, and sends the content notified by the write request information to the SRIO through a AXIm W channel;

The system comprises a master interface module, an output control module, a request packet from the slave interface module, a confirmation packet from the master interface module, a request response packet, a memory access response packet, a write response packet and a read confirmation packet, wherein the request packet comprises an application, sharing, releasing, writing and reading request packet, and the read response packet from the master interface module is subjected to multiplexing gating to solve output conflicts.

2. The memory management communication interface of claim 1, wherein the memory management communication interface receives an AXI bus type request from an SRIO, packages the request into an on-chip network type request packet, sends the request packet to a storage granule through an on-chip network, controls the storage granule to perform memory management and read-write operation, receives a response packet whether the operation is successful through the on-chip network after the completion, unpacks the response packet into the AXI bus type request, sends the response packet to the SRIO, and receives a read-write request packet sent by a host through the on-chip network, unpacks the request into the AXI bus type request, sends the request to the SRIO, receives an AXI bus type response from the SRIO after the completion, converts the response packet into an on-chip network type response packet, and sends the response packet to the host which initiates the request through the on-chip network.

3. The memory management communication interface of claim 1, wherein the AXI bus type data input/output port of the slave interface module is connected with the SRIO, the network-on-chip type data output port is connected with the output control module, the AXI bus type data input/output port of the master interface module is connected with the SRIO, the network-on-chip type data output port is connected with the output control module, and the network-on-chip type data input port is connected with the network-on-chip.

4. The memory management communication interface of claim 1, wherein the slave data conversion unit comprises AXIs AW channel control state machine, AXIs W channel control state machine, AXIs B channel control state machine, and data encapsulation logic, wherein the slave port of the AXI bus in the slave data conversion unit is connected with the master port of the SRIO, the slave data conversion unit is connected with the input and output ports of the master data conversion unit, the output port of the slave data conversion unit is connected with the input port of the slave logic judgment unit, the slave logic judgment unit is connected with the input and output ports of the master logic judgment unit, and the output port of the slave logic judgment unit is connected with the output control module.

5. The memory management communication interface of claim 1, wherein the slave logic determination unit is comprised of address mapping logic, data encapsulation logic, retransmission logic, and a read control state machine;

the method comprises the steps of receiving network-on-chip coding configuration information from a data conversion unit from a logic judgment unit, completing configuration of the network-on-chip, wherein the information is used as coding of a transmitting end network-on-chip and is necessary information for address mapping and data packet encapsulation, receiving information necessary for request events of application, sharing, release, reading and writing from the data conversion unit, completing address mapping according to the information obtained through analysis, encapsulating the data packet into a request packet in a form facing the network-on-chip, outputting the request packet, buffering the output request packet into a retransmission buffer area, timing after the output is completed, triggering retransmission, outputting the data packet in the retransmission buffer area again, timing again after retransmission, and sending a retransmission failure notification signal only when the occupation of the retransmission buffer area is finished, continuing to receive the request information from the data conversion unit from the logic judgment unit, and encapsulating and outputting the next data packet.

6. The memory management communication interface of claim 1, wherein the master port of the AXI bus in the master data conversion unit is interconnected with the slave port of the SRIO, the master data conversion unit is interconnected with the input/output port of the slave data conversion unit, the master data conversion unit is interconnected with the input/output port of the master logic judgment unit, the master logic judgment unit is interconnected with the input/output port of the slave logic judgment unit, the output port of the master logic judgment unit is connected with the output control module, and the input port of the master logic judgment unit is connected with the output port of the network on chip.

7. The memory management communication interface of claim 6, wherein the master logic determination unit comprises check logic, memory management logic, unpacking and data encapsulation logic, acknowledgement packet generation logic, read response generation logic, occupation/retransmission handshake logic, and master interface logic determination control state machine, wherein the master logic determination unit receives acknowledgement packets through an input port of the network on chip, and comprises an application response packet, a memory response packet, a write response packet, and a read acknowledgement packet, and after unpacking and verification, sends occupation release notification information to the slave logic determination unit, thereby releasing occupation of a retransmission buffer in the slave logic determination unit, writing the notification information of occupation release into the master data conversion unit, receives the read response packet and the shared interrupt packet through an input port of the network on chip, writes necessary information into the master data conversion unit after unpacking and verification, receives the read and write packets through an input port of the network on chip, sends the write response packet and the read acknowledgement packet through an output port of the network on chip, receives the read response packet from the master data conversion unit, and sends the read response packet back to the slave logic determination unit as the read response packet, and sends the read response packet to the master data conversion unit after the read response packet has failed to the read response packet.

8. The memory management communication interface of claim 1, wherein the primary data conversion unit comprises a AXImAW channel control state machine, a AXIm W channel control state machine, a AXIm B channel control state machine, a AXImAR channel control state machine, a AXIm R channel control state machine, data encapsulation logic, IO interrupt logic, data parsing logic, and a primary interface data conversion control state machine, wherein the primary data conversion unit receives necessary information of a read request from the primary logic judgment unit, initiates transmission to a read request address through AXImAR channels, then reads back read data through AXIm R channels, encapsulates the read data into a specific format, writes the write request into the primary logic judgment unit, initiates transmission to a read response AXI address given by an initial configuration through AXImAW channels, sends the read response information and the read response data to the SRIO through AXIm W channels, receives notification information including retransmission failure notification information, shared write notification information, occupation release notification information through AXImAW channels, initiates transmission to a notification information AXI address of a corresponding notification type given by the initial configuration, sends notification information of a request to the SRIO of a request AXIm W, and sends the notification information of the received request to the SRIO through the SRIO device through the initial configuration.

9. The memory management communication interface of claim 1, wherein the output control module performs arbitration and multi-way gating in units of data packets, performs arbitration according to a pre-priority when two or more packet header flits are received simultaneously, and takes up an output port before the whole data packet is output, and waits for next arbitration when the data packet with a lower priority has a higher priority, wherein the arbitration policy is that a request for obtaining output authority least recently has a highest priority.

10. The memory management communication method for the network on chip and the SRIO protocol is realized according to the memory management communication interface of any one of claims 1 to 9, and is characterized by comprising the following steps:

Step S1, after each reset, the memory management communication interface receives initial configuration information from SRIO through AXIs AW channels and AXIs W channels, and completes network-on-chip coding configuration, reading response receiving address, interrupt information receiving address, retransmission failure receiving address, occupation release receiving address, shared writing notification receiving address, writing request notification receiving address and request received notification receiving address;

Step S2, receiving memory management and read-write requests through AXIs AW channels and AXIs W channels, and packaging the requests into request packets in a network-on-chip-oriented form, wherein the request packets comprise application, sharing, release, read-write request packets;

Step S3, completing the transmission of write response, read data and various notification information through AXImAW channels and AXIm W channels, wherein the notification information comprises retransmission failure notification, occupation release notification, shared write notification, write request information notification and request received notification;

s4, receiving a read-write request packet through an on-chip network-oriented input port, and executing corresponding operation according to the request type after unpacking and verification;

Step S5, receiving response packets including application response packets, access response packets, write response packets, read confirmation packets, read response packets and shared interrupt packets through the network-on-chip input port, and executing corresponding operations according to response types after unpacking and verification;

And S6, setting a time-out retransmission function by the memory management communication interface, wherein a retransmission buffer zone caches a last request packet sent by a network-on-chip output port, and triggering retransmission and sending out the request packet in the retransmission buffer zone again if the corresponding response packet is not received within a set time after the request packet is sent out.