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CN119447065B - Back-side powered chip stacking structure and preparation method thereof - Google Patents

Back-side powered chip stacking structure and preparation method thereof

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Publication number
CN119447065B
CN119447065B CN202310957837.4A CN202310957837A CN119447065B CN 119447065 B CN119447065 B CN 119447065B CN 202310957837 A CN202310957837 A CN 202310957837A CN 119447065 B CN119447065 B CN 119447065B
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China
Prior art keywords
layer
chip
substrate
signal connection
power
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Active
Application number
CN202310957837.4A
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Chinese (zh)
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CN119447065A (en
Inventor
陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202310957837.4A priority Critical patent/CN119447065B/en
Publication of CN119447065A publication Critical patent/CN119447065A/en
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Publication of CN119447065B publication Critical patent/CN119447065B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/02381—Side view

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application provides a chip stacking structure for back power supply and a preparation method thereof, wherein the chip stacking structure comprises two chips which are bonded up and down, the two chips realize signal transmission through signal connection layers bonded with each other, and meanwhile, by combining the arrangement of a power rail and an embedded power layer, a metal interconnection layer is formed on the back of a first chip as a back power supply layer, so that transistors of the upper chip and the lower chip can be powered, and the transmission of electric signals is realized. Through the stacking design, the chip stacking structure can realize double transistor quantity under the same area, for example, only 14nm manufacturing process can be used, and the upper transistor stacking method and the lower transistor stacking method can achieve the transistor quantity under 7nm manufacturing process and achieve the same performance, so that the process cost is saved. In addition, the second chip bonded with the first chip also serves as a temporary carrier, and the temporary carrier is not required to be additionally provided, so that the manufacturing cost is further reduced.

Description

Back-side power supply chip stacking structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip stacking structure and a preparation method thereof.
Background
In conventional 2.5D or 3D advanced packaging, the signal lines and power lines are typically routed on the front side of the wafer, vertically stacked and connected to form a semiconductor device of two or more layers of active electronic components of an integrated circuit. The power supply network is formed by supplying power to the chips through the power lines. However, there is a signal network formed by signal lines in the front area of the chip, and the power supply network is fabricated on the front of the chip, which means that the power supply network and the signal network in the chip must share the same component space, and the power supply network often occupies a larger space, so that the volume of the whole packaging structure is difficult to be further reduced. In addition, the three-dimensional package structure with increased chip density may exhibit a high IR drop, which may lead to increased power consumption and reduced device performance.
Therefore, the industry is beginning to explore the possibility of transferring the power supply network to the back side, making back side PDN a popular technical issue. The current back side power supply technology is often used for 2D packaging, and based on the back side power supply technology, how to further increase the chip density of the packaging structure and increase the number of transistors so as to improve the device performance becomes another problem facing the technicians.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a chip stacking structure and a method for manufacturing the same, which are used for improving chip density and increasing the number of transistors.
To achieve the above and other related objects, the present invention provides a back-side power chip stack structure comprising:
the first chip comprises a first substrate, a buried power layer, a dielectric layer and a signal connection layer which are sequentially stacked from top to bottom, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors;
The second chip is bonded below the first chip and comprises a second substrate, a buried power layer, a dielectric layer and a signal connection layer which are sequentially stacked from bottom to top, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors;
The first chip and the second chip are respectively provided with a power rail, the power rails penetrate through the dielectric layer and the signal connection layer to be electrically connected with the embedded power layer, the signal connection layers of the two chips are in contact to realize signal connection, and the power rails of the two chips are in contact to realize electric connection.
Preferably, the chip stack structure further includes an isolation layer formed by a shallow trench isolation process, the isolation layer being used for isolation between a plurality of buried power layers or for electrical insulation between transistors.
Preferably, a plurality of metal columns penetrating through the first substrate are formed in the first substrate, and the metal columns are respectively and electrically connected with the power rail and the embedded power layer of the first chip.
Preferably, a metal interconnection layer is formed on the surface of the first substrate, and is used for electrically leading out the metal column.
Preferably, the semiconductor device further comprises a capacitance inductance layer, wherein the capacitance inductance layer is located between the first substrate and the metal interconnection layer.
The invention also provides a preparation method of the back-side power supply chip stacking structure, which comprises the following steps:
S1, providing a first substrate, forming a buried power layer and a dielectric layer on the first substrate, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer to form a first chip, and the buried power layer is used as a power supply channel of the transistors;
S2, providing a second substrate, forming a buried power layer and a dielectric layer on the second substrate, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and forming a second chip;
s3, forming a signal connection layer on the surface, far away from the substrate, of the dielectric layers of the first chip and the second chip, wherein a metal wire is formed in the signal connection layer so as to realize signal connection with the transistor;
And S4, bonding the first chip and the second chip up and down to form a stacked body, enabling the signal connection layers of the two chips to be in contact to realize signal connection, and enabling the power rails of the two chips to be in contact to realize electric connection.
Preferably, the method further comprises the following steps:
s5, turning over the stacking body to enable the first chip to face upwards, and thinning a first substrate of the first chip;
S6, forming a plurality of penetrating metal columns in the thinned first substrate, wherein the metal columns are respectively and electrically connected with the power rail of the first chip and the embedded power layer;
And S7, forming a metal interconnection layer on the surface of the thinned first substrate, and electrically leading out the metal column.
Preferably, before the metal interconnection layer is prepared in step S7, a capacitive inductance layer is further formed on the surface of the first substrate, and the capacitive inductance layer is located between the first substrate and the metal interconnection layer.
Preferably, the first substrate in the step S1 includes a silicon substrate layer, an etching stop layer and a silicon cover layer stacked in sequence, the second substrate in the step S2 is a silicon substrate layer, and the thinning process of the first substrate in the step S5 removes the silicon substrate layer and the etching stop layer.
Preferably, in the steps S1, S2, a process of forming an isolation layer for isolation between a plurality of buried power layers or for electrical insulation between transistors by a shallow trench isolation process is further included.
As described above, the application provides a chip stacking structure for back side power supply and a method for manufacturing the same, the chip stacking structure comprises two chips bonded up and down, the two chips realize signal transmission through signal connection layers bonded with each other, and simultaneously, by combining the arrangement of a power rail and a buried power layer, only a metal interconnection layer is formed on the back side of a first chip as a back side power supply layer, transistors of the upper and lower chips can be powered up, and electric signal transmission is realized. Through the stacking design, the chip stacking structure can realize double transistor quantity under the same area, for example, only 14nm manufacturing process can be used, and the upper transistor stacking method and the lower transistor stacking method can achieve the transistor quantity under 7nm manufacturing process and achieve the same performance, so that the process cost is saved. In addition, the second chip bonded with the first chip also serves as a temporary carrier, and the temporary carrier is not required to be additionally provided, so that the manufacturing cost is further reduced.
Drawings
Fig. 1-8 are schematic views of the process steps of the chip stacking structure of the present invention.
Fig. 9 is a schematic structural diagram of a chip stacking structure according to the present invention.
Fig. 10 is a schematic structural diagram of a chip stack structure with a capacitive inductance layer according to the present invention.
Description of element reference numerals
101 Silicon substrate layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between" means including both end values.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1 to 8, the present invention provides a method for preparing a back-side power supply chip stacking structure, which specifically includes the following steps:
S1, providing a first substrate, as shown in fig. 1-2, forming a buried power layer 104 and a dielectric layer 105 on the first substrate, wherein a plurality of transistors 201 electrically connected to the buried power layer 104 are formed in the dielectric layer 105, and forming a first chip 100, wherein the buried power layer 104 is used as a power supply channel of the transistors 201.
Specifically, the first substrate includes a silicon substrate layer 101, an etching stop layer 102, and a silicon capping layer 103 stacked in sequence, and the etching stop layer 102 may be one or any of SiGe, ti, al, siN. The buried power layer 104 and the dielectric layer 105 are sequentially formed on the silicon cap layer 103. As an example, the transistor 201 may be a Fin FET, the transistor 201 may be formed after the buried power layer 104 is formed, and the transistor 201 is formed by covering a silicon material layer and then further performing etching, doping, etc., and a specific manufacturing process of the transistor 201 (Fin FET) may be referred to in the prior art, which is not specifically described herein. The dielectric layer 105 is used to electrically insulate the transistors 201 from each other and from the upper and lower layers.
Further, a Shallow Trench Isolation (STI) process may be included in this step, which in some embodiments is used to form the buried power layer 104 by depositing a layer of insulating material, forming a trench by etching, and then filling the trench with a conductive material to form a pattern conductive to power the transistor. In still other embodiments, a shallow trench isolation process is used to fabricate isolation layer 202 to achieve isolation between multiple buried power layers 104, such as where the chip is provided with multiple buried power layers 104 (Buried power rail, BPR), including a first BPR for providing a first supply voltage (e.g., VDD) and a second BPR for providing a second supply voltage (e.g., VSS or GND), or to divide the transistors into multiple subsets, where the multiple buried power layers include a third BPR for providing the first supply voltage to the first subset of transistors and a fourth BPR for providing the first supply voltage to the second subset of transistors. In still other embodiments, shallow trench isolation processes are used to achieve electrical isolation between transistors, and isolation layers 202 are provided between transistors 201 to be separated from each other to ensure mutual isolation.
Next, step S2 is performed by providing a second substrate, and forming a buried power layer 104 and a dielectric layer 105 on the second substrate, wherein a plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105, thereby forming a second chip 200, as shown in fig. 3.
Specifically, as an example, the second substrate may have the same composite layer structure as the first substrate, and includes a silicon substrate layer 101, an etching stop layer 102, and a silicon capping layer 103 stacked in order. Preferably, the second substrate comprises only the silicon substrate layer 101, since the cost of a single silicon substrate layer 101 is obviously lower than the cost of the composite layer. The reason for selecting the composite layer for the first substrate is that the subsequent step S5 of thinning the first substrate requires the etching stop layer 102 as a stop signal during thinning. There is no thinning process for the second substrate and no etch stop layer 102 is required. Meanwhile, similar to the first chip, the second chip is also formed with an isolation layer 202 for isolation between a plurality of buried power layers or for electrical insulation between transistors.
Next, as shown in fig. 4, a signal connection layer 106 is formed on the surface of the dielectric layer 105 of the first chip 100 and the second chip 200 away from the substrate, and metal wires are formed in the signal connection layer 106 to realize signal connection with the transistor 201, and power rails 16 are respectively formed on the first chip 100 and the second chip 200, and the power rails 16 penetrate through the dielectric layer 105 and the signal connection layer 106 to electrically connect the embedded power layer 104;
Specifically, the signal connection layer 106 may be prepared by a damascene process of copper, and as an example, an insulating layer such as silicon dioxide is deposited on the surface of the dielectric layer 105, then etching is performed to form a trench, then metal copper is deposited in the trench, and finally the signal connection layer 106 is formed, where the metal wire in the signal connection layer 106 is copper.
Next, as shown in fig. 5, the first chip 100 and the second chip 200 are bonded up and down to form a stack, so that the signal connection layers 106 of the two chips are in contact to realize signal connection;
Specifically, the two chips are stacked and interconnected by bonding, and by the arrangement of the power rail 16 and the embedded power layer 104, the transistors 201 of the upper and lower chips can be powered. The double transistor number is realized under the same area, for example, only a 14nm process can be used, and the upper transistor stack method and the lower transistor stack method are combined to achieve the transistor number under the 7nm process and achieve the same performance. Advanced processes mean expensive process costs, which can be saved while achieving the same performance by stacking one above the other.
Next, step S5 is performed, as shown in fig. 6-7, turning the stack body upside down to make the first chip 100 face upwards, and then thinning the first substrate of the first chip 100;
Specifically, the first substrate before thinning includes a silicon substrate layer 101, an etching stop layer 102, and a silicon cap layer 103, and the etching stop layer 102 at the time of thinning serves as a stop signal at the time of thinning. In the process, the silicon substrate layer 101 of the first substrate is thinned by CMP, then the residual part of the silicon substrate layer 101 is removed by dry etching, and finally the etching stop layer 102 is removed by wet etching, that is, the thinned first substrate only comprises the silicon cover layer 103.
It should be noted that, the second chip 200 after being turned over is located below the first chip, which serves as a temporary carrier, and if the second chip 200 is not present, a temporary carrier needs to be provided to carry and fix the first chip 100 for subsequent thinning. The temporary carrier is a temporary material, and the manufacturing cost is high, so that the bonding of the first chip 100 and the second chip 200 increases the number of collective tubes, avoids the use of the temporary carrier, and reduces the manufacturing cost.
Next, as shown in fig. 8, a plurality of through metal pillars 31 are formed in the thinned first substrate (i.e., the remained silicon cap layer 103), and the plurality of metal pillars 31 are electrically connected to the power rail 16 and the buried power layer 104 of the first chip 100, respectively. The metal pillars electrically connected to the buried power layer 104 have a signal transmission function, except for transmitting power, and the signal is transmitted to the first chip, and then the first chip is transmitted to the second chip through the signal connection layer.
Specifically, a passivation layer is formed on the surface of the first substrate, the passivation layer is usually an oxide material or oxynitride to play a role of moisture prevention and static electricity prevention, so as to protect an internal circuit, then a metal column 31 is prepared, the process of preparing the metal column 31 is that a plurality of through silicon vias, more specifically nano through silicon vias, are formed in the first substrate, then an oxide layer is covered on the inner wall of the through silicon vias, and finally metal columns 31 are formed by metal filling.
In step S7, as shown in fig. 9, a metal interconnection layer 301 is formed on the surface of the thinned first substrate, so as to electrically lead out the metal pillars 31.
Specifically, similar to step S3, the metal interconnect layer 301 is also preferably prepared by a damascene process of copper, and as an example, an insulating layer such as silicon dioxide is deposited on the surface of the substrate, then etched to form a trench, and then metal copper is deposited in the trench, finally forming the metal interconnect layer 301.
Additionally, before the metal interconnection layer 301 is prepared, a capacitance-inductance layer 302 is further formed on the surface of the first substrate, as shown in fig. 10, the capacitance-inductance layer 302 is located between the first substrate and the metal interconnection layer 301, the metal interconnection layer 301 is electrically connected with the metal column 31 through the capacitance-inductance layer 302, the capacitance-inductance layer 302 comprises a plurality of capacitors and inductors, the regulation and control effect on the circuit is achieved, the power integrity is achieved, meanwhile, no additional occupied area is achieved, and the size is controlled to save space. The metal interconnection layer 301 and the capacitor inductance layer 302 serve as back side power supply layers for supplying power, and by combining the arrangement of the power rail 16 and the embedded power layer 104, the electric signal can be transmitted to the transistors 201 of the upper and lower chips only by forming the metal pillars 31 by making through silicon vias in the substrate of the first chip 100.
The present invention also provides a back-side power chip stack structure, as shown in fig. 9 to 10, which may be based on the above-mentioned preparation method, but is not limited to the above-mentioned preparation method, and the chip stack structure includes:
The first chip 100 includes a first substrate (here, the first substrate corresponds to the thinned first substrate in the above preparation method, i.e. the silicon cap layer 103), a buried power layer 104, a dielectric layer 105 and a signal connection layer 106, which are sequentially stacked from top to bottom, wherein a plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105, and metal wires are formed in the signal connection layer 106 to realize signal connection with the transistors 201;
a second chip 200 bonded below the first chip 100, including a second substrate, a buried power layer 104, a dielectric layer 105 and a signal connection layer 106 stacked in sequence from bottom to top, wherein a plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105, and metal wires are formed in the signal connection layer 106 to realize signal connection with the transistors 201;
The first chip 100 and the second chip 200 are further formed with power rails 16 respectively, the power rails 16 penetrate through the dielectric layer 105 and the signal connection layer 106 to electrically connect the embedded power layer 104, the signal connection layers 106 of the two chips are in contact to realize signal connection, and the power rails 16 of the two chips are in contact to realize electrical connection.
Further, the chip stack structure further includes an isolation layer 202 formed by a shallow trench isolation process, the isolation layer 202 being used for isolation between the plurality of buried power layers 104 or for electrical insulation between the transistors 201.
Further, a plurality of through metal pillars 31 are formed in the first substrate, and the plurality of metal pillars 31 are electrically connected to the power rail 16 and the embedded power layer 104 of the first chip 100, respectively.
Further, a metal interconnection layer 301 is formed on a surface of the first substrate, for electrically extracting the metal pillars 31.
Further, a capacitive inductance layer 302 is further included, and the capacitive inductance layer 302 is located between the first substrate and the metal interconnection layer 301.
For specific details of the chip stacking structure, reference may be made to the related descriptions in the above preparation method, which are not repeated here.
In summary, the present application provides a back-side power supply chip stacking structure and a method for manufacturing the same, where the chip stacking structure includes two chips bonded up and down, the two chips realize signal transmission through signal connection layers bonded to each other, and meanwhile, by combining the arrangement of a power rail and a buried power layer, only a metal interconnection layer is formed on the back side of a first chip as a back-side power supply layer, both transistors of the upper and lower chips can be powered, so as to realize transmission of electrical signals. Through the stacking design, the chip stacking structure can realize double transistor quantity under the same area, for example, only 14nm manufacturing process can be used, and the upper transistor stacking method and the lower transistor stacking method can achieve the transistor quantity under 7nm manufacturing process and achieve the same performance, so that the process cost is saved. In addition, the second chip bonded with the first chip also serves as a temporary carrier, and the temporary carrier is not required to be additionally provided, so that the manufacturing cost is further reduced.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A back-side powered chip stack structure, the chip stack structure comprising:
the first chip comprises a first substrate, a buried power layer, a dielectric layer and a signal connection layer which are sequentially stacked from top to bottom, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors;
The second chip is bonded below the first chip and comprises a second substrate, a buried power layer, a dielectric layer and a signal connection layer which are sequentially stacked from bottom to top, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors;
The first chip and the second chip are respectively provided with a power rail, the power rails penetrate through the dielectric layer and the signal connection layer to be electrically connected with the embedded power layer, the signal connection layers of the two chips are in contact to realize signal connection, and the power rails of the two chips are in contact to realize electric connection.
2. The chip stack structure of claim 1, further comprising an isolation layer formed by a shallow trench isolation process, wherein the isolation layer is used for isolation between a plurality of buried power layers or for electrical insulation between transistors.
3. The chip stacking structure as set forth in claim 1, wherein a plurality of metal pillars are formed in the first substrate, and the metal pillars are electrically connected to the power rail and the embedded power layer of the first chip, respectively.
4. The chip stacked structure of claim 3, wherein a metal interconnection layer is formed on a surface of the first substrate for electrically extracting the metal pillars.
5. The chip stack structure of claim 4, further comprising a capacitive-inductive layer between the first substrate and the metal interconnect layer.
6. A method for manufacturing a back-side powered chip stack structure, the method comprising the steps of:
S1, providing a first substrate, forming a buried power layer and a dielectric layer on the first substrate, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer to form a first chip, and the buried power layer is used as a power supply channel of the transistors;
S2, providing a second substrate, forming a buried power layer and a dielectric layer on the second substrate, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and forming a second chip;
s3, forming a signal connection layer on the surface, far away from the substrate, of the dielectric layers of the first chip and the second chip, wherein a metal wire is formed in the signal connection layer so as to realize signal connection with the transistor;
And S4, bonding the first chip and the second chip up and down to form a stacked body, enabling the signal connection layers of the two chips to be in contact to realize signal connection, and enabling the power rails of the two chips to be in contact to realize electric connection.
7. The method of manufacturing according to claim 6, further comprising the step of:
s5, turning over the stacking body to enable the first chip to face upwards, and thinning a first substrate of the first chip;
S6, forming a plurality of penetrating metal columns in the thinned first substrate, wherein the metal columns are respectively and electrically connected with the power rail of the first chip and the embedded power layer;
And S7, forming a metal interconnection layer on the surface of the thinned first substrate, and electrically leading out the metal column.
8. The method of manufacturing a metal interconnect layer according to claim 7, wherein a capacitive/inductive layer is further formed on the surface of the first substrate, the capacitive/inductive layer being located between the first substrate and the metal interconnect layer, before the metal interconnect layer is manufactured in step S7.
9. The method of claim 6, wherein the first substrate in step S1 comprises a silicon substrate layer, an etching stop layer and a silicon cover layer stacked in sequence, the second substrate in step S2 is a silicon substrate layer, and the thinning process of the first substrate in step S5 removes the silicon substrate layer and the etching stop layer.
10. The method of claim 6, wherein the step S1, S2 further comprises forming an isolation layer by shallow trench isolation, wherein the isolation layer is used for isolation between a plurality of buried power layers or for electrical insulation between transistors.
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