CN1194496C

CN1194496C - Method and circuit for controlling wireless baseband modulation multi-channel phase matching by using PLL

Info

Publication number: CN1194496C
Application number: CNB011348240A
Authority: CN
Inventors: 尹登庆
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2001-11-15
Filing date: 2001-11-15
Publication date: 2005-03-23
Anticipated expiration: 2021-11-15
Also published as: CN1420653A

Abstract

The present invention relates to a technique for modulating multi-channel phase match by a phase-lock loop (PLL) controlling radio base band. By a phase error testing circuit, a phase error of an analog signal between a passage to be adjusted and a reference passage of which the phase is set to a fixed value is converted to a pulse digital signal of which the duty ratio is changed along with the size of the phase error. The pulse digital signal controls the charging time and the discharging time of a charge pump to obtain a charge pump voltage reflecting the size of the phase error and the polarity. A current source of the charge pump is matched with a control circuit to control the consistency of the charging current and the discharging current of the charge pump. By an analog to digital converter, the charge pump voltage is converted to a digital control signal carrying out the phase matching adjustment on the passage to be adjusted. A latch is used for latching the digital control signal. By the analog to digital converter, the digital control signal is converted to an adjusting signal for carrying out the phase matching adjustment on the passage to be adjusted, which makes the phase of the passage to be adjusted keep consistent with that of the reference passage. The present invention has the characteristics of high adjustment precision and no relation between the adjustment error and the service life.

Description

Utilize the method and the circuit of PLL control radio base band modulating multi-channel phase matched

Technical field

The present invention relates to the multichannel phase coupling control technology in the wireless communication technology field, relate to a kind of adaptive technique of using or rather multichannel baseband modulation in the radio communication is carried out the method and the circuit of accurate phase control, be specially adapted to the design and the manufacturing of integrated circuit.

Background technology

In existing wireless communication baseband modulating system, interchannel phase matched is that the manufacturing process by integrated circuit guarantees.Integrated circuit is better to the matching degree of device closely, but to the interchannel coupling of multimode, its precision is difficult to guarantee.

When the phase place of interchannel signal not simultaneously, particularly be extensive use of phase modulation technique in the modern wireless communication systems, problems such as error rate raising that phase deviation, noise margin reduces and make system, communication speed reduction will appear in signal in decode procedure.

Fig. 1 is the principle structure schematic diagram of existing wireless communications baseband modulation integrated chip.Comprise digital modulator (DIGITAL MODULATION) 11, analog processor 12 (ANALOG PROCESS) and auxiliary circuit 13 (AUXILIARY CIRCUIT).The data DATA INPUT of input finishes digital modulation after entering the digital modulator (DIGITAL MODULATION) 11 of chip internal, (as 12～14bits) respective channel of giving analog processor 12 (ANALOG PROCESS), each passage is by digital to analog converter 121 (DAC), filter 122 (FILTER) and analog line driver 123 (DRIVER) formation that is linked in sequence in the mode of multi-channel parallel data.By each passage finish digital-to-analogue conversion (as 12～14bits), after filtering and the power drive, at last with the mode of multi-channel analog signal (OUTPUT I ... OUTPUT Q) give the back level processor.The logic input (LOGIC INPUT) of this integrated chip is mainly used in to be controlled various functions, and auxiliary circuit (AUXILIARY CIRCUIT) 13 is mainly finished functions such as voltage reference.

Above-mentioned radio base band modulation circuit is modulated at numerical portion and finishes, and for Modern wireless communication, the digital baseband modulation has main features such as precision height, response speed is fast, antijamming capability is strong.

But this circuit is that consistency with integrated circuit fabrication process realizes for the interchannel phase matched that is partly produced by simulation process, owing to do not carry out the correction of interchannel phase matched specially, interchannel phase error can only be controlled in certain scope.Again because the error of manufacturing process is a random distribution, thereby the performance of integrated chip can be offset within the specific limits, and consistency is relatively poor.

Utilize laser-adjusting and melt aluminium, melt bearing calibration such as polysilicon silk, need chip be tested, and test process needs by precision instrument, thereby increased the difficulty and the cost of chip testing.And laser-adjusting has only large-scale semiconductor company just to have the ability to do, and is not suitable for general manufacturer and adopts.Even proofreaied and correct precision, but circuit chip still may produce skew after long-time the use, causes the electric property of chip to reduce.

In sum, the multichannel of the radio communication quadrature modulation Base-Band Processing integrated chip circuit of obvious structure shown in Figure 1 gain coupling guarantees that technology is not fill part, and the utmost point has improved necessity.

Phase-locked loop (PLL) is the degenerative closed circuit of a kind of phase place, compare by the phase place of phase discriminator two signals (output signals of input and output signal or two passages), obtain and the corresponding error voltage of both phase differences, utilize this error voltage that circuit delay is adjusted again, the phase error between two signals is controlled in certain scope.

Can the phase error between two signals be converted to the pulse digital signal of duty ratio size with the phase error size variation by phase error detection circuit, go to control charge pump charging and the length of discharge time again, thereby by the charge pump stored charge is voltage on the electric capacity, goes to reflect the size and the polarity of phase error.

Shown in Figure 3 is a circuit that utilizes two voltage comparators to realize phase-detection.OUTPUT I and OUTPUT Q are the analog output signals of I, two passage quadrature modulation of Q, common-mode voltage when VCOMI and VCOMQ are I, Q channel modulation signal processing, the COM module is a voltage comparator, the opAMP module is an operational amplifier, the INV module is an inverter, the XOR module is an XOR gate, and SA and SB are electronic switch.

(OFFSET CANCELL) circuit is offset in the drift that is made of voltage comparator operational amplifier opAMP, capacitor C A and CB, electronic switch SA and SB.Analog quadrature modulation signal OUTPUTI and OUTPUTQ are that benchmark compares with VCOMI and VCOMQ respectively, it is final that to produce with common-mode voltage separately be the numeral output of zero crossing, after inverter INV is anti-phase, finish the phase-detection of OUTPUTI and two signals of OUTPUTQ in XOR gate (XOR), testing result is represented with CHLOGIC.

Utilize Fig. 3 circuit can realize the phase-detection of certain precision, but circuit have higher requirement to drift (OFFSET) voltage and the gain of voltage comparator.

Foregoing circuit causes that the main source of error is:

(1) circuit is limited to the inhibition of the drift voltage of voltage comparator, inhibition to the voltage comparator drift voltage is directly proportional with the gain of operational amplifier, when the gain of operational amplifier is 1000, the drift voltage of setting comparator is 10mV, and then the drift voltage of equivalence is 10uV (10mV/1000) in the circuit;

(2) gain of voltage comparator and gain matching precision are limited, if the gain of voltage comparator COM1 is 2000, the gain of voltage comparator COM2 is 1500, and output voltage swing 2V is effective, at this moment, COM1 is input as 1mV (2/2000), and COM2 is input as 1.33mY (2/1500), and the error of introducing is 0.33mV;

(3) comparator can not be introduced accurate returning between the dead zone, and The noise is big.

Referring to Fig. 4 in conjunction with referring to Fig. 3, CH I OUTPUT I and CH Q OUTPUT Q are respectively the output signals of passage I, Q, when CHANNEL I and CHANNEL Q with identical reference voltage (VREF) when making comparisons, can obtain accurately phase error to the mapping of pulse duty factor; When having drift (OFFSET) voltage (VREF+Vos), then there is mapping error, shown in shade drift effect among the figure (offset effect), the influence of factors such as matching error can be observed by the influence of OFFSET voltage and voltage comparator is gained.

Referring to Fig. 7, be the realization circuit of a general precision charge pump.Form by reference current source generation module, buffering output stage and switch control module.Operational amplifier op1, transistor M1 to Mll, resistance R 1 connect and compose the reference current source generation module, form the buffering output stage by operational amplifier op2, connect and compose switch control module by electronic switch SW1 to SW3 and iteration count (ITERATION COUNTER).

Op1 and op2 are two operational amplifiers, and the positive input terminal of op1 is connected with reference voltage VREF, and negative input end is connected with transistor M1 source electrode and resistance R 1, and the output of op1 is connected with the grid of M1.Transistor M2, M3, M4, M5, M6, M7 primordial standard (CASCODE) current source, transistor M8, M9, M10, M11 constitutes another one benchmark (CASCODE) current source.Transistor M2, M3, the grid of M7 is connected with bias voltage VBIASP, and the grid of M8 and M10 is connected with bias voltage VBIASN.M4, M5, the grid of M6 is connected with the drain electrode of M1, M2, M9, the grid of M11 is connected with the drain electrode of M3, M8.M4, M5, the source electrode of M6 is connected with power vd D, M9, the source electrode of M11 is connected with ground wire.

When the CHLOGIC signal of exporting in Fig. 3 circuit was " 1 " (the non-signal of CHLOGIC for " 0 "), control electronic switch SW2 allowed electric current among M6, the M7 to capacitor C 1 charging, and electronic switch SW1 imports power vd D with the electric current among M11, the M10; When CHLOGIC was " 0 " (the non-signal of CHLOGIC is " 1 "), SW2 imported ground wire with the electric current among M6, the M7, and SW1 imports capacitor C 1 with electric current among M11, the M10 with discharge type.

Op2 is a voltage follower, and positive input terminal is connected with capacitor C 1, and negative input end is connected with output.

Electronic switch SW3 realizes (RESET) control that resets of capacitor C 1, voltage on capacitor C 1 raises or reduces, thereby the variation that causes op2 output voltage VO UT caused the signed magnitude arithmetic(al) of a logic control, I, Q channel phases error are once adjusted after, promptly under the control of iteration count (ITERATION COUNTER), export the RESET signal, by electronic switch SW3 capacitor C 1 is resetted, make to be charged to VCOM.

When the equal and opposite in direction of charging current and discharging current, circuit shown in Figure 7 can be realized phase-detection and controlled function accurately.But in source (SOURCE), leakage (SINK) circuit, need realize the coupling of charging current and discharging current by transistorized coupling, the error of source transistor, drain circuit coupling has determined the precision of PLL circuit to phase error detection.

If T is the cycle of signal, Δ t is the mean value that the charge or discharge time changes in the one-period that causes of phase error, and I is a mean charging current, and Δ I is the error of charging current and discharging current.

Charge cycle is: T/2+ Δ t

Charging current is: I+ Δ I

Discharge cycle is: T/2-Δ t

Discharging current is: I-Δ I

Being changed to of voltage on the charge pump in signal period then:

ΔQ＝(I+ΔI)(T+Δt)-(I-ΔI)(T-Δt)

＝2×I×Δt+2×ΔI×T+2×Δt×ΔI

First (I+ Δ I) (T+ Δ t) is phase error in the following formula, and second (I-Δ I) (T-Δ t) is the error of charging and discharging current.Generally speaking, second will be far smaller than first.

When foregoing circuit is used in general PLL circuit, because the cycle of phase change and signal is at the same order of magnitude, thereby satisfy the error requirements between charging current and discharging current easily, but requiring the accurately occasion of coupling of phase place, adopt the simple charge pump (CHARGE PUMP) shown in Fig. 7 circuit, can not meet the demands.

If the cycle of signal is 16us, the phase matched precision of requirement is 4ns, and current error must then have less than 1/10 the influence of phase error:

ΔI×16us×10＜I×4ns

ΔI/I＜4/160000＝1/40000

Because the coupling of general electric current is about 0.1%, this high accuracy coupling is to realize with ball bearing made using shown in Figure 7.

Summary of the invention

The objective of the invention is to design a kind of method and circuit that utilizes phase-locked loop (PLL) control radio base band modulating multi-channel phase matched, have the precision of adjustment height, error can not occur adjusting along with the prolongation of time, make it to be suitable in high performance wireless communication system, to use, particularly in integrated chip design, use as the GPRS pattern of GSM.

The technical scheme that realizes the object of the invention is such, and a kind of method of utilizing phase-locked loop (PLL) control radio base band modulating multi-channel phase matched is characterized in that comprising following treatment step:

A. the phase place with the benchmark passage is made as fixed value, by phase error detector the phase error of the analog signal of passage to be adjusted and benchmark passage output is converted to the pulse digital signal of duty ratio with the phase error size variation, what import passage to be adjusted and benchmark passage is identical signal;

B. this pulse digital signal is controlled the length of charge pump charging interval and discharge time, obtains the charge pump voltage of reflection phase error size and polarity;

C. by analog to digital converter charge pump voltage is converted to passage to be adjusted is carried out the digital controlled signal that phase matched is adjusted;

D. by digital to analog converter this digital controlled signal is converted to passage to be adjusted is carried out the adjustment signal that phase matched is adjusted, make the phase place of passage to be adjusted keep consistent with the phase place of benchmark passage.

Described steps A is to carry out under the closed-loop working state in circuit power-up initializing stage to D, after initial phase finishes, digital controlled signal by latches step C acquisition, be converted to by the digital to analog converter among the step D and fixing passage to be adjusted carried out the adjustment signal that phase matched is adjusted, circuit working is under the operate in open loop state state.

Analog signal in the described steps A is in the circuit power-up initializing stage, and the digitized sine wave signal that is produced by digital sine wave generator obtains after digital modulation, digital-to-analogue conversion, filtering and power drive.

The described power-up initializing stage is the requirement of adjusting precision according to phase matched, carries out the time that repeats of timer controlled step A to D by the timing length of selecting timer.

Phase error detection in the described steps A further comprises:

A1. two analog signal gatings are sent into the positive input terminal of a voltage comparator (COM1), the VCOM level that inserts with negative input end compares, and is coupled in high resistant direct current mode between the positive and negative input of this voltage comparator (COM1);

A2. allow the positive input terminal of voltage comparator (COM2) insert the analog signal of benchmark passage, negative input end is connected with VCOM after the level translation;

The rising edge zero crossing and the trailing edge zero crossing of a3. first backgating detection reference passage and passage to be adjusted output analog signal, and repeat;

A4. distinguish rising edge and trailing edge by passage gate logic (MCS), allow rising edge according to being handled by the passage of node N1--N2, trailing edge is according to being handled by the passage of node N1--N3;

A5. in the phase error detection logical circuit, carry out the conversion of phase error to pulse duty factor.

Among the described step a4, be that gate with equal number and character connects to form synchronously or delay control circuit is realized by the passage of node N1--N2 with by the passage of node N1--N3.

Among the described step B, also comprise charging and discharging current automatic trimming circuit that a charge pump is set, the consistency of charging current and discharging current in the adjustment charge pump, and further comprise:

B1. by the charge and discharge current deviation of deviation current-sensing circuit charge inducing pump, the charge and discharge current deviation is converted to the rise and fall of node voltage, and as the input voltage of analog to digital converter;

B2. recurrence control is carried out in the conversion that provides a highest significant position (MSB) according to the rising or the decline of input voltage by analog to digital converter or the conversion of inferior highest significant position (MSB);

B3. analog to digital converter output through latch and digital-to-analogue conversion after, output current control reducing charge and discharge current deviation;

B4. the recursive procedure of repeated execution of steps b1 to b3, the least significant bit in being transformed into analog to digital converter (LSB).

Among described step b2, the b3, analog-to-digital realization further comprises following treatment step:

B5. allow the benchmark level of four voltage comparator COM1, COM2, COM3, COM4 negative input end successively decrease successively, with input voltage input four voltage comparator COM1, COM2 of described analog to digital converter, the normal phase input end of COM3, COM4 by VREF2P-VREF1P-VREF1N-VREF2N;

B6. when input voltage between VREF1P and VREF1N, voltage comparator COM2, COM3 output is when being " 1 ", judges and adjusts the requirement that the loop meets the channel phases coupling, the signal adjusted is ended in output;

B7. when VREF2N greater than input voltage, when voltage comparator COM4 is output as " 0 ", the negative sense deviation of judging passage to be adjusted and benchmark interchannel phase error is big, the employing step-length is that the addition of 2 times of least significant bits (2LSB) carries out recurrence, inserts the control signal of current source simultaneously to digital to analog converter output;

B8. work as VREF2N and be output as " 1 " less than input voltage, voltage comparator COM4, and VREF1N is greater than input voltage, when voltage comparator COM3 is output as " 0 ", the negative sense deviation of judging passage to be adjusted and benchmark interchannel phase error is little, the employing step-length is that the addition of 1 times of least significant bit (1LSB) carries out recurrence, inserts the control signal of current source simultaneously to digital to analog converter output;

B9. when VREF2P less than input voltage, when voltage comparator COM1 is output as " 1 ", the positivity bias of judging passage to be adjusted and benchmark interchannel phase error is big, the employing step-length is that the subtraction of 2 times of least significant bits (2LSB) carries out recurrence, inserts the heavy signal of electric current to digital to analog converter output simultaneously;

B10. work as VREF1P and be output as " 1 " less than input voltage, voltage comparator COM2, and when VREF2P greater than input voltage, when voltage comparator COM1 is output as " 0 ", the positivity bias of judging passage to be adjusted and benchmark interchannel error is little, the employing step-length is that the subtraction of 1 times of least significant bit (1LB) carries out recurrence, inserts the heavy signal of electric current to digital to analog converter output simultaneously.

The technical scheme that realizes the object of the invention still is such, and a kind of circuit that utilizes phase-locked loop (PLL) control radio base band modulating multi-channel phase matched is characterized in that:

Comprise phase error detection circuit, charge pump circuit, charge pump current source match control circuit, analog to digital conversion circuit, latch cicuit and D/A converting circuit;

An input of phase error detection circuit connects the output of benchmark channel analog signal, the phase place of this benchmark passage is made as fixed value, another input of phase error detection circuit connects the output of channel analog signal to be adjusted, phase error detection circuit is converted to the phase error of benchmark passage and channel analog signal to be adjusted the pulse digital signal that duty ratio changes with error size and imports charge pump circuit, this pulse digital signal is controlled charge pump circuit charging and the length of discharge time under the support of charge pump current source match control circuit, the charge pump voltage of output reflection phase error size and polarity is also sent analog to digital conversion circuit, analog to digital conversion circuit is converted to charge pump voltage passage to be adjusted is carried out the digital controlled signal of phase matched adjustment and send latch to latch, and the digital controlled signal that D/A converting circuit is exported latch is converted to adjusts parameter signal to the phase place of passage to be adjusted.

Described phase error detection circuit is connected and composed by univoltage comparator and digital module; The univoltage comparator comprises the voltage comparator that negative input end is connected with reference voltage (VCOM), just be coupling in this voltage comparator, direct current insert module between negative input end, be connected with this voltage comparator positive input terminal first, second electronic switch, first, second electronic switch connects the output of two coupling channel analog signals respectively, the output of switching logic connects first, the control end of second electronic switch, the resetting of the input of switching logic and voltage comparator, the set end connects the output of rising edge detection and logic module and trailing edge detection and logic module respectively; Digital module comprises two transmission channels, passage gating module and the phase error detection logic module that is connected and composed by transmission gate and inverter, passage gating module connects transmission gate, the voltage comparator output is connected with two transmission channels, and two transmission channels connect the phase error detection logic module.

Described charge pump current source match control circuit is linked in sequence by phase error current detection circuit, current amplification circuit, current-to-voltage converting circuit, recurrence control circuit, latch cicuit and D/A converting circuit and forms.

Described recurrence control circuit is an analog to digital converter, comprises first, second, third, fourth voltage comparator, stops to adjust judge module, step-length judge module and adder/subtracter module; The positive input terminal of first, second, third, fourth voltage comparator connects input voltage, negative input end connects reference voltage V REF2P, VREF1P, VREF1N, the VREF2N that tapers off, the first, the 4th voltage comparator output connects the step-length judge module, step-length judge module output connects the adder/subtracter module, second, third voltage comparator output and adder/subtracter module output connection stopping to adjust judge module.

Described D/A converting circuit is connected and composed by unit switch, the binary system electric current unit switch heavy and that the binary system electric current is heavy of logic decoder, binary system current source, binary system current source; Binary system current source and the heavy unit switch of binary system electric current are controlled in the output of logic decoder respectively, the output that binary system current source and binary system electric current sink inserts described phase error current detection circuit through behind the unit switch by same electric current output node.

Among the present invention, the deviation of charging and discharging current is finished fine adjustment automatically at the normal circuit initial phase, then with the logic state of locking the precision in the circuit entire work process is controlled when the circuit operate as normal.Circuit is in closed-loop working state in the passage initialization procedure, the phase error of passage is adjusted parameter and obtained automatically in closed loop; Be in the operate in open loop state state when the passage operate as normal, the phase error of passage is adjusted parameter and is preserved with logical value in operate in open loop state.After current deviation reached required precision, the phase error control module promptly quit work, simultaneously phase error is adjusted parameter and is remained in the latch with logic state, in the circuit operate as normal with the lasting conversion value of DAC as the analog control signal of adjusting.

The present invention is designed to phase discriminator to be made of single comparator, reduced the influence of drift voltage etc., for charge pump circuit has designed the Current-source matching control circuit, use high performance matched current sources to improve precision, and the high accuracy of current source coupling can be finished automatically.

The phase error detection circuit of univoltage comparator of the present invention can not considered drift (OFFSET) voltage of voltage comparator; Can not consider the coupling of the finite gain and the gain of voltage comparator; And can in voltage comparator, introduce back and reduce the influence of noise between the dead zone phase error detection.

Method of the present invention and circuit, high performance single comparator phase error detecting method and circuit, high-precision charge pump charging and discharging current coupling reach the implementation from dynamic(al) correction, have following characteristics:

(1) phase matched adjustment between multichannel be can realize automatically, extra test and correction means do not needed;

(2) the phase matched adjustment between multichannel can be carried out at integrated circuit (IC) chip, is applicable to different semiconductor fabrication process, particularly produces on a large scale;

(3) the phase matched adjustment between multichannel is adaptive, carries out with respect to the phase place of benchmark passage, and the phase error of each piece integrated circuit (IC) chip upper channel all can be controlled in the corresponding scope;

(4) the phase matched adjustment between multichannel is promptly carried out after circuit powers on each time, and its control precision can not change along with the prolongation of service time.

Description of drawings

Fig. 1 is the baseband processing chip electrical block diagram of radio communication quadrature modulation;

Fig. 2 adopts multichannel phase to mate the baseband processing chip circuit structure theory diagram of the radio communication quadrature modulation of alignment technique automatically;

Fig. 3 is the phase error detection circuit figure that adopts two voltage comparators to realize;

Fig. 4 is that drift (OFFSET) voltage influences exemplary waveforms figure to phase error detection;

Fig. 5 is the phase error detection circuit figure that utilizes single voltage comparator to realize;

Work wave schematic diagram when Fig. 6 is to use single voltage comparator to realize phase error detection;

Fig. 7 is that the charge pump of general precision is realized circuit diagram;

Fig. 8 is the electrical block diagram of realizing with the current source of high accuracy coupling;

Fig. 9 is the realization circuit theory diagrams of analog-to-digital conversion (ADC) module;

Figure 10 is the signal processing flow figure of analog-to-digital conversion (ADC) module.

Embodiment

Referring to Fig. 2, be a system construction drawing that has adopted the wireless communication baseband processing integrated chip of adaptive channel phase-matching technique of the present invention.Comprise digital modulation module 21, multichannel gain error control module 22, multichannel analog processing module 23, phase error control module 24, digital sine wave generator 25, auxiliary circuit 26 and timer 27.

The digitized sine wave signal (circuit power-up initializing stage) that produces by digital sine wave generator 25 or enter the digital modulation module 21 (DIGITAL MODULATION) of chip internal by the data DATA INPUT (normal work stage after initial phase finishes) of outside input after finish digital modulation, (12～14bits) mode sends multichannel gain error control module 22 to the parallel multi-channel data, adjustment (GAIN ADJUSTMENT) gains, wherein the signal of benchmark passage also enters synchronization module 223 (SYNC) through entering synchronization module 223 (SYNC) behind decay 221 (pre_att) and delay 222 (DELAY) in advance after the signal process of other passages pre-decay (pre_att) 221 and the gain-adaptive adjustment 224.Multichannel analog processing module 23 (ANALOG PROCESS), after analog signal carried out digital-to-analogue conversion 231 (DAC), filtering 232 (FILTER) and power drive 233 (DRIVER), mode OUTPUTI with multi-channel analog signal, ..., OUTPUT Q etc. gives back level processor and phase error control module 24.

24 pairs of multichannel simulation outputs of power-up initializing stage of phase error control module (single frequency sinusoidal ripple) detect, phase place with benchmark passage I is that the needed phase place of other passages of reference calculation (as the Q passage) is adjusted coefficient, remove to control the filter of this respective channel in the multichannel analog processing module 23, change and postpone the adjustment of realization multichannel phase coupling self adaptation.After the power-up initializing stage finished, phase error control module 24 quit work, but locked the phase place adjustment coefficient of each passage, until the circuit power down.

By phase error detection (PHASE DETECTOR) circuit 241 phase error of passage to be adjusted (Q) and benchmark passage (I) analog signal is converted to the pulse digital signal (CHLOGIC) that duty ratio changes with error size, the charging of this pulse digital signal control charge pump circuit 242 and the length of discharge time, by charges accumulated on the charge pump is voltage on the electric capacity, reflects the size and the polarity of channel phases error.Voltage on the charge pump is converted to digital controlled signal through analog to digital conversion circuit (ADC) 244, and the phase place of output channel Q is adjusted parameter after latch cicuit (LATCH) 245 and D/A converting circuit (DAC) 246 processing again.The phase place of benchmark passage I is a fixed value, after the phase place of Q passage is adjusted through the closed loop of above-mentioned PLL pattern, and can be consistent with passage I.

The phase error adjustment of each passage was finished in the circuit power-up initializing stage, and it is to be operated in the closed loop state that promptly whole phase error is adjusted circuit, and the phase error of this moment is adjusted circuit and realized phase-locked loop (PLL) function.When a passage and the interchannel phase error of benchmark were adjusted in the scope of permission, the digital signal after the ADC244 conversion reflected that promptly the needed phase place of respective channel is adjusted parameter in normal operation.When circuit end initial phase entered normal operating conditions, this parameter values was adjusted signal through exporting after the DAC246 conversion to the phase matched of respective channel filter by 245 lockings of LATCH circuit.

It is necessary increasing ADC244, LATCH245 and DAC246 in the PLL circuit.If utilizing common PLL simulaed phase locked loop controls the phase error of passage, owing to keep analog signal very difficult, particularly under long operating state, need constantly refresh analog control signal, thereby make that the continuous duty of circuit is interrupted.

The 243rd, charge pump current source match control circuit, be the charging and the discharging current automatic trimming circuit (CHARGE PUMP CURRENT AUTO-TRIM) of a charge pump, its major function is to adjust the consistency of charging and discharging current size in the charge pump, thereby improves the susceptibility of circuit control channel phase error.When the charge and discharge size of current did not match, the fixed error in the time of can introducing the phase place adjustment can not meet the demands channel performance.

The logic input (LOGIC INPUT) of circuit chip is used for the various functions of control circuit, auxiliary circuit (AUXILIARY CIRCUIT) 26 is mainly finished functions such as voltage reference, digital sine wave generator (SineWaveform GENERATOR) produces the sine wave of low frequency, use for phase error test and adjustment in system initialisation phase, timer (TIMER) 27, the control channel phase control loop is the operating time of phase error control module 24 at initial phase, and the length of time is determined according to adjusting precision.After initial phase finished, digital modulation module 21 sine wave signal input internally switched to external data input (DATA INPUT).

Referring to Fig. 5, it is a kind of enforcement circuit of high performance phase error detection circuit, utilize single voltage comparator and digital module to realize, single voltage comparator mainly is made up of voltage comparator COM1, DC insert module (DCinsert), switching logic (switch logic), electronic switch SW1, SW2, and digital module comprises 3 transmission gates, 5 inverters (inv) and phase error detection logic (phase error detectorlogic).All the other are auxiliary circuit, comprise that voltage comparator COM2, rising edge detect and logic (risingedge detector ﹠amp; Logic) circuit, trailing edge detect and logic (falling edge detector ﹠amp; Logic) circuit, startup and end logical circuit (start ﹠amp; End logic), mcs logic (mcs logic) circuit.Mcs logic (mcs logic) circuit and transmission gate, inverter connect and compose passage gating module, and phase error detection logic (phase error detector logic) output signal is PEOUT.

Single voltage comparator can detect to high consistency interchannel phase error, can not be subjected to the influence of module performance, and the digital processing part, by increasing synchronously or delay control circuit improves the circuit consistency of two passages, as two transmission gates of design and two inverters between node N1, the N2, a transmission gate of design and three inverters have used identical device in two passages between node N1, the N3.

Two input signal OUTPUT I and OUTPUT Q by electronic switch SW1, SW2 gating after, through being capacitively coupled to the positive input terminal of voltage comparator COM1, the negative input end of voltage comparator COM1 connects the VCOM level, between two inputs of COM1 with high resistant direct current (DC insert) mode coupling and.The positive input terminal of voltage comparator COM2 is connected with level OUTPUTI, and negative input end is connected with VCOM after level translation (250mv shift).Starting with the end logical circuit has 3 inputs and 1 output, and 3 input signals are respectively the output signals of COM2, start and END logical signal, and an output is that rising edge detects and logic (risingedge detector ﹠amp; Logic) circuit input, rising edge detects and logic (rising edgedetector ﹠amp; Logic) circuit and trailing edge detect and logic (falling edge detector ﹠amp; Logic) mutual transmitting control logical signal between the circuit, rising edge detection and logical circuit detect with trailing edge and are connected with RESET and the SET signal end of COM1 respectively with the output of logical circuit, and connect switching logic simultaneously two inputs of (SWITCHLOGIC).The output of COM1 (node N1) admission passage gating module, its signal processing channel is by the MCS logic control, the output of passage gating module connects the input of phase error detection logic (PHASEERROR DETECTOR LOGIC), and the last output duty cycle of phase error detection logic is subjected to the pulse digital signal PEOUT of phase error control.

Voltage comparator COM2 detects the state of CHANNEL I, and its output is as the startup and end logic (the START ﹠amp of testing circuit; END LOGIC) a input, when enable logic is effective, rising edge testing circuit (RISING EDGE DETECTOR ﹠amp; LOGIC) start working, its output signal control switch logic (SWITCHLOGIC), gating SW1 or SW2 successively detect the rising edge zero crossing of CHANNEL I and CHANNEL Q output signal OUTPUT I, OUTPUT Q; When two rising edges detect finish after, begin to detect the trailing edge zero crossing of two channel C HANNEL I and CHANNEL Q output signal OUTPUT I, OUTPUT Q, by under rise along testing circuit (FALLING EDGE DETECTOR ﹠amp; LOGIC) finish two trailing edges and detect after, duplicate detection rising edge, trailing edge for the second time again ....COM1 and COM2 import each other, export, and the another one of COM1 is input as the startup of testing circuit and finishes logic (START ﹠amp simultaneously; END LOGIC) output signal.

Passage gate logic MCS is used to distinguish rising edge and trailing edge, and rising edge is handled according to passage N1--N2, and trailing edge is handled according to N1--N3.In phase error detection logical circuit (PHASE ERROR DETECTORLOGIC), finish the conversion of phase error to pulse duty factor.

Can introduce back in voltage comparator between the dead zone to reduce the influence that noise etc. brings, the influence to two passages is identical between the dead zone owing to return, and can not constitute influence to the detection of phase error.

Owing to only used a voltage comparator in the processing section of analog signal, its influence to CHANNEL I and CHANNEL Q is identical, thereby has reduced the influence that the finite gain of voltage comparator drift (OFFSET) voltage and comparator and the coupling that gains etc. are brought phase error detection effectively.

And,, guarantee that perhaps the delay error that interchannel is handled has matching relationship as long as utilize same digital channel that the phase error of two passages is handled in the digital processing part, just can divide the accuracy of detection that guarantees phase error in digital processes.

Utilize the univoltage comparator of Fig. 5 to carry out the work wave of phase error detection shown in Fig. 6, the detection of phase error is with the rising edge of pulse or the trailing edge starting point as phase error computation.

Referring to Fig. 8, be currents match and the automatic calibration circuit of realizing high-precision charge pump charging and discharge.Charge pump circuit is connected and composed by reference current source generating circuit shown in Figure 7, buffering output stage and ON-OFF control circuit.Charge pump current source match control circuit is connected to form by error current testing circuit, current amplification circuit, current-to-voltage converting circuit, recurrence control circuit, latch (LATCH) and digital to analog converter (DAC).

The error current testing circuit is by electronic switch SW1, SW2, SW3, operational amplifier A 1, A2, A3, transistor M1, M2, M3, M4, M5, M6, M7, M13, M14, M15, M16, M0, M12, M8, M9, M10, M11, M17, M18, M19, M20 connect and compose.Wherein transistor M8, M9, M10, M11 connect and compose current amplification circuit, and M17, M18, M19, M20 connect and compose current amplification circuit, are that the electric current that the size by M8, M9 and M10, M11 and M17, M18 and M19, M20 constitutes amplifies.Operational amplifier A 4 and resistance R 4 connect and compose current/voltage (I/V) change-over circuit, and the recurrence control circuit is arranged on the digital recursive controller in the analog to digital converter (ADC).

The positive input terminal of operational amplifier A 1, A2, A3, A4 is connected with reference voltage V REF.The negative input end of A1 is connected with the source electrode of resistance R 1 and transistor M1, and the output of A1 is connected with the M1 grid, M1 drain electrode and transistor M2, M4, the grid of M6 and the drain electrode of M3 connect, bias voltage VbiasP1 and M3, M5, the grid of M7 connects, M3, M5, M7 constitutes reference current source (CASCODE), M2, M4, M6 are current mirror.Transistor M13, the grid of M15 is connected with bias voltage VbiasN1, and transistor M14 connects in the diode mode, and its grid is connected with electric current output node and M16 grid in the digital-to-analogue conversion (DAC).SW2 one end connects the drain electrode of M15, and the SW2 other end connects SW1, SW3 and capacitor C cp, SW3 connected node N1, and SW1 connects the drain electrode of M7.

Node N4 is connected with the negative input end of operational amplifier A 2, A3 and the source electrode of transistor M10, M12, the output 2 of A2, A3 is connected with the grid of transistor M10, M12 respectively, the grid of transistor M17, M19 is connected with bias voltage VbiasN2, transistor M18, the grid of M20 is connected with the drain electrode of transistor M17, M12.The grid of transistor M9, M11 is connected with bias voltage VbiasP2, and the grid of transistor M8, M10 is connected with the drain electrode of transistor M10, M9.Node N5 is connected with the drain electrode of transistor M11, M19, inserts the negative input end of A4 simultaneously, and resistance R 2 between the negative input end and output of A4, is converted to the variation of electric current the variation of voltage as the sensitive detection parts cross-over connection of electric current.Circuit constitutes deviation induction by current (error sensor) in this frame, finishes the current detecting of phase error.

ADC (adder/subtractor sign/speed decision adder/subtracter, mark/speed, judgement) by recursive controller the voltage of node N6 is utilized adder or subtracter, progressively convert it to logical value, after passing through latch circuit latches (LATCH) then, to adjust the grid of electric current access transistor M14, M16 by D/A converting circuit (DAC) by the electric current output node, realize the adjustment of mating at charging current in the charge pump and discharging current.

DAC is by logic decoder (digital-to-analog converter LOGIC digital-to-analogue conversion logic) and binary system current source (top in the DAC frame) and binary system electric current heavy (below in the DAC frame) formation, the output that current source and electric current sink is through after the switch combination, by the grid of same electric current output node access transistor M14, M16.The switch combination that current source or electric current are heavy, by the CA_sign logical signal decision that provides in the ADC change-over circuit, wherein the heavy switch of single current source or electric current is exported CA_b[4:0 by the logic that provides in the ADC change-over circuit] decision.

In Fig. 8, there is certain amplification between transistor M10 and M8, M20 and the M18, promptly their breadth length ratio is different, and the value of optimization is 31: 1,63: 1 or 127: 1.

The value of k is among the figure: 0.1%, and the binary system current source comprises discharging current k1 _Dis, k1 _Dis/ 2, k1 _Dis/ 4, k1 _Dis/ 8, k1 _Dis/ 16, the heavy charging current k1 that comprises of binary system electric current _Ch, k1 _Ch/ 2, k1 _Ch/ 4, k1 _Ch/ 8, k1 _Ch/ 16.

The present invention at first carries out from dynamic(al) correction the current deviation of charge pump, and the current deviation to the channel phases error carries out from dynamic(al) correction then.Carry out automatic timing at current deviation to charge pump, SW1, SW2, SW3 closure, when the last electric current of SW1 is gone up electric current greater than SW2, operational amplifier A 2 and transistor M0 end, and operational amplifier A 3 and transistor M12 work powers on node N6 to press liter thereby electric current enters node N5 from M17, M18, M19, M20 mirror image, ADC provides the conversion of a MSB, after passing through LATCH, DAC again, then the output current of DAC electric current output node is through the drain electrode of M13, and making SW2 go up electric current increases; Increase among the SW2 behind the electric current with SW1 in current ratio, when the last electric current of SW1 is gone up electric current less than SW2, operational amplifier A 2 and transistor M0 work, operational amplifier A 3 and transistor M12 end, and error current is through transistor M8, M9, M10, the laggard ingress N5 of M11 mirror image, cause the node N6 drops that powers on, the conversion of one MSB of ADC output, through behind LATCH, the DAC, then the output current of DAC electric current output node makes SW2 go up electric current and reduces through the drain electrode of M13.Repeat above recursive procedure, in ADC, arrive a last LSB.

Current deviation to the channel phases error carries out from dynamic(al) correction, promptly be to the channel phases error from dynamic(al) correction, this moment SW1, SW2 controlled, SW3 does not work, when control SW1 pulse duty factor greater than control SW2 pulse duty factor the time, capacitor C cp powers on and presses liter; When the pulse duty factor of control SW1 during less than the pulse duty factor of control SW2, it is low that capacitor C cp goes up voltage drop.Pulse duty factor is corresponding with the channel phases error.

Referring to Fig. 9, be the schematic diagram of adc circuit among Fig. 8 (recursive controller), with the ADC different (as the ADC among Fig. 2) of traditional structure, ADC herein will realize:

(1) coupling is adjusted the adaptation function in loop;

(2) judge the polarity of proofreading and correct;

(3) judge the foundation of proofreading and correct end;

(4) realize the conversion of simulation error to numeral.

In Fig. 9, voltage comparator COM1, COM2, COM3, the anode of COM4 inserts input voltage INPUT, the benchmark level that negative terminal inserts is successively decreased successively by VREF2P-VREF1P-VREF1N-VREF2N, when the phase error voltage of importing is between VREF1P and VREF1N, COM2, COM3 output is " 1 ", put CA_stop by the circuit that arrests a judgement (stop decision) and be " 1 ", think that phase error adjustment loop can meet the demands, finish the adjustment process of circuit this moment, enters normal operating conditions.

When COM4 is output as 0, think that the phase error voltage of input is big in the negative deviation of directivity, by step-length decision circuit (step decision) and and then by adder/subtracter, adopting step-length is that the adder of 2LSB is carried out recurrence; When COM4 is output as 1 and when COM3 is output as 0, think that the error of input is little in the negative deviation of directivity, by step-length decision circuit (step decision) and and then by adder/subtracter, adopting step-length is that the addition of 1LSB carries out recurrence; Simultaneously CA_sign is changed to 1, it is heavy promptly to insert current source, close current, by the CAb[4:0 of output] concrete control inserts which current source in the binary system current source.

When COM1 is output as 1, think that the phase error voltage of input is big in the positive deviation of directivity, by step-length decision circuit (step decision) and and then by adder/subtracter, adopting step-length is that the subtracter of 2LSB carries out recurrence; When COM2 is output as 1 and when COM1 is output as 0, think that the phase error voltage of input is little in the positive deviation of directivity, by step-length decision circuit (step decision) and and then by adder/subtracter, adopting step-length is that the subtraction of 1LSB carries out recurrence; Simultaneously CA_sign being changed to 0, promptly inserting heavy, the turn off current source of electric current, by the CA_b[4:0 of output] to insert which electric current of binary system electric current in heavy heavy in concrete control.

Figure 10 has provided the signal flow that the adc circuit operation realizes among Fig. 9.

Step 1001 is put CA_b[4:0]=00000;

Step 1002, when COM2 is output as 0 and COM3 when being output as 1, execution in step 1017 allows the CA_stop be " 1 ";

Step 1003 when COM2 output is not 0 and COM3 output when being not 1, allows the CA_stop be " 0 ";

Step

1004,1005,1006 when COM1 is output as 1 and COM2 when being output as 1, allows sign=1 and allow subtracter with step-length 2 recurrence;

Step

1007,1008,1009, COM1 output be not 1 and COM2 output be not 1, when COM1 is output as 0 and COM2 when being output as 1, allow sign=1 and allow subtracter with step-length 1 recurrence;

Step

1013,1014,1015, COM1 be output as be not 0 and COM2 output be not 1, when COM4 is output as 1, COM3 is output as 0 and COM2 when being output as 0, allow sign=1, allow adder with step-length 2 recurrence;

Step

1010,1011,1012, be not 1 in COM4 output, COM3 output be not 0 and COM2 output be not 0, when COM3 is output as 0 and COM4 when being output as 1, allow sign=1, with allow adder with step-length 1 recurrence, when COM3 output is not 0 and COM4 output when being not 1, execution in step 1017 allows the CA_stop be " 1 ";

Step 1016 after the execution of

step

1006,1009,1012,1015, allows after this two clock cycle vacant (IDEL 2 CLOCK).

As can be seen, the adc circuit of Fig. 9 is actually a controller that carries out recurrence by addition or subtraction from above-mentioned flow process.

The present invention is by being provided with charge pump current source match control circuit, the precision of charge pump can be controlled in the 1LSB of requirement (LSB is the representation of precision, is 1% as required precision, i.e. 7 bit accuracy, 1LSB is last position in 7 bits).

The channel phases error of the technology of the present invention is adjusted scheme, has the precision height, can not be suitable for being made into integrated chip along with prolong and the advantage of appearance adjustment error service time, is adapted at high performance system, uses in the GPRS pattern chip design as GSM.

Claims

1. a method utilizing phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching, is characterized in that comprising following processing steps:

A. Set the phase of the reference channel to a fixed value, and the phase error detector converts the phase error of the analog signal output by the channel to be adjusted and the reference channel into a pulse digital signal whose duty ratio varies with the phase error, and input it to the channel to be adjusted It is the same signal as the reference channel;

B. The pulse digital signal controls the charging time and discharging time of the charge pump, and obtains the charge pump voltage reflecting the magnitude and polarity of the phase error;

C. The charge pump voltage is converted by an analog-to-digital converter into a digital control signal for phase matching adjustment of the channel to be adjusted;

D. The digital control signal is converted into an adjustment signal for phase matching adjustment of the channel to be adjusted by a digital-to-analog converter, so that the phase of the channel to be adjusted is kept consistent with the phase of the reference channel.

2. A method of utilizing a phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 1, characterized in that: said steps A to D are closed-loop working states in the circuit power-on initialization stage After the initialization phase is completed, the digital control signal obtained in step C is latched by the latch, and then converted into a fixed adjustment signal for phase matching adjustment of the channel to be adjusted by the digital-to-analog converter in step D. The circuit Work in an open-loop working state.

3. a kind of method utilizing phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 1, is characterized in that: the analog signal in the described step A is in the initial stage of circuit power-on, by The digital sine wave signal generated by the digital sine wave generator is obtained after digital modulation, digital-to-analog conversion, filtering and power drive.

4. a kind of method utilizing phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 2 or 3, is characterized in that: described power-on initialization stage is according to the requirement of phase matching adjustment accuracy, By selecting the timing length of the timer, the timer controls the repeated execution time of steps A to D.

5. a kind of method utilizing phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 1, is characterized in that: the phase error detection in the described step A further comprises:

a1. Send two analog signals to the positive input terminal of a voltage comparator COM1, and compare it with the VCOM level connected to the negative input terminal. The positive and negative input terminals of the voltage comparator COM1 are connected with high impedance DC coupling;

a2. Connect the positive input terminal of another voltage comparator COM2 to the analog signal of the reference channel, and connect the negative input terminal to the reference voltage VCOM after level shifting;

a3. Select and detect the rising edge zero-crossing point and falling edge zero-crossing point of the output analog signal of the reference channel and the channel to be adjusted successively, and execute repeatedly;

a4. The channel gating logic MCS distinguishes the rising edge and the falling edge, so that the rising edge is processed according to the channel from the node N1--N2, and the falling edge is processed according to the channel from the node N1--N3;

a5. The phase error is converted into the pulse duty ratio in the phase error detection logic circuit.

6. A kind of method utilizing phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 5, is characterized in that: in described step a4, by the channel of node N1--N2 and by node The channels of N1--N3 are realized by connecting logic gates of the same number and nature to form a synchronous or delay control circuit.

7. A kind of method utilizing phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 1, is characterized in that: in the described step B, also comprise the charging and discharging current of setting a charge pump Automatic fine-tuning circuit to adjust the consistency of charging current and discharging current in the charge pump.

8. A kind of method utilizing phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 7, it is characterized in that: described adjustment further comprises:

b1. The charge and discharge current deviation of the charge pump is sensed by the deviation current sensing circuit, and the charge and discharge current deviation is converted into the rise and fall of the node voltage, and used as the input voltage of the analog-to-digital converter;

b2. The analog-to-digital converter gives a conversion of the most significant bit MSB or the conversion of the second most significant bit MSB according to the rise or fall of the input voltage, and performs recursive control;

b3. After the output of the analog-to-digital converter is latched and digital-to-analog converted, the output current is controlled to reduce the deviation of the charging and discharging current;

b4. Repeat the recursive process of steps b1 to b3 until conversion to the least significant bit LSB in the analog-to-digital converter.

9. A kind of method utilizing phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 8, it is characterized in that: in described step b2, b3, the realization of analog-to-digital conversion further comprises the following processing steps :

b5. Let the comparison reference levels of the negative input terminals of the four voltage comparators COM1, COM2, COM3, and COM4 decrease sequentially from VREF2P-VREF1P-VREF1N-VREF2N, and input the input voltage of the analog-to-digital converter into the four voltage comparators COM1 , COM2, COM3, COM4 positive phase input;

b6. When the input voltage is between VREF1P and VREF1N, and the outputs of the voltage comparators COM2 and COM3 are both "1", it is determined that the adjustment circuit meets the requirements of channel phase matching, and a signal to stop the adjustment is output;

b7. When VREF2N is greater than the input voltage and the output of the voltage comparator COM4 is "0", it is determined that the negative deviation of the phase error between the channel to be adjusted and the reference channel is large, and the recursion is carried out by adding the step size to 2 times the least significant bit 2LSB. Simultaneously output a control signal for accessing the current source to the digital-to-analog converter;

b8. When VREF2N is less than the input voltage, the output of voltage comparator COM4 is "1", and VREF1N is greater than the input voltage, and the output of voltage comparator COM3 is "0", it is determined that the negative deviation of the phase error between the channel to be adjusted and the reference channel is small , the recursion is carried out by adding with a step size of 1 times the least significant bit 1LSB, and at the same time outputting a control signal for accessing the current source to the digital-to-analog converter;

b9. When VREF2P is less than the input voltage and the voltage comparator COM1 output is "1", it is determined that the positive deviation of the phase error between the channel to be adjusted and the reference channel is large, and the subtraction with a step size of 2 times the least significant bit 2LSB is used for recursion. Simultaneously output the signal connected to the current sink to the digital-to-analog converter;

b10. When VREF1P is less than the input voltage, the output of voltage comparator COM2 is "1", and when VREF2P is greater than the input voltage, the output of voltage comparator COM1 is "0", it is determined that the positive deviation of the error between the channel to be adjusted and the reference channel is small , the recursion is carried out by subtraction with a step size of 1 times the least significant bit 1LB, and at the same time, a signal for accessing the current sink is output to the digital-to-analog converter.

10. A circuit utilizing a phase-locked loop PLL to control optical baseband modulation multi-channel phase matching, characterized in that:

Including phase error detection circuit, charge pump circuit, charge pump current source matching control circuit, analog-to-digital conversion circuit, latch circuit and digital-to-analog conversion circuit;

One input end of the phase error detection circuit is connected to the output end of the analog signal of the reference channel, the phase of the reference channel is set to a fixed value, the other input end of the phase error detection circuit is connected to the output end of the analog signal of the channel to be adjusted, and the phase error detection circuit Convert the phase error of the analog signal of the reference channel and the channel to be adjusted into a pulse digital signal whose duty cycle varies with the error and input it into the charge pump circuit. The pulse digital signal controls the charge pump circuit with the support of the charge pump current source matching control circuit The length of charging and discharging time, output the charge pump voltage reflecting the size and polarity of the phase error and send it to the analog-to-digital conversion circuit, the analog-to-digital conversion circuit converts the charge pump voltage into a digital control signal for phase matching adjustment of the channel to be adjusted and sends it to the lock The digital-to-analog conversion circuit converts the digital control signal output by the latch into a phase adjustment parameter signal of the channel to be adjusted.

11. A kind of circuit that utilizes phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 10, is characterized in that: described phase error detection circuit is formed by the connection of single voltage comparator and digital module; The single voltage comparator includes a voltage comparator whose negative input terminal is connected to the reference voltage VCOM, a DC plug-in module coupled between the positive and negative input terminals of the voltage comparator, and first and second voltage comparators connected to the positive input terminal of the voltage comparator. Electronic switch, the first and second electronic switches are respectively connected to the output terminals of the analog signals of the two matching channels, the output terminal of the switching logic is connected to the control terminals of the first and second electronic switches, the input terminal of the switching logic and the reset of the voltage comparator and the setting terminal are respectively connected to the output terminals of the rising edge detection and logic module and the falling edge detection and logic module; the digital module includes two transmission channels composed of transmission gates and inverter connections, a channel gating module and a phase error detection logic module, the channel gating module is connected with the transmission gate, the output terminal of the voltage comparator is connected with two transmission channels, and the two transmission channels are connected with a phase error detection logic module.

12. A circuit that utilizes a phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 10, characterized in that: the charge pump current source matching control circuit is composed of a phase error current detection circuit, A current amplification circuit, a current-voltage conversion circuit, a recursive control circuit, a latch circuit and a digital-to-analog conversion circuit are sequentially connected.

13. A kind of circuit that utilizes phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 12, it is characterized in that: described recursive control circuit is an analog-to-digital converter, comprising first, second Two, the third, the fourth voltage comparator, the stop adjustment judgment module, the step size judgment module and the adder/subtractor module; the positive input terminals of the first, second, third and fourth voltage comparators are connected to the input voltage, The negative input terminals are connected to decreasing reference voltages VREF2P, VREF1P, VREF1N, VREF2N, the output terminals of the first and fourth voltage comparators are connected to the step size judging module, and the output terminals of the step size judging module are connected to the adder/subtractor module, the second, The output terminal of the third voltage comparator and the output terminal of the adder/subtractor module are connected to the stop adjustment judging module.

14. A circuit that utilizes a phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 12, wherein the digital-to-analog conversion circuit is composed of a logic decoder, a binary current source, a binary current The combined switch of the source, the binary current sink and the combined switch of the binary current sink are connected; the output of the logic decoder controls the combined switch of the binary current source and the binary current sink respectively. After the output of the binary current source and the binary current sink passes through the combined switch, The phase error current detection circuit is connected through the same current output node.

15. A kind of circuit that utilizes phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 10, it is characterized in that: also comprise digital modulation module, multi-channel gain error control module, multi-channel analog processing Module, digital sine wave signal generator, auxiliary circuit and timer used to complete the voltage reference function; the digital sine wave signal generator is connected to the digital modulation module and the phase error control module, and is used to provide phase error testing and adjustment during the initialization phase; The timer is connected to the phase error control module to control the duration of the initialization phase; the digital modulation module, the multi-channel gain error control module, and the multi-channel analog processing module are sequentially connected to the channels to perform digital modulation on the input data or digital sine wave signals, and the channels Gain error adjustment and analog processing including digital-to-analog conversion, filtering and power drive; the phase error control module is connected to the reference channel of the multi-channel analog processing module and the channel to be adjusted, and the output is to the channel filter to be adjusted in the multi-channel analog processing module Delay control signal.

16. A circuit that utilizes a phase-locked loop PLL to control wireless baseband modulation multi-channel phase matching according to claim 15, characterized in that: said digital modulation module, multi-channel gain error control module, and multi-channel analog processing Modules, phase error control modules, digital sine wave signal generators, auxiliary circuits and timers are fabricated on an integrated chip circuit.