CN119451083A - Semiconductor structure and method for forming the same - Google Patents
Semiconductor structure and method for forming the same Download PDFInfo
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Abstract
一种半导体结构及其形成方法，半导体结构包括：基底，包括存储单元区，存储单元区包括沿第一方向延伸且沿第二方向相邻的子单元区，第一方向垂直于第二方向，子单元区包括：位于基底上且沿第一方向延伸并沿第二方向平行排布的第一沟道结构和第二沟道结构；横跨第一沟道结构和第二沟道结构的第一栅极结构，第一栅极结构与第一沟道结构构成下拉晶体管，第一栅极结构与第二沟道结构构成上拉晶体管；分立于第一沟道结构两侧的第二栅极结构，第二栅极结构与第一沟道结构构成传输门晶体管，且第二栅极结构与第一栅极结构沿第一方向平行排布。半导体结构的读取工作范围和写入工作范围能够得到减小或增大，从而能够提高了半导体结构的性能。
A semiconductor structure and a method for forming the same, the semiconductor structure comprising: a substrate, a memory cell region, the memory cell region comprising a sub-cell region extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction, the sub-cell region comprising: a first channel structure and a second channel structure located on the substrate and extending along the first direction and arranged in parallel along the second direction; a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure forming a pull-down transistor, the first gate structure and the second channel structure forming a pull-up transistor; a second gate structure separated on both sides of the first channel structure, the second gate structure and the first channel structure forming a transmission gate transistor, and the second gate structure and the first gate structure being arranged in parallel along the first direction. The read operating range and the write operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the current semiconductor industry, integrated circuit products are largely divided into three types, logic, memory, and analog circuits, where memory devices account for a significant proportion of integrated circuit products. With the development of semiconductor technology, memory devices are being used more widely, and it is required to form the memory devices on one chip together with other device regions to form an embedded semiconductor memory device. For example, the storage device is embedded in the cpu, so that the storage device is compatible with the embedded cpu platform, and the original specifications and corresponding electrical properties of the storage device are maintained.
In general, it is desirable to have the memory device compatible with embedded standard logic devices. For embedded semiconductor devices, they are generally divided into a logic region, which generally includes logic devices, and a memory region, which includes memory devices. With the development of Memory technology, various types of semiconductor memories such as static random access Memory (Static Random Access Memory, SRAM), dynamic random access Memory (Dynamic Random Access Memory, DRAM), erasable Programmable Read Only Memory (EPROM), electrically erasable programmable read Only Memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-Only, EEPROM), and Flash Memory (Flash) have emerged. Static random access memories and methods for forming the same are receiving more and more attention because of their low power consumption and faster operating speeds.
Performance of SRAM devices remains to be improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to improving the performance of the semiconductor structure.
In order to solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a storage unit region, a second gate structure and a transmission gate transistor, wherein the storage unit region comprises a subunit region extending along a first direction and adjacent along a second direction, the first direction is perpendicular to the second direction, the subunit region comprises a first channel structure and a second channel structure which are positioned on the substrate, extend along the first direction and are arranged in parallel along the second direction, a first gate structure stretches across the first channel structure and the second channel structure, the first gate structure and the first channel structure form a pull-down transistor, the first gate structure and the second channel structure form a pull-up transistor, the second gate structure and the first channel structure form a transmission gate transistor, and the second gate structure and the first gate structure are arranged in parallel along the first direction.
Optionally, the semiconductor structure further comprises a first source-drain doping layer, a second source-drain doping layer and a pull-down transistor, wherein the first source-drain doping layer is positioned in the first channel structure at two sides of the first gate structure and two sides of the second gate structure, the second source-drain doping layer is positioned in the second channel structure at two sides of the first gate structure, and the first source-drain doping layer of the pull-down transistor is electrically connected with the second source-drain doping of the pull-up transistor.
Optionally, the semiconductor structure further comprises a sharing plug, a source-drain plug, a gate plug and a first gate structure, wherein the sharing plug is positioned on the top of the first source-drain doped layer between the first gate structure and the second gate structure and extends along the second direction and is also positioned on the top of the second source-drain doped layer on the same side of the first gate structure, the source-drain plug is positioned on the top of the second source-drain doped layer on the other side of the first gate structure and the top of the remaining first source-drain doped layer, and the gate plug is positioned on the top of the first gate structure and is electrically connected with the first gate structure.
Optionally, the gate plug is further located on top of the shared plug of the adjacent subcell region, the gate plug being electrically connected to the shared plug of the adjacent subcell region.
Optionally, a source-drain plug on top of the second source-drain doped layer on the other side of the first gate structure is used for accessing VDD, and a source-drain plug on top of the first source-drain doped layer on the other side of the first gate structure is used for accessing VSS.
Optionally, the semiconductor structure further comprises a first word line, wherein the first word line is positioned at the top of the second grid structure at one side of the first channel structure and is electrically connected with the second grid structure, and the second word line is positioned at the top of the second grid structure at the other side of the first channel structure and is electrically connected with the second grid structure.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a storage unit region, the storage unit region comprises a subunit region extending along a first direction and adjacent along a second direction, the first direction is perpendicular to the second direction, a first channel structure and a second channel structure which extend along the first direction and are arranged in parallel along the second direction are formed on the substrate in the subunit region, a first grid structure crossing the first channel structure and the second channel structure is formed, the first grid structure and the first channel structure form a pull-down transistor, the first grid structure and the second channel structure form a pull-up transistor, a second grid structure which is separated from two sides of the first channel structure is formed, the second grid structure and the first channel structure form a transmission gate transistor, and the second grid structure and the first grid structure are arranged in parallel along the first direction.
Optionally, after forming the first gate structure and the second gate structure, the forming method further comprises forming a first source-drain doped layer in the first channel structure at both sides of the first gate structure and at both sides of the second gate structure, forming a second source-drain doped layer in the second channel structure at both sides of the first gate structure, and electrically connecting the first source-drain doped layer of the pull-down transistor with the second source-drain doped layer of the pull-up transistor.
Optionally, the step of forming the first gate structure and the second gate structure includes forming a first dielectric layer on top of the substrate of the sub-unit region to cover the first channel structure and the second channel structure, forming a first opening in the first dielectric layer to expose portions of the top and sidewalls of the first channel structure and the second channel structure, forming a second opening in the first dielectric to expose portions of the top and sidewalls of the first channel structure, the first opening and the second opening extending in a second direction and being arranged in parallel in the first direction, forming a gate material layer in the first opening and the second opening, planarizing the gate material layer located in the second opening such that the top of the remaining gate material layer in the second opening is level with the top of the first channel structure, using the gate material layer located in the first opening as the first gate structure, and using the remaining gate material layer located in the second opening as the second gate structure.
Optionally, after forming the first source-drain doped layer and the second source-drain doped layer, the method further comprises forming a shared plug on top of the first source-drain doped layer located between the first gate structure and the second gate structure and on top of the second source-drain doped layer extending along the second direction and located on the same side of the first gate structure, forming a source-drain plug on top of the second source-drain doped layer located on the other side of the first gate structure and on top of the remaining first source-drain doped layer, forming a gate plug on top of the first gate structure, and electrically connecting the first gate structure with the gate plug.
Optionally, in the step of forming the gate plug, the gate plug is further located on top of the shared plug of the adjacent subcell region, and the gate plug is electrically connected to the shared plug of the adjacent subcell region.
Optionally, in the step of forming the source-drain plug, the source-drain plug formed on top of the second source-drain doped layer on the other side of the first gate structure is used for accessing VDD, and the source-drain plug formed on top of the first source-drain doped layer on the other side of the first gate structure is used for accessing VSS.
Optionally, after forming the second gate structure separated from two sides of the first channel structure, the method further comprises forming a first word line on top of the second gate structure on one side of the first channel structure and electrically connected with the second gate structure, and forming a second word line on top of the second gate structure on the other side of the first channel structure and electrically connected with the second gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
According to the semiconductor structure provided by the embodiment of the invention, the second grid structures which are separated from the two sides of the first channel structure are arranged, the second grid structures and the first channel structure form the transmission gate transistor, the second grid structures and the first grid structures are arranged in parallel along the first direction, and the voltage signals can be independently and respectively applied to the second grid structures on the two sides of the first channel structure or simultaneously applied to the second grid structures on the two sides of the first channel structure by arranging the second grid structures which are separated from the two sides of the first channel structure, so that the current of the transmission gate transistor can be reduced or increased, namely the reading working range and the writing working range of the semiconductor structure can be reduced or increased, and the performance of the semiconductor structure can be improved.
Drawings
FIGS. 1-2 are schematic diagrams illustrating a semiconductor structure according to an embodiment of the present invention;
fig. 3 to 9 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of current semiconductor structures is to be improved, in particular, the read operating range of SRAM devices is determined by beta ratio (I pd/Ipg) and the write operating range of SRAM devices is determined by gamma ratio (Ipg/Ipu), but the Ipg value is fixed while the SRAM devices are in operation, resulting in the read operating range and write operating range of the SRAM devices not being amplified or reduced.
In order to solve the technical problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a storage unit region, a second gate structure, a transmission gate transistor and a first gate structure, wherein the storage unit region comprises a subunit region extending along a first direction and adjacent along a second direction, the first direction is perpendicular to the second direction, the subunit region comprises a first channel structure and a second channel structure which are positioned on the substrate, extend along the first direction and are arranged in parallel along the second direction, the first gate structure spans the first channel structure and the second channel structure, the first gate structure and the first channel structure form a pull-down transistor, the first gate structure and the second channel structure form a pull-up transistor, the second gate structure is separated from the two sides of the first channel structure, the second gate structure and the first channel structure form the transmission gate transistor, and the second gate structure and the first gate structure are arranged in parallel along the first direction.
In the semiconductor structure provided by the embodiment of the invention, the second gate structures separated from the two sides of the first channel structure are arranged, the second gate structures and the first channel structure form the transmission gate transistor, and the second gate structures and the first gate structures are arranged in parallel along the first direction, and by arranging the second gate structures separated from the two sides of the first channel structure, voltage signals can be independently and respectively applied to the second gate structures on the two sides of the first channel structure, or voltage signals can be simultaneously applied to the second gate structures on the two sides of the first channel structure, so that the current of the transmission gate transistor can be reduced or increased, namely the reading working range and the writing working range of the semiconductor structure can be reduced or increased, and the performance of the semiconductor structure can be improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1-2 are schematic structural diagrams of an embodiment of a semiconductor structure according to the present invention. Fig. 1 is a top view of the semiconductor structure, and fig. 2 is a cross-sectional view of fig. 1 along the BB direction.
The semiconductor structure includes a substrate 201 including a memory cell region 200A, the memory cell region 200A including a sub-cell region 200B extending in a first direction (shown as X-direction in fig. 1) and adjacent in a second direction (shown as Y-direction in fig. 1), the first direction being perpendicular to the second direction, the sub-cell region 200B including a first channel structure 202 and a second channel structure 203 on the substrate 201 and extending in the first direction and arranged in parallel in the second direction, a first gate structure 210 crossing the first channel structure 202 and the second channel structure 203, the first gate structure 210 and the first channel structure 202 forming a pull-down transistor, the first gate structure 210 and the second channel structure 203 forming a pull-up transistor, a second gate structure 212 being separated on both sides of the first channel structure 202, the second gate structure 212 and the first channel structure 202 forming a transfer gate transistor, and the second gate structure 212 and the first gate structure 210 being arranged in parallel in the first direction.
It should be noted that, by providing the second gate structures 212 separately on both sides of the first channel structure 202, a voltage signal can be applied to the second gate structures 212 on both sides of the first channel structure 202 separately, or a voltage signal can be applied to the second gate structures 212 on both sides of the first channel structure 202 at the same time, so that the current of the pass gate transistor can be reduced or increased, that is, the read operation range and the write operation range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.
The substrate 201 provides a process platform for providing a semiconductor structure.
In this embodiment, the base 201 includes a substrate.
The material of the substrate is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the semiconductor structure is an SRAM device, which includes a plurality of memory cell regions 200A.
Specifically, in the SRAM device, the plurality of memory cell regions 200A are arranged in a matrix in the first direction and the second direction.
In this embodiment, the memory cell region 200A includes sub-cell regions 200B extending in a first direction and adjacent in a second direction, the first direction being perpendicular to the second direction.
Specifically, each of the subcell regions 200B includes a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region.
Specifically, the pass gate transistor region is used to form a pass gate transistor, the pull-down transistor region is used to form a pull-down transistor, and the pull-up transistor region is used to form a pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.
The first channel structure 202 is used to provide a conductive channel for the pull-down transistor and the pass-gate transistor and the second channel structure 203 is used to provide a conductive channel for the pull-up transistor.
In this embodiment, the materials of the first channel structure 202 and the second channel structure 203 are both silicon. In other embodiments, the material of the first channel structure 202 and the second channel structure 203 may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the material of the first channel structure 202 may also be different from the material of the substrate.
It should be noted that the first gate structure 210 is used to control the turn-on and turn-off of the conduction channels of the pull-down transistor and the pull-up transistor, and the second gate structure 212 is used to control the turn-on and turn-off of the conduction channels of the pass-gate transistor.
The first gate structure 210 spans the first channel structure 202 and the second channel structure 203, that is, the first gate structure 210 covers the top and sidewalls of the fin.
It should be further noted that, by providing the second gate structures 212 separately disposed on both sides of the first channel structure 202, a voltage signal can be applied to the second gate structures 212 on both sides of the first channel structure 202 separately, or a voltage signal can be applied to the second gate structures 212 on both sides of the first channel structure 202 at the same time, so that the current of the pass gate transistor can be reduced or increased, that is, the read operation range and the write operation range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.
Specifically, the read operation range of the SRAM device is determined by the beta ratio (I pd/Ipg), the write operation range of the SRAM device is determined by the gamma ratio (I pg/Ipu), and the beta ratio and the gamma ratio of the SRAM device are made larger or smaller by controlling the current of the pass gate transistor to be increased or decreased, so that the read operation range and the write operation range of the SRAM device can be reduced or increased.
In this embodiment, the first gate structure 210 and the second gate structure 212 are both metal gate structures, the first gate structure 210 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, and the second gate structure 212 also includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer.
The gate dielectric layer is used to electrically isolate the gate electrode layer from the first channel structure 202 and to electrically isolate the gate electrode layer from the second channel structure 203.
The gate dielectric layer material includes one or more of HfO 2、ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、SiO2 and La 2O3.
In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO 2、ZrO2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO, al 2O3, or the like.
The gate dielectric layer may further include a gate oxide layer, where the gate oxide layer is located between the high-k gate dielectric layer and the first channel structure 202, and between the high-k gate dielectric layer and the second channel structure 203. Specifically, the material of the gate oxide layer may be silicon oxide.
In this embodiment, one or more of the materials TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC of the gate electrode layer.
Specifically, the gate electrode layer includes a work function layer (not shown), and an electrode layer (not shown) located on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electricity of the metal gate structure.
In other embodiments, the first gate structure and the second gate structure may also be polysilicon gate structures according to process requirements.
It should be noted that, as an example, the pass gate transistor and the pull-down transistor share the same first channel structure 202 to meet the operation requirement of the SRAM device.
As an example, the pull-down transistor and the pull-up transistor share a first gate structure 210 to meet the operating requirements of the SRAM device.
In this embodiment, the semiconductor structure further includes a first source-drain doped layer (not shown) disposed in the first channel structure 202 on both sides of the first gate structure 210 and on both sides of the second gate structure 212.
The first source-drain doped layer is used as a source region and a drain region of a pull-down transistor and is used as a source region and a drain region of a pass gate transistor.
The doping type of the first source-drain doping layer is the same as the channel conductivity type of the corresponding transistor.
Since the pass gate transistor and the pull-down transistor are both N-type transistors, the doping type of the first source-drain doping layer is N-type.
It should be noted that, as an example, in the formation process of the first channel structure 202, the first channel structure 202 has doping ions, and the doping type is the same as that of the first source-drain doping layer.
The first channel structure 202 has doped ions and has the same doping type as the first source-drain doped layer, so that the pass gate transistor and the pull-down transistor both adopt junction-free field effect transistors (Junctionless FieldEffect Transistor, JLT), which is beneficial to simplifying the formation process and steps of the SRAM device.
In this embodiment, the semiconductor structure further includes a second source-drain doped layer (not shown) disposed in the second channel structure 203 at both sides of the first gate structure 210.
The second source-drain doped layer is used as a source region and a drain region of the pull-up transistor.
The doping type of the second source-drain doping layer is the same as the channel conductivity type of the corresponding transistor.
Since the pull-up transistor is a P-type transistor, the doping type of the second source-drain doping layer is P-type.
Note that, as an example, in the formation process of the second channel structure 203, the second channel structure 203 has doping ions, and the doping type is the same as that of the second source-drain doping layer.
The second channel structure 203 has doped ions and has the same doping type as the second source/drain doped layer, so that the pull-up Transistor adopts a junction-free field effect Transistor (Junctionless FIELD EFFECT Transistor, JLT), which is beneficial to simplifying the formation process and steps of the SRAM device.
That is, after the first channel structure 202 and the second channel structure 203 having the doped ions are formed, the source-drain doping is not required, but the first channel structures 202 on both sides of the first gate structure 210 and on both sides of the second gate structure 212 are directly used as the first source-drain doping layers, and the second channel structures 203 on both sides of the first gate structure 210 are used as the second source-drain doping layers, so that the junction-free field effect transistor is formed, and the difficulty in forming the semiconductor structure is greatly reduced.
In this embodiment, the second source-drain doped layer of the pull-up transistor is electrically connected to the first source-drain doped layer of the pull-down transistor.
Specifically, in each sub-cell region 200B, the drain region of the pull-up transistor is connected to the drain region of the pull-down transistor, and the pull-up transistor and the pull-down transistor share the first gate structure 210, so that in the adjacent two sub-cell regions 200B, the pull-up transistor and the pull-down transistor respectively constitute a first CMOS transistor and a second CMOS transistor, an input terminal of the first CMOS transistor is connected to an output terminal of the second CMOS transistor, and an output terminal of the first CMOS transistor is connected to an input terminal of the second CMOS transistor.
In this embodiment, the semiconductor structure further includes a sharing plug 228 located on top of the first source-drain doped layer between the first gate structure 210 and the second gate structure 212 and extending in the second direction also located on top of the second source-drain doped layer on the same side of the first gate structure 210.
Note that the sharing plug 228 electrically connects the first source-drain doped layer between the first gate structure 210 and the second gate structure 212 with the second source-drain doped layer extending in the second direction and also located on the same side of the first gate structure 210, so that in each sub-cell region 200B, the drain region of the pull-up transistor is electrically connected with the drain region of the pull-down transistor.
In this embodiment, the material of the shared plug 228 is tungsten. In other embodiments, the material of the shared plug may also be cobalt or ruthenium.
In this embodiment, the semiconductor structure further includes a source-drain plug 226 on top of the second source-drain doped layer on the other side of the first gate structure 210 and on top of the remaining first source-drain doped layer.
The source-drain plug 226 is used to electrically lead out the first source-drain doped layer and the second source-drain doped layer, so that in each sub-unit region 200B, the source regions of the pull-up transistors are all connected to the power supply voltage, the source regions of the pull-down transistors are all connected to the power supply voltage, and the source regions of the pass-gate transistors are connected to the bit line BL.
In this embodiment, the source-drain plug 226 on top of the second source-drain doped layer on the other side of the first gate structure 210 is used to access VDD.
Specifically, VDD represents the operating positive voltage of the access.
In this embodiment, the source-drain plug 226 on top of the first source-drain doped layer on the other side of the first gate structure 210 is used to access VSS.
Specifically, VSS represents the operating negative voltage that is switched in.
In this embodiment, the source/drain plug 226 is made of tungsten. In other embodiments, the material of the source-drain plug may be cobalt or ruthenium.
In this embodiment, the semiconductor structure further includes a gate plug 230 disposed on top of the first gate structure 210, and the first gate structure 210 is electrically connected to the gate plug 230.
The gate plug 230 is used to electrically lead out the first gate structure 210, so as to control the conductive channels of the first channel structure 202 and the second channel structure 203.
In this embodiment, the gate plug 230 is further located on top of the sharing plug 228 of the adjacent sub-unit 200B, and the gate plug 230 is electrically connected to the sharing plug 228 of the adjacent sub-unit 200B.
In the adjacent two sub-cell regions 200B, the pull-up transistor and the pull-down transistor respectively constitute a first CMOS transistor and a second CMOS transistor, and the gate plug 230 is electrically connected to the shared plug 228 of the adjacent sub-cell region 200B, so that the input terminal of the first CMOS transistor is connected to the output terminal of the second CMOS transistor, and the output terminal of the first CMOS transistor is connected to the input terminal of the second CMOS transistor.
In this embodiment, the semiconductor structure further includes a first word line 261 located on top of the second gate structure 212 on one side of the first channel structure 202, and the first word line 261 is electrically connected to the second gate structure 212, and a second word line 260 located on top of the second gate structure 212 on the other side of the first channel structure 202, and the second word line 260 is electrically connected to the second gate structure 212.
Note that the first word line 261 and the second word line 260 are used to control the read operation and the write operation of the SRAM device.
It should be further noted that, by disposing the first word line 261 and the second word line 260 on both sides of the first channel structure 202, a voltage signal can be applied to the first word line 261 and the second word line 260, or a voltage signal can be applied to the first word line 261 and the second word line 260 at the same time, so that a current of the pass gate transistor can be reduced or increased, that is, a read operation range and a write operation range of the semiconductor structure can be reduced or increased, thereby improving performance of the SRAM device.
In this embodiment, the materials of the first word line 261 and the second word line 260 each include one or more of TiN, cu, and W.
Fig. 3 to 9 are schematic structural views corresponding to each step in an embodiment of a method for fabricating a semiconductor structure according to the present invention.
Referring to fig. 3, a substrate 101 is provided, the substrate 101 including a memory cell region 100A, the memory cell region 100A including a sub-cell region 100B extending in a first direction (shown as an X direction in fig. 3) and adjacent in a second direction (shown as a Y direction in fig. 3), the first direction being perpendicular to the second direction.
The substrate 101 provides a process platform for the formation process of the semiconductor structure.
In this embodiment, the base 101 includes a substrate.
The material of the substrate is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the semiconductor structure is an SRAM device, which includes a plurality of memory cell regions 100A.
Specifically, in the SRAM device, a plurality of memory cell regions 100A are arranged in a matrix in the first direction and the second direction.
In this embodiment, the memory cell region 100A includes sub-cell regions 100B extending in a first direction and adjacent in a second direction, and the first direction is perpendicular to the second direction.
Specifically, each of the subcell regions 100B includes a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region.
Specifically, the pass gate transistor region is used to form a pass gate transistor, the pull-down transistor region is used to form a pull-down transistor, and the pull-up transistor region is used to form a pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.
Referring to fig. 4, in the sub-unit region 100B, a first channel structure 102 and a second channel structure 103 extending in a first direction and arranged in parallel in a second direction are formed on a substrate 101.
Specifically, the first channel structure 102 is used to provide a conductive channel for the pull-down transistor and the pass-gate transistor, and the second channel structure 103 is used to provide a conductive channel for the pull-up transistor.
In this embodiment, the materials of the first channel structure 102 and the second channel structure 103 are both silicon. In other embodiments, the material of the first channel structure 102 and the second channel structure 103 may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the material of the first channel structure 102 may also be different from the material of the substrate.
In this embodiment, the step of forming the first channel structure 102 and the second channel structure 103 includes forming a channel material layer (not shown) on the substrate 101, forming a first mask layer (not shown) and a second mask layer (not shown) on top of the channel material layer, each of the first mask layer and the second mask layer extending along a first direction and being arranged in parallel along a second direction, and patterning the channel material layer using the first mask layer and the second mask layer as masks, to form the first channel structure 102 and the second channel structure 103 extending along the first direction and being arranged in parallel along the second direction on the substrate 101.
In this embodiment, the process of patterning the channel material layer includes a dry etching process.
Referring to fig. 5 and 6, in which fig. 5 is a top view, fig. 6 is a cross-sectional view along the AA direction of fig. 5, forming a first gate structure 110 crossing the first channel structure 102 and the second channel structure 103, the first gate structure 110 and the first channel structure 102 forming a pull-down transistor, the first gate structure 110 and the second channel structure 103 forming a pull-up transistor, forming a second gate structure 112 separated on both sides of the first channel structure 102, the second gate structure 112 and the first channel structure 102 forming a pass gate transistor, and the second gate structure 112 and the first gate structure 110 being arranged in parallel along the first direction.
It should be noted that the first gate structure 110 is used to control the turn-on and turn-off of the conduction channels of the pull-down transistor and the pull-up transistor, and the second gate structure 112 is used to control the turn-on and turn-off of the conduction channels of the pass-gate transistor.
It should be further noted that, by providing the second gate structures 112 that are separated from the two sides of the first channel structure 102, a voltage signal can be separately applied to the second gate structures 112 on the two sides of the first channel structure 102, or a voltage signal can be simultaneously applied to the second gate structures 112 on the two sides of the first channel structure 102, so that the current of the pass gate transistor can be reduced or increased, that is, the read operating range and the write operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.
Specifically, the read operation range of the SRAM device is determined by the beta ratio (I pd/Ipg), the write operation range of the SRAM device is determined by the gamma ratio (I pg/Ipu), and the beta ratio and the gamma ratio of the SRAM device are made larger or smaller by controlling the current of the pass gate transistor to be increased or decreased, so that the read operation range and the write operation range of the SRAM device can be reduced or increased.
In this embodiment, the step of forming the first gate structure 110 and the second gate structure 112 includes forming a first dielectric layer (not shown) covering the first channel structure 102 and the second channel structure 103 on top of the substrate 101 of the sub-unit region 100B, forming a first opening (not shown) exposing portions of the tops and sidewalls of the first channel structure 102 and the second channel structure 103 in the first dielectric layer, forming a second opening (not shown) exposing portions of the tops and sidewalls of the first channel structure 102 in the first dielectric layer, the first opening and the second opening extending in the second direction and being arranged in parallel in the first direction, forming a gate material layer (not shown) in the first opening and the second opening, planarizing the gate material layer remaining in the second opening so that the tops of the gate material layers remaining in the second opening are flush with the tops of the first channel structure 102, using the gate material layer located in the first opening as the first gate structure 110, and using the remaining gate material layer located in the second opening as the second gate structure 112.
The first opening provides a spatial location for forming the first gate structure 110.
In this embodiment, the process of forming the first opening includes an anisotropic dry etching process.
Specifically, the anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate is greater than the transverse etching rate, and the pattern transfer precision is better, so that the shape quality of the side wall of the first opening can be improved, and meanwhile, in the anisotropic dry etching process, the etching selection ratio between the first dielectric layer and the first channel structure 102 can be utilized, so that the purpose of removing the first dielectric layer is achieved, and the probability of damaging the first channel structure 102 is reduced.
The second opening provides a spatial location for forming the first gate structure 110.
In this embodiment, the process of forming the second opening includes an anisotropic dry etching process.
As one example, the process of forming the gate material layer in the first and second openings includes an atomic layer deposition process or a chemical vapor deposition process.
It should be noted that, by performing the planarization treatment on the gate material layer located in the second opening, the top of the remaining gate material layer in the second opening is flush with the top of the first channel structure 102, so that the gate material layers are separated at two sides of the first channel structure 102, and the gate material layers separated at two sides of the first channel structure 102 are used as the second gate structures 112, so as to achieve the purpose of respectively applying a voltage signal to the second gate structures 112 at two sides of the first channel structure 102, or simultaneously applying a voltage signal to the second gate structures 112 at two sides of the first channel structure 102.
It should be further noted that the first gate structure 110 and the second gate structure 112 are formed in the same step, which reduces the process steps and reduces the process cost. In other embodiments, the first gate structure 110 and the second gate structure 112 may also be formed separately in different steps.
In this embodiment, the first gate structure 110 and the second gate structure 112 are both metal gate structures, the first gate structure 110 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, and the second gate structure 112 also includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer.
The gate dielectric layer is used to electrically isolate the gate electrode layer from the first channel structure 102 and to electrically isolate the gate electrode layer from the second channel structure 103.
The gate dielectric layer material includes one or more of HfO 2、ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、SiO2 and La 2O3.
In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO 2、ZrO2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO, al 2O3, or the like.
The gate dielectric layer may further include a gate oxide layer, where the gate oxide layer is located between the high-k gate dielectric layer and the first channel structure 102, and between the high-k gate dielectric layer and the second channel structure 103. Specifically, the material of the gate oxide layer may be silicon oxide.
In this embodiment, one or more of the materials TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC of the gate electrode layer.
Specifically, the gate electrode layer includes a work function layer (not shown), and an electrode layer (not shown) located on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electricity of the metal gate structure.
In other embodiments, the first gate structure 110 and the second gate structure 112 may also be polysilicon gate structures according to process requirements.
It should be noted that, as an example, the pass gate transistor and the pull-down transistor share the same first channel structure 102 to meet the operation requirement of the SRAM device.
As an example, the pull-down transistor and the pull-up transistor share a first gate structure 110 to meet the operating requirements of the SRAM device.
Referring to fig. 7, after forming the first gate structure 110 and the second gate structure 112, the forming method further includes forming a first source-drain doped layer 120 in the first channel structure 102 on both sides of the first gate structure 110 and on both sides of the second gate structure 112, forming a second source-drain doped layer 122 in the second channel structure 103 on both sides of the first gate structure 110, and electrically connecting the first source-drain doped layer 120 of the pull-down transistor with the second source-drain doped layer 122 of the pull-up transistor.
The first source-drain doped layer 120 is used as source and drain regions for pull-down transistors and as source and drain regions for pass-gate transistors.
The doping type of the first source drain doping layer 120 is the same as the channel conductivity type of the corresponding transistor.
Since the pass gate transistor and the pull-down transistor are both N-type transistors, the doping type of the first source drain doping layer 120 is N-type.
It should be noted that, as an example, in the step of forming the first channel structure 102, the first channel structure 102 has doping ions and has the same doping type as the first source-drain doping layer 120.
The first channel structure 102 has doped ions and has the same doping type as the first source/drain doped layer 120, so that the pass gate transistor and the pull-down transistor both use junction-free field effect transistors (Junctionless FieldEffect Transistor, JLT), which is beneficial to simplifying the formation process and steps of the SRAM device.
The second source-drain doped layer 122 serves as a source region and a drain region of the pull-up transistor.
The doping type of the second source drain doping layer 122 is the same as the channel conductivity type of the corresponding transistor.
Since the pull-up transistor is a P-type transistor, the doping type of the second source-drain doping layer 122 is P-type.
Note that, as an example, in the step of forming the second channel structure 103, the second channel structure 103 has doping ions and the same doping type as the second source-drain doping layer 122.
The second channel structure 103 has doped ions and has the same doping type as the second source/drain doped layer 122, so that the pull-up Transistor adopts a junction-free field effect Transistor (Junctionless FIELD EFFECT Transistor, JLT), which is beneficial to simplifying the formation process and steps of the SRAM device.
That is, after the first channel structure 102 and the second channel structure 103 having the doped ions are formed, the source-drain doping is not required, but the first channel structure 102 on both sides of the first gate structure 110 and on both sides of the second gate structure 112 is directly used as the first source-drain doped layer 120, and the second channel structure 103 on both sides of the first gate structure 110 is used as the second source-drain doped layer 122, so that the junction-free field effect transistor is formed, and the difficulty in forming the semiconductor structure is greatly reduced.
In this embodiment, the second source-drain doped layer 122 of the pull-up transistor is electrically connected to the first source-drain doped layer 120 of the pull-down transistor.
Specifically, in each of the sub-cell regions 100B, the drain region of the pull-up transistor is connected to the drain region of the pull-down transistor, and the pull-up transistor and the pull-down transistor share the first gate structure 110, so that in the adjacent two sub-cell regions 100B, the pull-up transistor and the pull-down transistor respectively constitute a first CMOS transistor and a second CMOS transistor, an input terminal of the first CMOS transistor is connected to an output terminal of the second CMOS transistor, and an output terminal of the first CMOS transistor is connected to an input terminal of the second CMOS transistor.
Referring to fig. 8, after forming the first source-drain doped layer 120 and the second source-drain doped layer 122, before subsequently forming the sharing plug, the gate plug, and the source-drain plug, a second dielectric layer (not shown) is further formed on top of the first dielectric layer, the first gate structure 110, and the second gate structure 112.
The second dielectric layer provides a process basis for the subsequent formation of the shared plug, the source drain plug and the gate plug.
In this embodiment, the material of the second dielectric layer is an insulating material. Specifically, the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.
With continued reference to fig. 8, after forming the first source-drain doped layer 120 and the second source-drain doped layer 122, the method of forming a semiconductor structure further includes forming a shared plug 128 on top of the first source-drain doped layer 120 between the first gate structure 110 and the second gate structure 112 and on top of the second source-drain doped layer 122 extending in the second direction also on the same side of the first gate structure 110, forming a source-drain plug 126 on top of the second source-drain doped layer 122 on the other side of the first gate structure 110 and on top of the remaining first source-drain doped layer 120, forming a gate plug 130 on top of the first gate structure 110, and electrically connecting the first gate structure 110 to the gate plug 130.
It should be noted that the sharing plug 128 electrically connects the first source-drain doped layer 120 between the first gate structure 110 and the second gate structure 112 and the second source-drain doped layer 122 extending along the second direction and also located on the same side of the first gate structure 110, so that in each sub-cell region 100B, the drain region of the pull-up transistor is electrically connected to the drain region of the pull-down transistor.
In this embodiment, the material of the shared plug 128 is tungsten. In other embodiments, the material of the shared plug may also be cobalt or ruthenium.
The source-drain plug 126 is used to electrically draw out the first source-drain doped layer 120 and the second source-drain doped layer 122, so that in each sub-unit region 100B, the source region of the pull-up transistor is connected to a power supply voltage, the source region of the pull-down transistor is connected to a power supply voltage, and the source region of the pass-gate transistor is connected to the bit line BL.
In this embodiment, in the step of forming the source-drain plug 126, the source-drain plug 126 formed on top of the second source-drain doped layer 122 on the other side of the first gate structure 110 is used to access VDD.
Specifically, VDD represents the operating positive voltage of the access.
In this embodiment, in the step of forming the source-drain plug 126, the source-drain plug 126 formed on top of the first source-drain doped layer 120 on the other side of the first gate structure 110 is used to access VSS.
Specifically, VSS represents the operating negative voltage that is switched in.
In this embodiment, the source/drain plug 126 is made of tungsten. In other embodiments, the material of the source-drain plug may be cobalt or ruthenium.
The gate plug 130 is used to electrically lead out the first gate structure 110, so as to control the conductive channels of the first channel structure 102 and the second channel structure 103.
In this embodiment, in the step of forming the gate plug 130, the gate plug 130 is further located on top of the shared plug 128 of the adjacent sub-unit region 100B, and the gate plug 130 is electrically connected to the shared plug 128 of the adjacent sub-unit region 100B.
In the adjacent two sub-cell regions 100B, the pull-up transistor and the pull-down transistor respectively constitute a first CMOS transistor and a second CMOS transistor, and the gate plug 130 is electrically connected to the shared plug 128 of the adjacent sub-cell region 100B, so that the input terminal of the first CMOS transistor is connected to the output terminal of the second CMOS transistor, and the output terminal of the first CMOS transistor is connected to the input terminal of the second CMOS transistor.
Referring to fig. 9, after forming the second gate structure 112 separately on both sides of the first channel structure 102, the method of forming a semiconductor structure further includes forming a first word line 161 on top of the second gate structure 112 on one side of the first channel structure 102 and electrically connecting the first word line 161 with the second gate structure 112, and forming a second word line 160 on top of the second gate structure 112 on the other side of the first channel structure 102 and electrically connecting the second word line 160 with the second gate structure 112.
Note that the first word line 161 and the second word line 160 are used to control the read operation and the write operation of the SRAM device.
It should be noted that, by providing the first word line 161 and the second word line 160 on both sides of the first channel structure 102, a voltage signal can be applied to the first word line 161 and the second word line 160, respectively, or a voltage signal can be applied to the first word line 161 and the second word line 160 at the same time, so that the current of the pass gate transistor can be reduced or increased, that is, the read operation range and the write operation range of the semiconductor structure can be reduced or increased, and thus the performance of the semiconductor structure can be improved.
In this embodiment, the materials of the first word line 161 and the second word line 160 each include one or more of TiN, cu, and W.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (13)
1. A semiconductor structure, comprising:
A substrate comprising a memory cell region comprising subcell regions extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction, the subcell regions comprising:
A first channel structure and a second channel structure located on the substrate and extending in the first direction and arranged in parallel in the second direction;
A first gate structure crossing the first and second channel structures, the first gate structure and the first channel structure forming a pull-down transistor, the first gate structure and the second channel structure forming a pull-up transistor;
and the second gate structure is separated from the two sides of the first channel structure, the second gate structure and the first channel structure form a transmission gate transistor, and the second gate structure and the first gate structure are arranged in parallel along the first direction.
2. The semiconductor structure of claim 1, further comprising a first source drain doped layer in a first channel structure on both sides of the first gate structure and on both sides of the second gate structure;
The second source-drain doped layer is positioned in the second channel structures at two sides of the first grid structure;
the first source-drain doped layer of the pull-down transistor is electrically connected with the second source-drain doped layer of the pull-up transistor.
3. The semiconductor structure of claim 2, further comprising a shared plug on top of the first source drain doped layer between the first gate structure and the second gate structure and extending in the second direction and on top of a second source drain doped layer on the same side of the first gate structure;
a source-drain plug positioned on the top of the second source-drain doping layer on the other side of the first gate structure and the top of the rest of the first source-drain doping layer;
And the gate plug is positioned on the top of the first gate structure and is electrically connected with the first gate structure.
4. The semiconductor structure of claim 3, wherein the gate plug is further positioned on top of a shared plug adjacent the subunit region, the gate plug being electrically connected to the shared plug adjacent the subunit region.
5. The semiconductor structure of claim 3, wherein a source-drain plug on top of the second source-drain doped layer on the other side of the first gate structure is for accessing VDD;
And a source-drain plug positioned on the top of the first source-drain doping layer on the other side of the first grid structure is used for accessing VSS.
6. The semiconductor structure of claim 1, further comprising a first word line on top of the second gate structure on one side of the first channel structure, the first word line being electrically connected to the second gate structure;
and the second word line is positioned on the top of the second grid structure at the other side of the first channel structure and is electrically connected with the second grid structure.
7. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a memory cell region comprising subcell regions extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction;
forming a first channel structure and a second channel structure extending in the first direction and arranged in parallel in the second direction on the substrate in the sub-unit region;
forming a first gate structure across the first and second channel structures, the first gate structure and the first channel structure forming a pull-down transistor, the first gate structure and the second channel structure forming a pull-up transistor;
And forming a second gate structure which is separated from two sides of the first channel structure, wherein the second gate structure and the first channel structure form a transmission gate transistor, and the second gate structure and the first gate structure are arranged in parallel along the first direction.
8. The method of forming a semiconductor structure of claim 7, wherein after forming the first gate structure and the second gate structure, the method further comprises forming a first source-drain doped layer in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure;
forming second source-drain doped layers in second channel structures at two sides of the first gate structure;
the first source-drain doped layer of the pull-down transistor is electrically connected with the second source-drain doped layer of the pull-up transistor.
9. The method of forming a semiconductor structure of claim 7, wherein forming the first and second gate structures comprises forming a first dielectric layer on top of a substrate of the subcell region covering the first and second channel structures;
forming first openings exposing portions of the tops and the side walls of the first channel structure and the second channel structure in the first dielectric layer, and forming second openings exposing portions of the tops and the side walls of the first channel structure in the first dielectric layer, wherein the first openings and the second openings extend along the second direction and are arranged in parallel along the first direction;
forming a gate material layer in the first opening and the second opening;
And flattening the gate material layer in the second opening to enable the top of the gate material layer remaining in the second opening to be flush with the top of the first channel structure, taking the gate material layer in the first opening as the first gate structure, and taking the gate material layer remaining in the second opening as the second gate structure.
10. The method of forming a semiconductor structure of claim 8, wherein after forming the first and second source-drain doped layers, the method further comprises forming a shared plug on top of the first source-drain doped layer between the first and second gate structures and on top of a second source-drain doped layer extending in the second direction and also on the same side of the first gate structure;
Forming a source-drain plug on the top of the second source-drain doping layer positioned on the other side of the first gate structure and on the top of the rest first source-drain doping layer;
a gate plug is formed on top of the first gate structure and the first gate structure is electrically connected to the gate plug.
11. The method of forming a semiconductor structure of claim 10, wherein in the step of forming the gate plug, the gate plug is further positioned on top of a shared plug adjacent to the subcell region, the gate plug being electrically connected to the shared plug adjacent to the subcell region.
12. The method of forming a semiconductor structure of claim 10, wherein in the step of forming a source-drain plug, a source-drain plug formed on top of a second source-drain doped layer on the other side of the first gate structure is used to access VDD;
And a source-drain plug formed on the top of the first source-drain doping layer on the other side of the first gate structure is used for accessing VSS.
13. The method of forming a semiconductor structure of claim 7, wherein after forming the second gate structure separately on both sides of the first channel structure, the method further comprises forming a first word line on top of the second gate structure on one side of the first channel structure, and the first word line is electrically connected to the second gate structure;
a second word line is formed on top of the second gate structure on the other side of the first channel structure, and the second word line is electrically connected with the second gate structure.
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