CN119451153A - Low temperature polysilicon thin film transistor and manufacturing method thereof, display panel, and display device - Google Patents
Low temperature polysilicon thin film transistor and manufacturing method thereof, display panel, and display device Download PDFInfo
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- CN119451153A CN119451153A CN202411527969.4A CN202411527969A CN119451153A CN 119451153 A CN119451153 A CN 119451153A CN 202411527969 A CN202411527969 A CN 202411527969A CN 119451153 A CN119451153 A CN 119451153A
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- 239000010409 thin film Substances 0.000 title claims abstract description 68
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 54
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 190
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000011149 active material Substances 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 230000004913 activation Effects 0.000 claims abstract description 16
- 230000007423 decrease Effects 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 26
- 208000032750 Device leakage Diseases 0.000 abstract 1
- 238000001994 activation Methods 0.000 description 22
- 230000000694 effects Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
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- 238000007715 excimer laser crystallization Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000002409 silicon-based active material Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- Thin Film Transistor (AREA)
Abstract
本发明涉及一种低温多晶硅薄膜晶体管及其制作方法、显示面板、显示装置。低温多晶硅薄膜晶体管的制作方法包括如下步骤：在缓冲层上依次形成有源材料层、第一栅极绝缘层、栅极金属层、第二栅极绝缘层以及层间介电层；形成过孔，过孔依次贯穿层间介电层、第二栅极绝缘层和第一栅极绝缘层，以露出有源材料层；以及对有源材料层与过孔对应的区域进行重掺杂，之后进行活化处理，活化处理之后掺杂浓度自重掺杂区向外围逐渐减小，以形成有源层。上述低温多晶硅薄膜晶体管的制作方法工艺简单，通过将源漏极重掺杂工艺及活化处理后移，能够在不增加Mask及工艺复杂性的前提下，形成薄膜晶体管的LDD结构，实现降低器件漏电的目的。
The present invention relates to a low-temperature polysilicon thin film transistor and a manufacturing method thereof, a display panel, and a display device. The manufacturing method of the low-temperature polysilicon thin film transistor comprises the following steps: forming an active material layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer, and an interlayer dielectric layer on a buffer layer in sequence; forming a via hole, the via hole sequentially penetrates the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer to expose the active material layer; and heavily doping the area corresponding to the active material layer and the via hole, and then performing an activation treatment, after which the doping concentration gradually decreases from the heavily doped area to the periphery to form an active layer. The manufacturing method of the low-temperature polysilicon thin film transistor has a simple process. By postponing the source and drain heavy doping process and the activation treatment, the LDD structure of the thin film transistor can be formed without increasing the complexity of the mask and the process, thereby achieving the purpose of reducing device leakage.
Description
Technical Field
The invention relates to the technical field of display, in particular to a low-temperature polycrystalline silicon thin film transistor, a manufacturing method thereof, a display panel and a display device.
Background
In the pixel circuit of the display technology, the low-temperature polysilicon TFT has high leakage, so that the technical direction of low leakage is considered to be that the LTPS circuit uses an LDD structure to reduce the leakage of the TFT or LTPO technology, namely a switching tube is manufactured by using an IGZO-TFT with lower leakage. However, LTPS LDD structures or LTPO technology increase masks, which increases not only cost but also process complexity and process accuracy requirements.
Disclosure of Invention
Based on this, it is necessary to provide a low-temperature polysilicon thin film transistor, a manufacturing method thereof, a display panel and a display device for solving the problem of reducing the leakage current of the device without increasing Mask and process complexity.
The manufacturing method of the low-temperature polysilicon thin film transistor comprises the following steps:
Sequentially forming an active material layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer on the buffer layer;
Forming a via hole penetrating the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer in order to expose the active material layer, and
And carrying out heavy doping on the region of the active material layer corresponding to the via hole, then carrying out activation treatment, and gradually reducing the doping concentration from the heavy doping region to the periphery after the activation treatment so as to form the active layer.
The manufacturing method of the low-temperature polysilicon thin film transistor is simple in process, and the LDD structure of the thin film transistor can be formed on the premise of not increasing Mask and process complexity by moving the source-drain heavy doping process and the activation process backwards, so that the purpose of reducing electric leakage of a device is achieved. Meanwhile, the method can also play a role in improving the channel edge effect of the thin film transistor and improve Hump problems.
In one possible implementation, the operation of heavily doping the region of the active material layer corresponding to the via hole is to perform ion implantation on the region of the active material layer corresponding to the via hole by using an ion beam, wherein the ion implantation dose is 5E14/cm 2～1E15/cm2.
In a possible implementation manner, the doping element for heavily doping the region of the active material layer corresponding to the via hole is at least one selected from boron element or phosphorus element.
In one possible implementation, the activation treatment is performed by heat treatment at 400-450 ℃ for 0.5-1 h.
In one possible implementation, the active layer further includes a transistor channel region near the lower doping concentration side.
In one possible implementation, the via includes a first via and a second via;
The activation treatment further comprises the following steps:
And forming a source electrode and a drain electrode on the interlayer dielectric layer, wherein the source electrode is connected with the active layer through the first via hole, and the drain electrode is connected with the active layer through the second via hole.
A low-temperature polysilicon thin film transistor comprises a buffer layer, an active layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer which are sequentially stacked;
the low-temperature polysilicon thin film transistor is provided with a via hole, and the via hole sequentially penetrates through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer;
The region of the active layer corresponding to the via hole is a heavily doped region, and the doping concentration in the active layer gradually decreases from the heavily doped region to the periphery.
According to the low-temperature polycrystalline silicon thin film transistor, the LDD structure of the thin film transistor can be formed on the premise of not increasing Mask and process complexity by moving the source-drain heavy doping process and the activation treatment backwards, and the purpose of reducing the electric leakage of a device is achieved. Meanwhile, the method can also play a role in improving the channel edge effect of the thin film transistor and improve Hump problems.
In one possible implementation, the via includes a first via and a second via;
the low-temperature polycrystalline silicon thin film transistor further comprises a source electrode and a drain electrode, wherein the source electrode is connected with the active layer through the first via hole, and the drain electrode is connected with the active layer through the second via hole.
A display panel comprises the low-temperature polycrystalline silicon thin film transistor manufactured by the manufacturing method of any one of the low-temperature polycrystalline silicon thin film transistors or the low-temperature polycrystalline silicon thin film transistor.
The display panel of the technical scheme of the invention comprises the low-temperature polysilicon thin film transistor, and the LDD structure of the thin film transistor can be formed on the premise of not increasing Mask and process complexity by moving the source-drain heavy doping process and the activation treatment backwards, so that the purpose of reducing the electric leakage of the device is realized. Meanwhile, the method can also play a role in improving the channel edge effect of the thin film transistor and improve Hump problems.
A display device comprises the display panel.
The display device of the technical scheme of the invention comprises the display panel, and the display panel comprises the low-temperature polysilicon thin film transistor, and the LDD structure of the thin film transistor can be formed on the premise of not increasing Mask and process complexity by moving the source-drain heavy doping process and the activation process backwards, so that the purpose of reducing the electric leakage of the device is realized. Meanwhile, the method can also play a role in improving the channel edge effect of the thin film transistor and improve Hump problems.
Drawings
FIG. 1 is a flow chart of a method for fabricating a LTPS TFT according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a method for fabricating a LTPS TFT according to an embodiment after forming an active material layer on a buffer layer;
Fig. 3 is a schematic diagram of a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment after forming a first gate insulating layer on an active material layer;
fig. 4 is a schematic diagram of a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment after forming a gate metal layer on a first gate insulating layer;
fig. 5 is a schematic diagram of a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment after forming a second gate insulating layer and an interlayer dielectric layer in sequence on a first gate insulating layer and a gate metal layer;
FIG. 6 is a schematic diagram of a low temperature polysilicon TFT according to an embodiment after forming a via hole;
fig. 7 is a schematic diagram of a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment after heavily doping an active material layer;
FIG. 8 is a schematic diagram of an activation process in a method for fabricating a LTPS TFT according to one embodiment;
FIG. 9 is a schematic cross-sectional view of a low temperature polysilicon thin film transistor after an activation process in a method of fabricating the same;
FIG. 10 is a schematic plan view of a low temperature polysilicon thin film transistor according to an embodiment after an activation process;
fig. 11 is a schematic diagram of a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment after forming a source and a drain on an interlayer dielectric layer.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the invention includes the following steps:
S10, sequentially forming an active material layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer on the buffer layer.
An active material layer (PSI) 120' is formed on the Buffer layer (Buffer) 110, as shown in fig. 2. The active material layer (PSI) 120 'may be formed on the Buffer layer (Buffer) 110 using conventional means in the art, for example, an amorphous silicon layer is deposited on the Buffer layer (Buffer) 110, and the amorphous silicon layer is converted into the polycrystalline silicon active material layer (PSI) 120' using a low temperature crystallization process, which may be Solid Phase Crystallization (SPC), excimer laser crystallization (ELA), rapid Thermal Annealing (RTA), or metal lateral induction (MILC), etc.
The Buffer layer (Buffer) 110 may be a silicon oxide (SiO x) layer, a silicon nitride (SiN x) layer, or a composite layer formed by stacking a silicon oxide layer and a silicon nitride layer. In addition, a Buffer layer (Buffer) 110 may be disposed on a substrate, which serves as a carrier, and may be a transparent substrate, such as a glass substrate, or the like.
A first gate insulating layer (GI) 130 is formed on the active material layer (PSI) 120', as shown in fig. 3. The first gate insulating layer (GI) 130 may be formed on the active material layer (PSI) 120' using conventional means in the art. The first gate insulating layer (GI) 130 may be a silicon oxide (SiO x) layer, a silicon nitride (SiN x) layer, or a composite layer formed by stacking a silicon oxide layer and a silicon nitride layer.
A gate metal layer (M1) 140 is formed on the first gate insulating layer (GI) 130, as shown in fig. 4. The gate metal layer (M1) 140 may be formed on the first gate insulating layer (GI) 130 by a conventional means in the art, for example, a whole metal layer is formed on the first gate insulating layer (GI) 130, and then the whole metal layer is etched to obtain the gate metal layer (M1) 140. Wherein the material of the whole metal layer can be, but not limited to, one or more of molybdenum (Mo), titanium (Ti), aluminum (Al) and copper (Cu).
A second gate insulating layer (CI) 150 and an interlayer dielectric layer (ILD) 160 are sequentially formed on the first gate insulating layer (GI) 130 and the gate metal layer (M1) 140, as shown in fig. 5. The second gate insulating layer (CI) 150 and the interlayer dielectric layer (ILD) 160 may be sequentially formed on the first gate insulating layer (GI) 130 and the gate metal layer (M1) 140 using conventional means in the art. The second gate insulating layer (CI) 150 may be a silicon oxide (SiO x) layer, a silicon nitride (SiN x) layer, or a composite layer formed by stacking a silicon oxide layer and a silicon nitride layer.
S20, forming a via hole, wherein the via hole penetrates through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer in sequence to expose the active material layer.
The via 170 may be formed using an etching process, and the via 170 sequentially penetrates through the interlayer dielectric layer (ILD) 160, the second gate insulating layer (CI) 150, and the first gate insulating layer (GI) 130, and exposes the active material layer (PSI) 120', and a region of the active material layer (PSI) 120' corresponding to the via 170 is the heavily doped region 121, as shown in fig. 6. Further, the via 170 includes a first via 171 and a second via 172, and each of the first via 171 and the second via 172 sequentially penetrates the interlayer dielectric layer (ILD) 160, the second gate insulating layer (CI) 150, and the first gate insulating layer (GI) 130.
The region of the active material layer (PSI) 120' corresponding to the via hole is the heavily doped region 121, and refers to the projection region of the bottom opening of the via hole 170 on the active layer (PSI) 120 is the heavily doped region 121. Further, the area of the heavily doped region 121 is determined by the projected area of the bottom opening of the via 170 on the active material layer (PSI) 120', that is, the area of the heavily doped region 121 is equal to the projected area of the bottom opening of the via 170 on the active material layer (PSI) 120'. The invention is not limited in the size of the via 170.
S30, heavily doping the region of the active material layer corresponding to the via hole, then carrying out activation treatment, and gradually reducing the doping concentration from the heavily doped region to the periphery after the activation treatment so as to form the active layer.
In one possible implementation, the operation of heavily doping the region of the active material layer (PSI) 120 'corresponding to the via 170 is to implant ions into the region of the active material layer (PSI) 120' corresponding to the via 170 using an ion beam at a dose of 5E14/cm 2～1E15/cm2, as shown in FIG. 7. Further, the dose of ion implantation may be, but is not limited to, 5E14/cm 2、6E14/cm2、7E14/cm2、8E14/cm2、9E14/cm2 or 1E15/cm 2.
In one possible implementation, the doping element heavily doping the region of the active material layer (PSI) 120' corresponding to the via 170 is selected from at least one of boron or phosphorus.
In one possible implementation, the activation treatment is performed by heat treatment at 400-450 ℃ for 0.5-1 h, as shown in fig. 8. Further, the temperature of the heat treatment may be, but is not limited to, 400 ℃, 405 ℃, 410 ℃, 415 ℃, 420 ℃, 425 ℃, 430 ℃, 435 ℃, 440 ℃, 445 ℃, or 450 ℃, and the time of the heat treatment may be, but is not limited to, 0.5h, 0.6h, 0.7h, 0.8h, 0.9h, or 1h. The activation process can repair the implantation damage and diffuse the implanted ions in the heavily doped region 121 at a high temperature, and form annular diffusion around the heavily doped region 121, and gradually decrease the doping concentration from the heavily doped region 121 to the periphery. Further, the dopant ions form a ring-shaped diffusion after the activation process to form a lightly doped region 122 having a relatively low concentration at the periphery of the heavily doped region 121, and an active material layer (PSI) 120' forms an active layer 120 after the activation process, as shown in fig. 9 and 10.
In one possible implementation, the active layer 120 further includes a transistor channel region 123, and the transistor channel region 123 is adjacent to the side with the lower doping concentration, i.e., is connected to the lightly doped region 122. The region where the transistor channel region 123 is located is a projection region of the gate metal layer (M1) 140 on the active layer (PSI) 120. That is, the periphery of the transistor channel region 123 is the lightly doped region 122. As shown in FIG. 10, the improvement of the channel edge effect shows that the source/drain doping is ring-shaped diffusion, the middle resistance is low, the resistance of the part near the two sides of the transistor channel region 123 is high, the current direction passes through the paths shown in the figures ① and ②, the length of the path ② is increased, the current is reduced, and the purpose of weakening the channel edge effect is achieved.
In one possible implementation, the activation process may further include a step of forming a source electrode 180 and a drain electrode 190 on the interlayer dielectric layer (ILD) 160, the source electrode 180 being connected to the active layer 120 through the first via 171, the drain electrode 190 being connected to the active layer 120 through the second via 172, as shown in fig. 11. The operation of forming the source electrode 180 and the drain electrode 190 on the interlayer dielectric layer (ILD) 160 is to form an entire metal layer on the interlayer dielectric layer (ILD) 160, and then etch the entire metal layer to obtain the source electrode 180 and the drain electrode 190. Wherein the material of the whole metal layer can be, but not limited to, one or more of molybdenum (Mo), titanium (Ti), aluminum (Al) and copper (Cu).
The manufacturing method of the low-temperature polysilicon thin film transistor is simple in process, and the LDD structure of the thin film transistor can be formed on the premise of not increasing Mask and process complexity by moving the source-drain heavy doping process and the activation process backwards, so that the purpose of reducing electric leakage of a device is achieved. Meanwhile, the method can also play a role in improving the channel edge effect of the thin film transistor and improve Hump problems.
Referring to fig. 11, a low temperature polysilicon thin film transistor 100 according to an embodiment is manufactured by any of the above methods.
Specifically, the low-temperature polysilicon thin film transistor 100 of an embodiment includes a Buffer layer (Buffer) 110, an active layer 120, a first gate insulating layer (GI) 130, a gate metal layer (M1) 140, a second gate insulating layer (CI) 150, and an interlayer dielectric layer (ILD) 160, which are sequentially stacked.
The low temperature polysilicon thin film transistor 100 has a via 170, and the via 170 penetrates through an interlayer dielectric (ILD) 160, a second gate insulating layer (CI) 150, and a first gate insulating layer (GI) 130 in order, and exposes the active layer 120.
The region of the active layer 120 corresponding to the via 170 is a heavily doped region 121, and the doping concentration in the active layer 120 gradually decreases from the heavily doped region 121 to the periphery. That is, the heavily doped region 121 is surrounded by the lightly doped region 122.
On the basis of the foregoing embodiment, the active layer 120 further includes a transistor channel region 123, and the transistor channel region 123 is adjacent to the side having a lower doping concentration, i.e., is connected to the lightly doped region 122.
In addition, the low temperature polysilicon thin film transistor 100 further includes a source 180 and a drain 190, and the source 180 and the drain 190 are respectively connected to the heavily doped region 121 via the via 170.
The low temperature polysilicon thin film transistor 100 further includes a source 180 and a drain 190, the source 180 is connected to the active layer 120 through the first via 171, and the drain 190 is connected to the active layer 120 through the second via 172.
According to the low-temperature polycrystalline silicon thin film transistor, the source and drain heavy doping process and the activation treatment are moved backwards, so that a LDD (Lightly Doped Drain) structure of the thin film transistor can be formed on the premise of not increasing Mask and process complexity, and the purpose of reducing electric leakage of a device is achieved. Meanwhile, the method can also play a role in improving the channel edge effect of the thin film transistor and improve Hump problems.
The display panel of an embodiment comprises the low-temperature polysilicon thin film transistor manufactured by the manufacturing method of any one of the low-temperature polysilicon thin film transistors or the low-temperature polysilicon thin film transistor.
The display panel of the technical scheme of the invention comprises the low-temperature polysilicon thin film transistor, and the LDD structure of the thin film transistor can be formed on the premise of not increasing Mask and process complexity by moving the source-drain heavy doping process and the activation treatment backwards, so that the purpose of reducing the electric leakage of the device is realized. Meanwhile, the method can also play a role in improving the channel edge effect of the thin film transistor and improve Hump problems.
An embodiment of the display device includes the display panel.
The display device of the technical scheme of the invention comprises the display panel, and the display panel comprises the low-temperature polysilicon thin film transistor, and the LDD structure of the thin film transistor can be formed on the premise of not increasing Mask and process complexity by moving the source-drain heavy doping process and the activation process backwards, so that the purpose of reducing the electric leakage of the device is realized. Meanwhile, the method can also play a role in improving the channel edge effect of the thin film transistor and improve Hump problems.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
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| CN202411527969.4A CN119451153A (en) | 2024-10-30 | 2024-10-30 | Low temperature polysilicon thin film transistor and manufacturing method thereof, display panel, and display device |
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| CN202411527969.4A CN119451153A (en) | 2024-10-30 | 2024-10-30 | Low temperature polysilicon thin film transistor and manufacturing method thereof, display panel, and display device |
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