CN119479731A - Memory and method of operating the same - Google Patents

Abstract

The presently disclosed embodiment discloses a memory and an operation method thereof, wherein the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines; the peripheral circuit is configured to: in response to a write command, apply a first voltage to a selected word line, apply a second voltage to a selected bit line, apply a ground voltage to an unselected word line, and apply a power supply voltage to an unselected bit line, so that a target memory cell coupled to the selected word line and the selected bit line is in a conductive state, and a non-target memory cell coupled to the unselected word line and/or the unselected bit line is in a non-conductive state.

Description

Memory and operation method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, for example, to a memory and a method of operating the same.

Background

Semiconductor memories can be roughly divided into two types, depending on whether they retain stored data when powered down, volatile memories that lose stored data when powered down, and nonvolatile memories that retain stored data when powered down.

The phase change memory is used as an emerging nonvolatile memory device, and has great superiority in a plurality of aspects such as read-write speed, read-write times, data holding time, unit area, multi-value implementation and the like compared with a flash memory.

Disclosure of Invention

According to a first aspect of embodiments of the present disclosure, there is provided a memory comprising a memory cell array and peripheral circuitry coupled to the memory cell array, the memory cell array comprising a plurality of bit lines, a plurality of word lines, a plurality of memory cells located between the plurality of bit lines and the plurality of word lines, the peripheral circuitry configured to apply a first voltage to a selected word line, a second voltage to an unselected word line, a ground voltage to an unselected bit line, and a supply voltage to an unselected bit line in response to a write command such that a target memory cell coupled to the selected word line and the selected bit line is in a conductive state and a non-target memory cell coupled to the unselected word line and/or the unselected bit line is in a non-conductive state.

In some alternative embodiments, a plurality of memory cells in the memory cell array are configured to have a set state and a reset state, the set state corresponding to a first threshold voltage distribution and the reset state corresponding to a second threshold voltage distribution, a minimum value of the second threshold voltage distribution being greater than a maximum value of the first threshold voltage distribution, and a difference between the first voltage and the second voltage being greater than the maximum value of the second threshold voltage distribution.

In some alternative embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than an absolute value of the second voltage.

In some alternative embodiments, the difference between the first voltage and the power supply voltage is a first value, the difference between the ground voltage and the second voltage is a second value, and both the first value and the second value are less than a minimum value of the first threshold voltage distribution.

In some alternative embodiments, the absolute value of the difference between the first value and the second value is less than or equal to 0.2V.

In some alternative embodiments, the absolute value of the difference between the first value and the second value is equal to 0.

In some alternative embodiments, the range of the first voltage is 4V-5V, the range of the second voltage is-4V-3V, and the range of the power supply voltage is 1.1V-1.2V.

In some alternative embodiments, the peripheral circuitry is configured to perform a set operation or a reset operation on the target memory cell based on the target memory cell being in a conductive state.

In some alternative embodiments, the memory cell comprises a phase change memory cell comprising a phase change element and a gating element in series with the phase change element.

According to a second aspect of embodiments of the present disclosure, there is provided a method of operating a memory, the method of operating including applying a first voltage to a selected word line, applying a second voltage to a selected bit line, applying a ground voltage to an unselected word line, applying a power supply voltage to an unselected bit line to place a target memory cell coupled to the selected word line and the selected bit line in a conductive state, and placing a non-target memory cell coupled to the unselected word line and/or the unselected bit line in a non-conductive state in response to a write command.

In the disclosed embodiments, a first voltage is applied to a selected word line, a second voltage is applied to a selected bit line so that a target memory cell is in a conductive state, a ground voltage is applied to an unselected word line, and a power supply voltage is applied to an unselected bit line so that a non-target memory cell coupled to the unselected word line and/or the unselected bit line is further in a non-conductive state. According to the scheme of the embodiment of the disclosure, in the first aspect, the double-rail power supply is adopted, and voltages are simultaneously applied to the selected word line and the selected bit line, so that the problems that a high-voltage resistant process is required to be used in a single-rail power supply scheme, the power consumption is high, and the threshold voltage drift of stored data of a non-target storage unit can be accelerated due to the high voltage are solved; the method comprises the steps of selecting a target memory cell, applying a first voltage and a second voltage to the selected word line and the selected bit line which are coupled with the target memory cell respectively, so that the problems that a high voltage resistant process is needed to be used and power consumption is high caused by applying a high voltage to the selected word line or the selected bit line only can be avoided, applying a grounding voltage to the unselected word line, applying a power voltage to the unselected bit line, and performing voltage compensation to the unselected word line and the unselected bit line, so that the non-target memory cell is in a non-conducting state, and further, the problem that data of the non-target memory cell is wrongly rewritten due to the fact that the non-target memory cell is wrongly opened is avoided.

Drawings

FIG. 1 is a schematic diagram of an exemplary system provided in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a memory device including a memory cell array and peripheral circuits according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of a memory cell according to an embodiment of the disclosure;

Fig. 4 is a schematic diagram of a second structure of a memory cell according to an embodiment of the disclosure;

FIG. 5 illustrates various pulse diagrams for performing set and reset operations on a phase change memory cell;

FIG. 6 is a schematic diagram of threshold voltage distribution of memory cells in a memory according to an embodiment of the disclosure;

FIG. 7 is a schematic diagram showing a relationship between threshold voltage distribution and applied voltage provided by an embodiment of the present disclosure;

FIG. 8 is a schematic diagram illustrating a voltage application condition of each memory cell according to an embodiment of the disclosure;

FIG. 9 is a second schematic diagram of the relationship between threshold voltage distribution and applied voltage provided by an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known functions and constructions are not described in detail to avoid obscuring the present disclosure, i.e., not all features of an actual embodiment are described herein.

In the drawings, like numbers refer to like elements throughout.

It should be understood that spatially relative terms, such as "under," "above," "over," and the like, may be used herein for convenience of description to describe one element or feature as illustrated in the figures as compared to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As shown in fig. 1, an exemplary system 10 is shown in an embodiment of the present disclosure, the exemplary system 10 may include a host 20 and a memory system 30. Exemplary System 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an augmented Reality (Augmented Reality, AR) device, or any other suitable electronic device having memory 34 therein, host 20 may be a processor of an electronic device (e.g., a central processing unit (Central Processing Unit, CPU) or a System on Chip (SoC) (e.g., an application processor (Application Process, AP)) memory System 30 includes a memory controller 32 and memory 34 coupled to memory controller 32.

Illustratively, the memory controller 32 may communicate with an external host through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) protocol, a PCI express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI-E) protocol, an advanced technology attachment (Advanced Technology Attachment, ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small interface (Small Computer SYSTEM INTERFACE, SCSI) protocol, an enhanced Small disk interface (ENHANCED SMALL DISK INTERFACE, ESDI) protocol, an integrated drive electronics (INTEGRATED DEVELOPMENT EQUIPMENT, IDE) protocol, a Firewire (Firewire) protocol, ONFI, DDR, LPDDR, and the like.

The memory includes a memory cell array, which may include a plurality of memory cells, and peripheral circuitry coupled to the memory cell array. The memory cell array may be integrated on the same die of the peripheral circuit, which allows for a wider bus and higher operating speed. In some embodiments, the memory cell array and the peripheral circuit may be formed in different regions on the same plane, or the memory cell array and the peripheral circuit may be formed in a stacked structure, i.e., they are formed on different planes.

Fig. 2 shows a schematic diagram of a memory including a memory cell array and peripheral circuits. As shown in fig. 2, the memory 304 includes a memory cell array 401 and a peripheral circuit 402 coupled to the memory cell array 401, and the memory cell array 401 may include a plurality of memory cells 4013 arranged in rows and columns, the plurality of memory cells 4013 arranged in rows are coupled to the same Word Line 4011, and the plurality of memory cells arranged in columns are coupled to the same Bit Line 4012.

In embodiments of the present disclosure, the Memory includes, but is not limited to, a variety of Memory types including phase change Memory (PHASE CHANGE Memory, PCM) and selector-only Memory (Selector Only Memory, SOM). It should be understood that the present disclosure is not limited thereto. In some embodiments, the memory cell is a phase change memory cell, as shown in FIG. 3, phase change memory cell 130 includes a gating element 110 and a phase change element 120 in series. In some embodiments, the memory cells are select only memory cells, and as shown in FIG. 4, select only memory cell 140 includes gating element 110.

The following description will take a memory as an example of a phase change memory. The basic storage principle of the phase change memory is to apply voltage or current pulse signals with different widths and heights to the phase change memory cell to change the physical phase state of the phase change material in the phase change element of the phase change memory cell, for example, reversible mutual conversion of the phase change material between a crystalline state (low-resistance state) and an amorphous state (high-resistance state) is realized, so that data storage is realized, and the memory cell has different threshold voltages when being in the crystalline state and the amorphous state, wherein the threshold voltage of the crystalline state (defined as 1) is lower, and the threshold voltage of the amorphous state (defined as 0) is higher. The operation that can perform the crystallization switching for the memory cell is defined as a set operation, and the operation that can perform the non-crystallization switching for the memory cell is defined as a reset operation.

In some embodiments, to achieve transition of phase change material in a phase change memory between crystalline and amorphous states, different pulses (e.g., optical pulses, electrical pulses) may be used to control phase change material heating. Fig. 5 shows a schematic diagram of pulses for performing a set operation and a reset operation on a phase change memory cell. As shown in fig. 5, the set operation includes the step of increasing the temperature of the phase change material of the phase change memory cell below the melting temperature Tm, above the crystallization temperature Tx, and maintaining for a period of time and promoting nucleation growth by applying a long and medium-intensity set pulse to effect transition of the phase change material of the phase change memory cell from an amorphous state (corresponding to a high resistance state) to a crystalline state (corresponding to a low resistance state). The reset operation includes the step of rapidly cooling the phase change material of the phase change memory cell after the temperature of the phase change material of the phase change memory cell is raised above the melting temperature Tm by applying a short and strong reset pulse. The set process and the reset process are mutually reversible processes, and thus, the phase change memory cell may represent a unit binary data "1" using a crystalline state and a binary data "0" using an amorphous state.

Fig. 6 is a schematic diagram of threshold voltage distribution of a memory cell in a memory according to an embodiment of the disclosure. As shown in fig. 6, a plurality of memory cells in the memory have a set state (crystalline state) and a reset state (amorphous state). The memory cells having a set state correspond to a first threshold voltage distribution, and the memory cells having a reset state correspond to a second threshold voltage distribution, a minimum voltage of the second threshold voltage distribution being greater than a maximum voltage of the first threshold voltage distribution.

In order to implement the write operation, i.e., to complete the set operation or the reset operation described above, as shown in fig. 7, a maximum voltage higher than a threshold voltage distribution (second threshold voltage distribution) corresponding to the memory cell in the reset state needs to be applied to both ends of the target memory cell to ensure that the target memory cell is in the on state. Here, the voltage Vwrite higher than the maximum voltage of the threshold voltage distribution corresponding to the memory cell in the reset state is generally higher.

In some embodiments, the higher Vwrite is applied by a single rail power supply to the selected word line or selected bit line to which the target memory cell is coupled. The non-target memory cells of the selected word lines or the selected bit lines in the memory cell array are also subjected to higher voltage, the higher voltage accelerates the threshold voltage drift of the stored data of the non-target memory cells, and finally errors can occur in the non-target memory cells when the data are read out.

The embodiment of the disclosure provides a memory, which comprises a memory cell array and peripheral circuits coupled with the memory cell array, wherein the memory cell array comprises a plurality of bit lines, a plurality of word lines and a plurality of memory cells positioned between the bit lines and the word lines, and the peripheral circuits are configured to respond to a write command, apply a first voltage to a selected word line, apply a second voltage to an unselected word line, apply a ground voltage to an unselected bit line and apply a power supply voltage to unselected bit lines so that target memory cells coupled with the selected word line and the selected bit line are in a conductive state and non-target memory cells coupled with the unselected word line and/or the unselected bit line are in a non-conductive state.

Fig. 8 is a schematic diagram of voltage application conditions of each memory cell according to an embodiment of the disclosure. As shown in fig. 8, a first Voltage (VH) is applied to a selected word line, a second Voltage (VN) is applied to a selected bit line, a ground Voltage (VSS) is applied to an unselected word line, and a power supply Voltage (VDD) is applied to an unselected bit line. The target memory cell is cell0.

In the disclosed embodiments, a first voltage is applied to a selected word line, a second voltage is applied to a selected bit line so that a target memory cell is in a conductive state, a ground voltage is applied to an unselected word line, and a power supply voltage is applied to an unselected bit line so that a non-target memory cell coupled to the unselected word line and/or the unselected bit line is further in a non-conductive state. According to the scheme of the embodiment of the disclosure, in the first aspect, the double-rail power supply is adopted, and voltages are simultaneously applied to the selected word line and the selected bit line, so that the problems that a high-voltage resistant process is required to be used in a single-rail power supply scheme, the power consumption is high, and the threshold voltage drift of stored data of a non-target storage unit can be accelerated due to the high voltage are solved; the method comprises the steps of selecting a target memory cell, applying a first voltage and a second voltage to the selected word line and the selected bit line which are coupled with the target memory cell respectively, so that the problems that a high voltage resistant process is needed to be used and power consumption is high caused by applying a high voltage to the selected word line or the selected bit line only can be avoided, applying a grounding voltage to the unselected word line, applying a power voltage to the unselected bit line, and performing voltage compensation to the unselected word line and the unselected bit line, so that the non-target memory cell is in a non-conducting state, and further, the problem that data of the non-target memory cell is wrongly rewritten due to the fact that the non-target memory cell is wrongly opened is avoided.

In some embodiments, a plurality of memory cells in the memory cell array are configured to have a set state and a reset state, the set state corresponding to a first threshold voltage distribution and the reset state corresponding to a second threshold voltage distribution, a minimum value of the second threshold voltage distribution being greater than a maximum value of the first threshold voltage distribution, and a difference between the first voltage and the second voltage being greater than the maximum value of the second threshold voltage distribution.

In the embodiment of the disclosure, a first voltage is applied to a selected word line, a second voltage is applied to a selected bit line, the first voltage is greater than 0, and the second voltage is less than 0, that is, a positive voltage is applied to the selected word line, and a negative voltage is applied to the selected bit line. The voltage across the target memory cell is the difference between the first voltage and the second voltage, which is greater than the maximum value of the second threshold voltage distribution, that is, the voltage across the target memory cell is greater than the maximum threshold voltage of the memory cell, so that the target memory cell can be ensured to be in a conductive state whether the target memory cell is in a set state or a reset state, or whether the threshold voltage of the target memory cell is higher or lower.

FIG. 9 is a schematic diagram of the relationship between threshold voltage distribution and applied voltage provided by embodiments of the present disclosure. As shown in FIG. 8 and FIG. 9, the non-target memory cells can be divided into 3 types according to the voltage across the non-target memory cell, namely, a first non-target memory cell1, the non-target memory cell1 is coupled to the selected word line and the unselected bit line, the voltage across the non-target memory cell1 is (VH-VDD), a second non-target memory cell2, the non-target memory cell2 is coupled to the unselected word line and the selected bit line, the voltage across the non-target memory cell2 is (VSS-VN), and a third non-target memory cell3, the non-target memory cell3 is coupled to the unselected word line and the unselected bit line, and the voltage across the non-target memory cell3 is (VSS-VDD). In addition, the voltage across the target cell0 is (VH-VN), (VH-VN) equal to Vwrite.

In some embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than an absolute value of the second voltage.

In the embodiment of the disclosure, the first voltage is greater than the absolute value of the second voltage, and an asymmetric pressurization mode of the selected word line and the selected bit line is adopted, so that the voltage (VSS-VN) at two ends of the non-target memory cell2 can be smaller than Vwrite/2. As shown in fig. 7, vwrite/2 is here greater than the minimum voltage of the first threshold voltage distribution and less than the maximum voltage of the first threshold voltage distribution.

In some embodiments, the difference between the first voltage and the power supply voltage is a first value, the difference between the ground voltage and the second voltage is a second value, and both the first value and the second value are less than a minimum value of the first threshold voltage distribution.

Here, the first value is (VH-VDD), and the second value is (VSS-VN), both of which are smaller than the minimum value of the first threshold voltage distribution, so that the non-target memory cell1 and the non-target memory cell2 are not turned on by mistake while the target memory cell0 is in the on state.

In the embodiment of the disclosure, the voltages at the two ends of the non-target memory cell3 are (VSS-VDD), which is smaller than the minimum value of the first threshold voltage distribution, and the non-target memory cell3 is not turned on by mistake while the target memory cell0 is in the on state.

In some embodiments, the absolute value of the difference between the first value and the second value is less than or equal to 0.2V.

In the embodiment of the disclosure, the absolute value of the difference between the first value and the second value is smaller, that is, the first value and the second value are closer, so that voltages at two ends of different non-target memory cells are more balanced, and the phenomenon of bias drift (english is expressed as bias drift) is improved greatly. Bias drift is understood herein to be the phenomenon of biasing a selected word line and a selected bit line such that the threshold voltage of non-target memory cells coupled to the selected word line or the selected bit line are shifted.

In some embodiments, the absolute value of the difference between the first value and the second value is equal to 0.

It will be appreciated that in the case where the absolute value of the difference between the first and second values is equal to 0, the first and second values are equal, which may result in a more balanced voltage across the different non-target memory cells, resulting in a maximum improvement in bias drift. In addition, in the case where the absolute value of the difference between the first value and the second value is equal to 0, the above-described embodiment can reduce the voltage across the non-target memory cell1 and the non-target memory cell2 by VDD/2 with respect to the dichotomy (selected word line applied Vwrite/2, selected bit line applied-Vwrite/2).

In some embodiments, the range of the first voltage is 4V-5V, the range of the second voltage is-4V-3V, and the range of the power supply voltage is 1.1V-1.2V.

It should be noted that, the ranges of the first voltage, the second voltage, and the power supply voltage given in the above embodiments are only examples, and are not used to limit the ranges of the first voltage, the second voltage, and the power supply voltage in the embodiments of the present disclosure, and in some specific examples, the first voltage, the second voltage, and the power supply voltage may be adjusted accordingly according to actual needs.

In some embodiments, the peripheral circuitry is configured to:

and executing a set operation or a reset operation on the target memory cell based on the target memory cell being in a conducting state.

In the embodiment of the disclosure, on the basis of making the target memory cell in a conductive state in response to a write command, a set operation or a reset operation is performed on the target memory cell, so that a write "0" or a write "1" is realized.

In some embodiments, the memory cell comprises a phase change memory cell comprising a phase change element and a gating element in series with the phase change element.

In some specific examples, the phase change element may include a chalcogenide composition, such as a binary compound of GaSb, inSb, inSe, sbTe and GeTe, a ternary compound of GeSbTe, gaSeTe, inSbTe, snSbTe and InSbGe, or at least one of a quaternary compound of AgInSbTe, (GeSn) SbTe, geSb (SeTe), and TeGeSbS. The gating element may comprise a material having an ovonic threshold switch (Ovonic Threshold Switch, OTS) property, which may include at least one element of oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as ZnxTey, gexTey, nbxOy, sixAsyTez, etc.

In the embodiment of the disclosure, the power supply voltage and the ground voltage applied to the unselected word lines and the unselected bit lines are all voltages commonly used in the memory, VDD and VSS which can be provided by the existing general logic circuit power supply are used for reducing the bearing of the non-target memory cells coupled with the selected word lines and/or the selected bit lines, so that the risk of being opened by mistake due to too small threshold voltages of the non-target memory cells coupled with the selected word lines and/or the selected bit lines is eliminated, bias drift is reduced, in addition, because greater power consumption is required for charging and discharging all the unselected bit lines, if the unselected bit lines are charged by using an internal additional voltage source, the required voltage source has greater carrying capacity, so that a larger chip area is required, and the interconnection lines for supplying power to the memory cell array also need greater current capacity, so that a wider power supply path is required, the area of the memory cell array can be further increased, the problems of the existing logic power supply VDD and VSS are effectively avoided, the logic power supply and VSS are the original voltages used in the chip, and the additional voltage source and the extra bit lines in the memory array can not be charged and discharged by using the extra power supply paths.

Based on the memory described above, the disclosed embodiments also provide a memory system comprising the memory of any of the above embodiments and a memory controller coupled to the memory, the memory controller configured to control the memory.

Based on the memory, the embodiment of the disclosure also provides an operation method of the memory, which comprises the steps of responding to a write command, applying a first voltage to a selected word line, applying a second voltage to a selected bit line, applying a grounding voltage to an unselected word line, and applying a power supply voltage to the unselected bit line so as to enable a target memory cell coupled with the selected word line and the selected bit line to be in a conducting state and enable a non-target memory cell coupled with the unselected word line and/or the unselected bit line to be in a non-conducting state.

In some embodiments, a plurality of memory cells in the memory cell array are configured to have a set state and a reset state, the set state corresponding to a first threshold voltage distribution and the reset state corresponding to a second threshold voltage distribution, a minimum value of the second threshold voltage distribution being greater than a maximum value of the first threshold voltage distribution, and a difference between the first voltage and the second voltage being greater than the maximum value of the second threshold voltage distribution.

In some embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than an absolute value of the second voltage.

In some embodiments, the difference between the first voltage and the power supply voltage is a first value, the difference between the ground voltage and the second voltage is a second value, and both the first value and the second value are less than a minimum value of the first threshold voltage distribution.

In some embodiments, the absolute value of the difference between the first value and the second value is less than or equal to 0.2V.

In some embodiments, the absolute value of the difference between the first value and the second value is equal to 0.

In some embodiments, the range of the first voltage is 4V-5V, the range of the second voltage is-4V-3V, and the range of the power supply voltage is 1.1V-1.2V.

In some embodiments, the method of operation further comprises performing a set operation or a reset operation on the target memory cell based on the target memory cell being in a conductive state.

In some embodiments, the memory cell comprises a phase change memory cell comprising a phase change element and a gating element in series with the phase change element.

Specific details regarding the operation method of the memory are described in detail on the memory side, and are not repeated here for brevity.

The features disclosed in the several device embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain a new device embodiment.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims (10)

1. A memory, characterized in that the memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuit is configured as follows: In response to a write command, a first voltage is applied to a selected word line, a second voltage is applied to a selected bit line, a ground voltage is applied to an unselected word line, and a power supply voltage is applied to an unselected bit line, so that the target memory cells coupled to the selected word line and the selected bit line are in a conductive state, and the non-target memory cells coupled to the unselected word line and/or the unselected bit line are in a non-conductive state. 2. The memory according to claim 1 is characterized in that the multiple memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution. 3 . The memory according to claim 2 , wherein the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than an absolute value of the second voltage. 4. The memory according to claim 2 is characterized in that the difference between the first voltage and the power supply voltage is a first value, the difference between the ground voltage and the second voltage is a second value, and the first value and the second value are both smaller than the minimum value of the first threshold voltage distribution. 5 . The memory according to claim 4 , wherein an absolute value of a difference between the first value and the second value is less than or equal to 0.2 V. 6 . The memory according to claim 5 , wherein an absolute value of a difference between the first value and the second value is equal to 0. 7 . 7 . The memory according to claim 1 , wherein the first voltage ranges from 4V to 5V, the second voltage ranges from −4V to −3V, and the power supply voltage ranges from 1.1V to 1.2V. 8. The memory according to claim 1, wherein the peripheral circuit is configured as follows: Based on the target memory cell being in the on state, a set operation or a reset operation is performed on the target memory cell. 9 . The memory according to claim 1 , wherein the memory cell comprises a phase change memory cell; the phase change memory cell comprises a phase change element and a gating element connected in series with the phase change element. 10. A method for operating a memory, characterized in that the method comprises: In response to a write command, a first voltage is applied to a selected word line, a second voltage is applied to a selected bit line, a ground voltage is applied to an unselected word line, and a power supply voltage is applied to an unselected bit line, so that the target memory cells coupled to the selected word line and the selected bit line are in a conductive state, and the non-target memory cells coupled to the unselected word line and/or the unselected bit line are in a non-conductive state.