CN119519704A

CN119519704A - Phase-locked loop detection circuit, phase-locked loop circuit and electronic equipment

Info

Publication number: CN119519704A
Application number: CN202411562465.6A
Authority: CN
Inventors: 张笑宇; 肖伊璠; 李季
Original assignee: Beijing Yisiwei System Technology Co ltd; Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Yisiwei System Technology Co ltd; Beijing Eswin Computing Technology Co Ltd
Priority date: 2024-11-04
Filing date: 2024-11-04
Publication date: 2025-02-25

Abstract

Provided are a detection circuit for a phase-locked loop, a phase-locked loop circuit, and an electronic device, which belong to the technical field of integrated circuits. The detection circuit includes a lock detection module and a clock detection module. Since the lock detection module can reliably detect whether the phase-locked loop is locked based on a lock indication signal, and output an unlock indication signal when the phase-locked loop is detected to be unlocked; the clock detection module can reliably detect whether a frequency deviation occurs in a clock signal generated by the phase-locked loop based on a reference clock signal and a clock signal to be measured, and output a frequency deviation indication signal when a frequency deviation occurs in the clock signal. Therefore, an external controller can adjust the operation of the phase-locked loop in a timely manner based on the unlock indication signal and the frequency deviation indication signal, so as to avoid the circuit based on the clock signal from being unable to work properly due to various factors such as the phase-locked loop being unable to lock or the clock signal generated by the phase-locked loop being frequency-deviation.

Description

Phase-locked loop detection circuit, phase-locked loop circuit and electronic equipment

Technical Field

The present application relates to the field of integrated circuits, and in particular, to a phase-locked loop detection circuit, a phase-locked loop circuit, and an electronic device.

Background

A phase-locked loop (PLL) is a circuit for generating a clock signal.

In the related art, a PLL generally includes a phase comparator (PD) for comparing an input signal and an output signal (also referred to as a feedback signal) to generate an error signal representing a phase difference, a Loop Filter (LF) for adjusting the frequency of the VCO to gradually approach the frequency of the input signal so as to minimize the phase difference, and a Voltage Controlled Oscillator (VCO) for maintaining the phase difference between the input signal and the output signal constant when the PLL is in a locked state, when the PLL is considered to generate a stable clock signal.

However, due to noise or other interference in the circuit, the PLL may not be locked (unlock), lose lock (lock lose), and jitter or frequency offset of the generated clock signal, which may cause the circuit operating based on the clock signal to not operate normally.

Disclosure of Invention

The embodiment of the application provides a detection circuit of a phase-locked loop, a phase-locked loop circuit and electronic equipment, which can solve the problem that a circuit working based on a clock signal cannot work normally due to the influence of the PLL (phase locked loop) cannot be locked, the PLL is unlocked, and generated clock signal jitter or frequency offset and the like in the related technology. The technical scheme is as follows:

in one aspect, a detection circuit of a phase-locked loop is provided, the detection circuit comprises a lock detection module and a clock detection module, wherein the lock detection module and the clock detection module are both connected with the phase-locked loop;

The lock detection module is used for receiving a lock indication signal output by the phase-locked loop, and outputting an unlock indication signal if the lock indication signal is detected to be not in accordance with a lock requirement after the phase-locked loop generates a clock signal;

The clock detection module is used for receiving a reference clock signal input to the phase-locked loop and a clock signal to be detected output by the phase-locked loop, counting according to the reference clock signal based on a first counting standard to obtain a first counting value, counting according to the clock signal to be detected based on a second counting standard to obtain a second counting value, and outputting a frequency deviation indication signal if detecting that the difference value between the first counting value and the second counting value is larger than a first difference value threshold.

The lock detection module comprises a first lock monitoring unit and an unlock interrupt generating unit which are mutually connected, and the unlock interrupt generating unit is also used for being connected with a controller and a register;

The first locking monitoring unit is used for receiving the locking indication signal, and outputting an unlocking abnormal signal to the unlocking interruption generating unit if the locking indication signal is detected to be not in accordance with the locking requirement after the phase-locked loop generates a clock signal;

The unlocking interrupt generating unit is used for generating the unlocking interrupt signal and the unlocking alarm signal based on the unlocking abnormal signal, outputting the unlocking interrupt signal to the controller and outputting the unlocking alarm signal to the register.

Optionally, the lock detection module further comprises an unlocking synchronization unit, wherein the unlocking synchronization unit is connected with the unlocking interrupt generation unit;

The unlocking synchronization unit is used for receiving an unlocking interrupt shielding signal and an unlocking interrupt clearing signal, synchronizing the unlocking interrupt shielding signal and the unlocking interrupt clearing signal, and outputting the synchronized unlocking interrupt shielding signal and unlocking interrupt clearing signal to the unlocking interrupt generation unit;

The unlocking interrupt generating unit is used for generating the unlocking interrupt signal and the unlocking alarm signal based on the unlocking abnormal signal, the synchronized unlocking interrupt shielding signal and the synchronized unlocking interrupt clearing signal.

Optionally, the locking detection module is further configured to output an out-of-lock indication signal if a jump edge of the locking indication signal is detected after the locking indication signal is detected to meet a locking requirement.

The lock detection module comprises a second lock monitoring unit and an out-of-lock interrupt generating unit which are connected with each other, wherein the out-of-lock interrupt generating unit is also used for being connected with a controller and a register;

the second locking monitoring unit is used for receiving the locking indication signal, and outputting an unlocking abnormal signal to the unlocking interruption generating unit when detecting the jump edge of the locking indication signal if the locking indication signal is detected to meet the locking requirement after the phase-locked loop generates a clock signal;

The out-of-lock interrupt generation unit is used for generating the out-of-lock interrupt signal and the out-of-lock alarm signal based on the out-of-lock abnormal signal, outputting the out-of-lock interrupt signal to the controller and outputting the out-of-lock alarm signal to the register.

Optionally, the lock detection module further comprises an out-of-lock synchronization unit, wherein the out-of-lock synchronization unit is connected with the out-of-lock interrupt generation unit;

The out-of-lock synchronization unit is used for receiving an out-of-lock interrupt shielding signal and an out-of-lock interrupt clearing signal, synchronizing the out-of-lock interrupt shielding signal and the out-of-lock interrupt clearing signal, and outputting the synchronized out-of-lock interrupt shielding signal and the synchronized out-of-lock interrupt clearing signal to the out-of-lock interrupt generating unit;

the out-of-lock interruption generating unit is used for generating the out-of-lock interruption signal and the out-of-lock alarm signal based on the out-of-lock abnormality signal, the synchronized out-of-lock interruption shielding signal and the out-of-lock interruption clearing signal.

Optionally, the second lock monitoring unit is shared with a first lock monitoring unit included in the lock detection module, and/or the out-of-lock synchronization unit is shared with an out-of-lock synchronization unit included in the lock detection module.

Optionally, the lock detection module is further configured to receive a phase-locked enable signal and the reference clock signal input to the phase-locked loop, count according to the reference clock signal in response to the phase-locked enable signal, and determine that the phase-locked loop generates a clock signal when the count reaches a phase-locked count reference, where the phase-locked count reference is related to a standard clock period of the phase-locked loop generating the clock signal.

Optionally, the clock detection module is further configured to obtain a third count value based on the third count reference according to the reference clock signal count, obtain a fourth count value based on the fourth count reference according to the clock signal count to be detected, and output a jitter indication signal if it is detected that a difference between the third count value and the fourth count value is greater than a second difference threshold.

Optionally, the clock detection module is further configured to receive a detection enabling signal, respond to the detection enabling signal, count according to the reference clock signal based on the first counting standard to obtain the first counting value, count according to the clock signal to be detected based on the second counting standard to obtain the second counting value, and/or respond to the detection enabling signal, count according to the reference clock signal based on the third counting standard to obtain the third counting value, and count according to the clock signal to be detected based on the fourth counting standard to obtain the fourth counting value.

Optionally, the clock detection module comprises a frequency detection module and a jitter detection module;

The frequency detection module is used for receiving the reference clock signal and the clock signal to be detected, counting according to the reference clock signal based on the first counting standard to obtain the first counting value, counting according to the clock signal to be detected based on the second counting standard to obtain the second counting value, and outputting the frequency deviation indication signal if detecting that the difference value between the first counting value and the second counting value is larger than the first difference value threshold;

The jitter detection module is used for receiving the reference clock signal and the clock signal to be detected, counting according to the reference clock signal based on the third counting standard to obtain a third counting value, counting according to the clock signal to be detected based on the fourth counting standard to obtain a fourth counting value, and outputting the jitter indication signal if detecting that the difference value between the third counting value and the fourth counting value is larger than the second difference value threshold.

The frequency detection module comprises a frequency monitoring unit and a frequency abnormal interrupt generating unit which are connected with each other, wherein the frequency abnormal interrupt generating unit is also used for being connected with a controller and a register;

The frequency monitoring unit is used for receiving the reference clock signal and the clock signal to be detected, counting according to the reference clock signal based on the first counting standard to obtain the first counting value, counting according to the clock signal to be detected based on the second counting standard to obtain the second counting value, and outputting a frequency abnormal signal to the frequency abnormal interrupt generating unit if detecting that the difference value between the first counting value and the second counting value is larger than the first difference value threshold;

the frequency abnormal interrupt generating unit is used for generating the frequency abnormal interrupt signal and the frequency abnormal alarm signal based on the frequency abnormal signal, outputting the frequency abnormal interrupt signal to the controller and outputting the frequency abnormal alarm signal to the register.

Optionally, the frequency detection module further comprises a frequency abnormality synchronization unit, wherein the frequency abnormality synchronization unit is connected with the frequency abnormality interrupt generation unit;

The frequency abnormal synchronization unit is used for receiving a frequency abnormal interrupt shielding signal and a frequency abnormal interrupt clearing signal, synchronizing the frequency abnormal interrupt shielding signal and the frequency abnormal interrupt clearing signal, and outputting the synchronized frequency abnormal interrupt shielding signal and frequency abnormal interrupt clearing signal to the frequency abnormal interrupt generating unit;

The frequency abnormal interrupt generating unit is used for generating the frequency abnormal interrupt signal and the frequency abnormal alarm signal based on the synchronized frequency abnormal signal, the synchronized frequency abnormal interrupt shielding signal and the synchronized frequency abnormal interrupt clearing signal.

Optionally, the frequency monitoring unit is further used for determining frequency deviation information and outputting the frequency deviation information to the register;

The frequency monitoring unit is further used for determining frequency deviation information and outputting the frequency deviation information to the frequency abnormal interruption generating unit, and the frequency abnormal interruption generating unit is used for generating the frequency abnormal interruption signal and the frequency abnormal alarm signal based on the synchronized frequency abnormal signal and the frequency deviation information.

The jitter detection module comprises a jitter monitoring unit and a jitter abnormal interrupt generating unit which are connected with each other, wherein the jitter abnormal interrupt generating unit is also used for being connected with a controller and a register;

the jitter monitoring unit is used for receiving the reference clock signal and the clock signal to be detected, counting according to the reference clock signal based on the third counting standard to obtain a third counting value, counting according to the clock signal to be detected based on the fourth counting standard to obtain a fourth counting value, and outputting a jitter abnormal signal to the jitter abnormal interrupt generating unit if detecting that the difference value between the third counting value and the fourth counting value is larger than the second difference value threshold;

the jitter abnormal interrupt generating unit is used for generating the jitter abnormal interrupt signal and the jitter abnormal alarm signal based on the jitter abnormal signal, outputting the jitter abnormal interrupt signal to the controller and outputting the jitter abnormal alarm signal to the register.

Optionally, the jitter detection module further comprises a jitter abnormal synchronization unit, wherein the jitter abnormal synchronization unit is connected with the jitter abnormal interrupt generation unit;

The jitter abnormal synchronization unit is used for receiving a jitter abnormal interrupt shielding signal and a jitter abnormal interrupt clearing signal, synchronizing the jitter abnormal interrupt shielding signal and the jitter abnormal interrupt clearing signal, and outputting the synchronized jitter abnormal interrupt shielding signal and the synchronized jitter abnormal interrupt clearing signal to the jitter abnormal interrupt generating unit;

the jitter abnormal interrupt generating unit is used for generating the jitter abnormal interrupt signal and the jitter abnormal alarm signal based on the synchronized jitter abnormal signal, the synchronized jitter abnormal interrupt shielding signal and the synchronized jitter abnormal interrupt clearing signal.

In another aspect, a phase-locked loop circuit is provided, the phase-locked loop circuit comprising a phase-locked loop, and a detection circuit as described in the above aspect;

the detection circuit is connected with the phase-locked loop and is used for detecting the work of the phase-locked loop.

In yet another aspect, an electronic device is provided that includes a controller, a register, and a phase-locked loop circuit as described in another aspect above;

The detection circuit in the phase-locked loop circuit is respectively connected with the controller and the register and is used for outputting the detection result aiming at the phase-locked loop to the controller and the register.

In summary, the technical solution provided by the embodiment of the present application at least includes the following beneficial effects:

a phase-locked loop detection circuit, a phase-locked loop circuit and an electronic device are provided. The detection circuit comprises a lock detection module and a clock detection module. The clock detection module can reliably detect whether the clock signal generated by the phase-locked loop generates frequency offset or not based on the reference clock signal and the clock signal to be detected, and output the frequency offset indication signal when the clock signal generates the frequency offset. Therefore, the external controller can timely adjust the work of the phase-locked loop based on the unlocking indication signal and the frequency deviation indication signal, and the phenomenon that a circuit based on the clock signal works can not work normally due to the influence of various factors such as the fact that the phase-locked loop cannot be locked or the clock signal generated by the phase-locked loop is subjected to frequency deviation is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a phase-locked loop according to an embodiment of the present application;

Fig. 2 is a schematic structural diagram of a detection circuit of a phase-locked loop according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a detection circuit of another phase-locked loop according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a detection circuit of a phase-locked loop according to an embodiment of the present application;

Fig. 5 is a schematic structural diagram of a detection circuit of a phase-locked loop according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a detection circuit of a phase-locked loop according to an embodiment of the present application;

fig. 7 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present application;

Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

The clock signal is an important component in the design of the digital chip, is the basis of sequential logic, and is a signal with a fixed period and an operation rule independent of the circuit function. The operating speed of the hardware can be regulated by controlling the period and frequency of the clock signal. In a circuit (e.g., a digital circuit), a PLL as shown in fig. 1 is typically used to generate a desired clock signal to trigger a register in the circuit to operate or to change the operating state of the circuit. Referring to fig. 1, it can be seen that the PLL may be connected to a voltage input Vin, which may provide an input voltage to analog circuitry within the PLL to control the operation of the analog circuitry. As can be seen with reference to fig. 2 again on the basis of fig. 1, a PLL may generally comprise a PD, an LF and a VCO connected in series and forming a loop. And, the PLL may also receive a reference clock signal rf_clk, a phase-lock enable signal pll_en, and a reset signal rst. Wherein the PLL can be reset or initialized based on the reset signal rst. The PLL can start operating under the control of the phase lock enable signal pll_en. And, after the PLL starts to operate, the PD therein can compare the received reference clock signal rf_clk with the feedback signal fed back through the VCO and generate an error signal Vpd representing the phase difference. The LF is able to adjust the frequency of the VCO based on the error signal Vpd to generate a control voltage Vcont such that a constant phase difference is maintained between the feedback signal output by the VCO and the input signal (i.e., the reference clock signal rf_clk), i.e., such that the output signal h_clk of the PLL remains synchronized with the input signal rf_clk. At this time, the PLL can be considered to be in a locked state. Conversely, if the output signal and the input signal cannot be kept synchronized, the PLL may be considered unlocked or out of lock. The PLL not locked may mean that the PLL is not successfully locked, and the PLL losing lock may mean that the PLL loses lock again after being successfully locked. Furthermore, as can be seen in connection with fig. 1 and 2, the PLL is also capable of outputting a lock indication signal locked to indicate the locked state of the PLL.

As described above, noise interference may cause the PLL to be unlocked or out of lock, and may also cause abnormal jitter or abnormal frequency shift (also referred to as frequency shift) of a clock signal generated by the PLL, where the larger the noise, the larger the frequency shift, and the more frequent the clock signal is. That is, the PLL generates a clock signal that is unstable. Since the clock signal generally determines the operating speed of the circuit operating based on the clock signal, the instability is likely to cause the circuit to fail to operate normally, resulting in an increase in the data transmission error rate or a decrease in the signal integrity of the circuit. In particular, some circuits (e.g., microprocessors, digital signal processors, or wireless communication devices) that require a high quality clock signal, i.e., PLL generation clock signal instability is generally not permitted. Based on this, it is needed to provide a detection circuit for continuously monitoring the clock signal generated by the PLL, and timely detecting the abnormal problems such as unlocked, jittered or frequency offset, so as to avoid the circuit working based on the clock signal generated by the PLL from failing to work normally.

In some embodiments, the primary emphasis is on frequency detection of the clock signal. For example, a frequency counter or an oscilloscope is used to detect the frequency of the clock signal generated by the PLL, or the output signal of the PLL is compared with a reference signal and the counter and the oscilloscope are combined to detect the frequency of the clock signal generated by the PLL. However, this is not only dependent on the design of the PLL, but it is also impossible to perform a complete and comprehensive test on the clock signal generated by the PLL, such as whether the PLL is unlocked, whether the clock signal generated by the PLL is jittery, etc. In addition, in this embodiment, the detection results are often stored in registers for the controller to invoke by polling or other mechanisms, and the operation of the PLL is adjusted based on the detection results to enable the PLL to generate a stable clock signal. However, the calling mode cannot ensure timely and accurate feedback of the detection result, and further cannot timely and reliably control the PLL to generate a stable clock signal. The controller may be, for example, a central processing unit (central processing unit, CPU).

Based on the above, the embodiment of the application provides a detection circuit to realize timely and accurate detection of a clock signal generated by a PLL, so that the PLL can timely and reliably generate a stable clock signal, and a circuit working based on the clock signal can work normally. Fig. 2 is a schematic structural diagram of a detection circuit of a phase-locked loop according to an embodiment of the present application. As shown in fig. 2, the detection circuit 00 includes a lock detection module 01 and a clock detection module 02. The lock detection module 01 and the clock detection module 02 are both connected to a phase locked loop PLL.

The lock detection module 01 is configured to receive a lock indication signal locked output by the phase-locked loop PLL, and output an unlock indication signal if the lock indication signal locked is detected to be not in compliance with a lock requirement after the phase-locked loop PLL generates a clock signal. That is, the lock detection module 01 may be used to detect whether the phase locked loop PLL is locked.

As can be seen in connection with fig. 1, the phase locked loop PLL may output a lock indication signal locked to indicate the locked state of the phase locked loop PLL, which may also be referred to as a lock state indication signal, accordingly. The lock detection module 01 may be connected to the PLL to receive the lock indication signal locked, and determine whether the PLL is locked by detecting whether the lock indication signal locked meets a locking requirement after the PLL generates a clock signal. For example, the lock indication signal locked to be output to the lock detection module 01 is also identified as pll_lock in fig. 2.

Alternatively, the PLL normally generates a clock signal for N standard clock cycles, where N is an integer greater than 1, for example, N may be 3. Accordingly, the lock detection module 01 may start to detect whether the lock indication signal locked (i.e. pll_lock) output by the PLL meets the lock requirement after at least 3 standard clock cycles.

Furthermore, as is clear from the foregoing description, meeting the locking requirement may mean that the output signal and the input signal of the phase-locked loop PLL remain synchronized for a certain period of time, and the phase-locked loop PLL can generate a stable clock signal. Conversely, a failure to meet the locking requirement may mean that the output signal and the input signal of the PLL cannot be stably synchronized within a certain period of time. In general, if the PLL is successfully locked, the level of the locked indication signal locked outputted by the PLL is high (e.g., logic 1), that is, the level of the locked indication signal locked reflecting that the PLL is in the locked state is high. If the PLL is unlocked, the level of the lock indication signal locked outputted by the PLL is low (e.g., logic 0), that is, the level of the lock indication signal locked reflecting that the PLL is in an unlocked state is low. Accordingly, the lock detection module 01 can reliably and quickly determine whether the PLL is locked by detecting the level of the lock indication signal locked.

For example, after the PLL works for N standard clock cycles, if the level of the lock indication signal locked is detected to be low level 0, the lock detection module 01 may determine that the lock indication signal locked does not meet the lock requirement, i.e. may determine that the PLL is not locked. At this time, the lock detection module 01 may output an unlock indication signal to indicate that the phase locked loop PLL is not locked. Of course, if the level of the lock indication signal locked is detected to be high level 1, it may be determined that the lock indication signal locked meets the lock requirement, that is, it may be determined that the PLL has been successfully locked. At this time, the lock detection module 01 may not output the unlock instruction signal, or may output the lock instruction signal to instruct the phase locked loop PLL to lock reliably. Alternatively, the lock indication signal and the unlock indication signal may be two signals having different levels, for example, the level of the unlock indication signal may be a high level 1 and the level of the lock indication signal may be a low level 0.

Optionally, the lock detection module 01 may be connected to a controller (e.g. a CPU), and may output an unlock indication signal to the controller, so as to instruct the controller to adjust parameters in the PLL in time or control the PLL to stop working when the PLL cannot lock, so as to avoid that a circuit working based on a clock signal generated by the PLL cannot work normally.

The clock detection module 02 is configured to receive a reference clock signal rf_clk input to the phase-locked loop PLL and a clock signal h_clk to be detected output by the phase-locked loop PLL, count the reference clock signal rf_clk based on a first count reference to obtain a first count value, count the reference clock signal h_clk based on a second count reference to obtain a second count value, and output a frequency offset indication signal if detecting that a difference between the first count value and the second count value is greater than a first difference threshold. That is, the clock detection module 02 may be configured to detect whether an abnormal shift occurs in the frequency of the clock signal generated by the phase-locked loop PLL, that is, whether a frequency shift occurs.

As can also be seen in connection with fig. 1, the phase-locked loop PLL may also receive a reference clock signal rf_clk to ensure that the internal oscillating signal and the external reference signal maintain phase and frequency consistency based on the reference clock signal rf_clk, thereby outputting a stable clock signal, herein referred to as clock signal under test h_clk. The clock detection module 02 may be connected to a phase locked loop PLL to receive the reference clock signal rf_clk and the clock signal under test h_clk. Then, the clock detection module 02 may count according to the reference clock signal rf_clk and the clock signal h_clk to be detected to obtain a first count value and a second count value, and determine whether the clock signal generated by the phase-locked loop PLL generates a frequency offset based on the magnitude relation between the first count value and the second count value.

It will be appreciated that the first count value and the second count value should be close when the frequency of the clock signal h_clk to be measured is not shifted or is shifted less, and that the first count value and the second count value are different more when the frequency of the clock signal h_clk to be measured is shifted abnormally more. Accordingly, the clock detection module 02 may determine whether the frequency of the clock signal generated by the phase-locked loop PLL is abnormally shifted (i.e., whether a frequency offset, such as an over-frequency, occurs) by detecting whether the difference between the first count value and the second count value is large.

If the difference between the first count value and the second count value is larger, the clock detection module 02 can determine that the clock signal h_clk to be detected is subjected to frequency offset. At this time, the clock detection module 02 may output a frequency offset indication signal to indicate that the frequency of the clock signal generated by the phase locked loop PLL is abnormally shifted. Of course, if the difference between the first count value and the second count value is smaller or is 0, the clock detection module 02 may determine that the frequency of the clock signal h_clk to be detected is normal. At this time, the clock detection module 02 may not output the frequency offset indication signal, or may output the frequency normal indication signal to indicate that the frequency of the clock signal generated by the phase-locked loop PLL is not abnormally offset. Alternatively, the frequency offset indication signal and the frequency normal indication signal may be two signals with different levels, for example, the level of the frequency offset indication signal is a high level 1, and the level of the frequency normal indication signal is a low level 0. It is understood that the frequency anomaly offset may refer to a larger frequency offset, where the offset may refer to a deviation from an ideal value.

Alternatively, the first difference threshold may be preset to measure whether the first count value and the second count value differ greatly, and the absolute value of the difference between the first count value and the second count value detected by the clock detection module 02 may be greater than the first difference threshold. And, the first count reference and the second count reference may be set in advance so that the clock detection module 02 performs counting based on the first count reference, that is, counts to the first count reference to stop counting when counting according to the reference clock signal rf_clk. Correspondingly, the first counting standard can also be called as the counting standard of the reference clock, and when counting according to the clock signal h_clk to be measured, counting is performed based on the second counting standard, namely, counting is stopped until the second counting standard is counted. Accordingly, the second count reference may also be referred to as a count reference of the clock under test. Also, the first count reference and the second count reference may be flexibly designed according to the specifications of the phase-locked loop PLL, e.g., the first count reference and the second count reference may be identical to ensure counting at the same time period according to different clock signals. In addition, the first count reference, the second count reference, the first difference threshold and the like can be stored in the clock detection module 02 in advance by configuring register parameters for the clock detection module 02 to call, and belong to parameter configuration signals.

Optionally, with the lock detection module 01, the clock detection module 02 may also be connected to the controller, and output a frequency offset indication signal to the controller, so as to instruct the controller to adjust parameters in the PLL in time or control the PLL to stop working when the frequency of the clock signal generated by the PLL is abnormally offset, so as to avoid that a circuit working based on the clock signal generated by the PLL cannot work normally.

Based on the above description, the detection circuit 00 provided by the embodiment of the application not only can detect whether the PLL is locked, but also can detect whether the clock signal generated by the PLL is in frequency offset, and the detection is relatively comprehensive. On the basis, the detection result is timely informed to the controller, so that the controller can conveniently and timely adjust the work of the phase-locked loop PLL, and the phenomenon that a circuit based on the clock signal output by the phase-locked loop PLL cannot work normally is avoided. That is, it is possible to ensure that a circuit operating based on a clock signal generated by the phase-locked loop PLL can always be in a normal operating state without being affected by an abnormal operation of the phase-locked loop PLL.

In summary, the embodiment of the application provides a detection circuit of a phase-locked loop. The detection circuit comprises a lock detection module and a clock detection module. The clock detection module can reliably detect whether the clock signal generated by the phase-locked loop generates frequency offset or not based on the reference clock signal and the clock signal to be detected, and output the frequency offset indication signal when the clock signal generates the frequency offset. Therefore, the external controller can timely adjust the work of the phase-locked loop based on the unlocking indication signal and the frequency deviation indication signal, and the phenomenon that a circuit based on the clock signal works can not work normally due to the influence of various factors such as the fact that the phase-locked loop cannot be locked or the clock signal generated by the phase-locked loop is subjected to frequency deviation is avoided.

Optionally, as can also be seen with continued reference to FIG. 2, the unlock indication signal may include an unlock interrupt signal and an unlock alert signal. Accordingly, as shown in FIG. 3, the lock detection module 01 may include a first lock monitor unit 011 and an unlocked interrupt generating unit 012 that are connected to each other, and the unlocked interrupt generating unit 012 may also be used in connection with a controller and a register. The controller and registers belonging to external devices independent of the detection circuit 00 are not shown in fig. 3.

The first lock monitor unit 011 may be configured to receive the lock indication signal lock (i.e. pll_lock), and after generating a clock signal by the PLL, if it is detected that the lock indication signal lock does not meet the lock requirement, output an unlock exception signal to the unlock interrupt generating unit 012. That is, whether the lock instruction signal locked meets the lock requirement may be detected by the first lock monitor unit 011.

Alternatively, in conjunction with fig. 3, when the first lock monitor unit 011 detects that the lock indication signal lock does not meet the lock requirement, the level of the signal pl_unlock output to the unlocked interrupt generation unit 012 may be pulled up from the initial low level to the high level, that is, the signal pl_unlock of the high level is output to the unlocked interrupt generation unit 012 to indicate that the lock indication signal lock does not meet the lock requirement, that is, to indicate that the phase-locked loop PLL is not locked. In other words, the unlock abnormality signal output by the first lock monitor unit 011 to the unlock interrupt generation unit 012 may refer to a signal pl_unlock of high level. Of course, the level pulling process is not limited, and the level pulling process may be from the initial high level to the low level, which is not limited in the embodiment of the present application.

The unlocked interrupt generation unit 012 may be configured to generate an unlocked interrupt signal and an unlocked alert signal based on the unlocked exception signal (i.e., the high level signal pll_unlock), and output the unlocked interrupt signal to the controller and the unlocked alert signal to the register. That is, an unlock instruction signal may be generated and output by the unlock interrupt generation unit 012 based on the unlock abnormality signal output by the first lock monitor unit 011.

Optionally, the unlocked interrupt generating unit 012 may output the generated unlocked interrupt signal and the unlocked alarm signal to the controller and the register through different output channels, so that the controller may adjust the operation of the PLL based on the unlocked interrupt signal in time, so as to avoid that the PLL is abnormal, and thus the circuit that operates based on the clock signal generated by the PLL cannot operate normally, and may also cause the controller to invoke the unlocked alarm signal from the register through polling or other mechanisms to determine whether the PLL operates normally. The detection can be made more timely and accurate than the mode that the above embodiment can only poll the call from the register.

Alternatively, the unlocked interrupt signal/unlocked alarm signal generated by the unlocked interrupt generating unit 012 may be a pulse signal, and the high-level pulse width of the pulse signal may be equal to the high-level pulse width of one reference clock signal rf_clk. In some embodiments, an external signal processing circuit may also be provided between the lock detection module 01 and the controller to convert the pulses to a level to adapt the controller for processing by the controller. The external signal processing circuit generally works in a configuration clock domain, and the clock signal and the reference clock signal rf_clk adopted in the configuration clock domain are in asynchronous relation. Thus, the clock signal used by the external signal processing circuit and the reference clock signal rf_clk received by the PLL are also asynchronously processed to ensure that the external signal processing circuit correctly samples the signal (e.g., the alarm signal).

Optionally, as can also be seen with continued reference to FIG. 3, the lock detection module 01 may further include an unlocked synchronization unit 013. The unlock synchronization unit 013 may be connected with the unlock interrupt generation unit 012.

The unlocked synchronization unit 013 may be configured to receive the unlocked interrupt mask signal unlock inr mask and the unlocked interrupt clear signal unlock inr clr, synchronize the unlocked interrupt mask signal unlock inr mask and the unlocked interrupt clear signal unlock inr clr, and output the synchronized unlocked interrupt mask signal unlock inr mask and unlocked interrupt clear signal unlock inr clr to the unlocked interrupt generation unit 012.

Alternatively, the unlocked interrupt mask signal and the unlocked interrupt clear signal may come from external circuitry, also referred to as the outside world, that is independent of the detection circuitry. That is, the unlocked synchronization unit 013 can synchronize the unlocked interrupt mask signal unlock inr mask and the unlocked interrupt clear signal unlock inr clr received from the outside.

The synchronization may refer to synchronizing the unlocked interrupt mask signal unlock inr mask and the unlocked interrupt clear signal unlock inr clr under the same reference clock, to prevent error processing caused by signal dyssynchrony, where the reference clock may refer to a reference clock signal rf_clk received by a phase-locked loop PLL. An unlocked interrupt mask signal unlock inr mask may refer to instructions that temporarily mask some interrupts that are not so urgent to avoid interfering with the main flow. In the embodiment of the present application, the main flow may refer to an unlock determination flow. An unlocked interrupt clear signal unlock inr clr may refer to a signal used to clear an interrupt that has occurred so that the system may continue to function properly in preparation for processing a new interrupt signal.

Alternatively, the unlocked interrupt mask signal unlock inr mask and the unlocked interrupt clear signal unlock inr clr may each have a high level 1 and a low level 0. For example, a low level 0 unlocked interrupt mask signal unlock inr mask may be used to indicate a mask signal, whereas a high level 1 unlocked interrupt mask signal unlock inr mask may be used to indicate unmasking.

The unlocked interrupt generation unit 012 may be configured to generate an unlocked interrupt signal and an unlocked alert signal based on the unlocked exception signal, and the synchronized unlocked interrupt mask signal unlock inr mask and unlocked interrupt clear signal unlock inr clr.

Alternatively, the unlocked interrupt generating unit 012 may select whether to mask the unlocked interrupt signal and the unlocked alert signal generated based on the unlocked interrupt mask signal unlock inrmask and select whether to clear the unlocked interrupt signal and the unlocked alert signal generated based on the unlocked interrupt signal based on the unlocked interrupt clear signal unlock inrmask and the unlocked interrupt clear signal based on the unlocked interrupt mask signal unlock inrmask and the unlocked interrupt clear signal unlock inrclr after the synchronization is received, so that the unlocked interrupt signal and the unlocked alert signal are flexibly generated based on the unlocked interrupt signal and the unlocked interrupt mask signal unlock inrmask and the unlocked interrupt clear signal unlock inrclr after the synchronization.

Optionally, the lock detection module 01 may be further configured to output an out-of-lock indication signal if a jump edge of the lock indication signal lock is detected after detecting that the lock indication signal lock (i.e. pll_lock) meets the lock requirement. That is, the lock detection module 01 may also be used to detect whether the phase locked loop PLL is unlocked again after locking. In this way, the detection function can be further enriched.

Alternatively, after the phase-locked loop PLL is in a locked state, the lock indication signal locked may be kept at a high level for a certain period of time, and once the high level is powered down to a low level, the phase-locked loop PLL may be considered to be out of lock. Accordingly, the transition edge of the lock indication signal locked may refer to a falling edge that transitions from a high level to a low level. Accordingly, it can be known that, after detecting that the lock indication signal locked meets the lock requirement, the lock detection module 01 may continue to detect the falling edge of the lock indication signal locked in real time to determine whether the PLL is unlocked, if the level of the lock indication signal locked is detected to be high level 1. For example, the lock detection module 01 may determine that the phase-locked loop PLL is out of lock once detecting that the lock indication signal locked has a falling edge. At this time, the lock detection module 01 may output an out-of-lock indication signal to indicate that the phase-locked loop PLL is out of lock.

Optionally, the lock detection module 01 may also output the unlock indication signal to the controller, so as to instruct the controller to timely adjust parameters in the PLL or control the PLL to stop working when the PLL is unlocked, so as to avoid that a circuit working based on a clock signal generated by the PLL cannot work normally.

Optionally, as can also be seen with continued reference to FIG. 2, the out-of-lock indication signal may include an out-of-lock interrupt signal and an out-of-lock alarm signal. Accordingly, as shown in fig. 3, the lock detection module 01 may include a second lock monitor unit 014 and an out-of-lock interrupt generation unit 015 connected to each other, and the out-of-lock interrupt generation unit 015 may also be used to connect with a controller and registers.

The second lock monitor unit 014 may be configured to receive the lock indication signal lock (i.e. pll_lock), and after generating a clock signal by the PLL, if the lock indication signal lock is detected to meet the lock requirement, output an out-of-lock exception signal to the out-of-lock interrupt generating unit 015 when a transition edge (e.g. a falling edge) of the lock indication signal is detected. That is, whether or not the lock instruction signal locked occurs on the falling edge may be detected by the second lock monitor unit 014.

Alternatively, in conjunction with fig. 3, when the second lock monitor unit 014 detects a falling edge of the lock indication signal lock, the level of the signal pll_ locklose outputted to the out-of-lock interrupt generation unit 015 may be pulled up from the initial low level to the high level, that is, the high level signal pll_ locklose is outputted to the out-of-lock interrupt generation unit 015 to indicate that the lock indication signal lock has a falling edge, that is, to indicate that the phase-locked loop PLL is out of lock. In other words, the out-of-lock abnormality signal output from the second lock monitor unit 014 to the out-of-lock interrupt generation unit 015 may refer to the signal pll_ locklose of high level. Of course, the level pulling process is not limited, and the level pulling process may be from the initial high level to the low level, which is not limited in the embodiment of the present application.

The out-of-lock interrupt generation unit 015 may be configured to generate an out-of-lock interrupt signal and an out-of-lock alarm signal based on the out-of-lock abnormal signal (i.e., the high-level signal pll_ locklose), and output the out-of-lock interrupt signal to the controller and the out-of-lock alarm signal to the register. That is, the out-of-lock instruction signal may be generated and output by the out-of-lock interrupt generation unit 015 based on the out-of-lock abnormality signal output by the second lock monitoring unit 014.

Optionally, the out-of-lock interrupt generating unit 015 may also output the generated out-of-lock interrupt signal and the out-of-lock alarm signal to the controller and the register through different output channels, so that the controller may adjust the operation of the PLL based on the out-of-lock interrupt signal in time, so as to avoid abnormal operation of the PLL, which may cause a circuit that operates based on a clock signal generated by the PLL to fail to operate normally, and may also cause the controller to invoke the out-of-lock alarm signal from the register through polling or other mechanisms to determine whether the PLL operates normally. The detection can be made more timely and accurate than the mode that the above embodiment can only poll the call from the register.

Optionally, as can also be seen with continued reference to FIG. 3, the lock detection module 01 may further comprise an out-of-lock synchronization unit 016. The out-of-lock synchronization unit 016 may be connected to an out-of-lock break generation unit 015.

The out-of-lock synchronization unit 016 may be configured to receive the out-of-lock interrupt mask signal lock lose intr mask and the out-of-lock interrupt clear signal lock lose intr clr, synchronize the out-of-lock interrupt mask signal lock lose intr mask and the out-of-lock interrupt clear signal lock lose intr clr, and output the synchronized out-of-lock interrupt mask signal lock lose intr mask and out-of-lock interrupt clear signal lock lose intr clr to the out-of-lock interrupt generation unit 015.

The out-of-lock interrupt generation unit 015 may be configured to generate an out-of-lock interrupt signal and an out-of-lock alarm signal based on the synchronized out-of-lock exception signal, and the synchronized out-of-lock interrupt mask signal lock lose intr mask and out-of-lock interrupt clear signal lock lose intr clr.

That is, in the same manner as the unlock synchronizing unit 013, the unlock synchronizing unit 016 may be configured to synchronize the unlock interruption shielding signal lock lose intr mask and the unlock interruption clearing signal lock lose intr clr received from the outside, so that the unlock interruption generating unit 015 may refer to the unlock interruption shielding signal lock lose intr mask and the unlock interruption clearing signal lock lose intr clr after the synchronization to flexibly and reliably generate the unlock interruption signal and the unlock warning signal when generating the unlock interruption signal and the unlock warning signal.

It is to be understood that, regarding the out-of-lock synchronization unit 016, the out-of-lock interrupt mask signal lock lose intr mask, the out-of-lock interrupt clear signal lock lose intr clr, and the like, reference may be made to the foregoing descriptions for the out-of-lock synchronization unit 013, the out-of-lock interrupt mask signal unlock inr mask, and the out-of-lock interrupt clear signal unlock inr clr, and the detailed description will not be repeated.

Alternatively, as can be seen with continued reference to fig. 3, the second lock monitoring unit 014 may be common with the first lock monitoring unit 011 included in the lock detection module 01. That is, in the lock detection module 01, the lock monitoring unit for monitoring whether the lock indication signal locked meets the lock requirement and the lock monitoring unit for monitoring whether the lock indication signal locked has a falling edge may be the same lock monitoring unit. And/or, the out-of-lock synchronization unit 016 may be shared with the out-of-lock synchronization unit 013 included in the lock detection module 01. That is, in the lock detection module 01, the synchronization unit for synchronizing the unlocked abnormal signal and the synchronization unit for synchronizing the unlocked abnormal signal may be the same synchronization unit. Thus, the circuit structure can be simplified, and the cost can be saved.

Alternatively, as can be seen with continued reference to fig. 3, the lock detection module 01 may be further configured to receive a phase-locked enable signal pll_en and a reference clock signal rf_clk input to the phase-locked loop PLL, and in response to the phase-locked enable signal pll_en, count according to the reference clock signal rf_clk, and determine that the phase-locked loop PLL generates a clock signal when the count reaches a phase-locked count reference pll_ locknum. Wherein the phase-locked count reference pll_ locknum is related to a standard clock period during which the phase-locked loop PLL generates a clock signal. For example, the phase-locked count reference pll_ locknum may be equal to or greater than the standard clock period.

Optionally, as can be seen with continued reference to fig. 1, the phase-locked loop PLL may also receive a phase-locked enable signal pll_en to start operating based on the phase-locked enable signal pll_en. For example, the PLL may be connected to the PLL enable terminal to receive the PLL enable signal pll_en provided by the PLL enable terminal. The pll_en may refer to a high level signal provided by the pll enable terminal, whereas a low level signal provided by the pll enable terminal may represent a disable signal. That is, the phase lock enable signal pll_en may be represented by pulling up the level of the signal provided by the phase lock enable terminal. The phase-locked loop PLL may start to operate after receiving the high level phase-locked enable signal pll_en. The phase-locked enable signal pll_en may also be referred to as an on signal of the phase-locked loop PLL. Correspondingly, the lock detection module 01 may count according to the reference clock signal rf_clk based on the phase-locked counting reference pll_ locknum when receiving the phase-locked enabling signal pll_en with a high level or when the level of the phase-locked enabling signal pll_en is pulled high, stop counting until the phase-locked counting reference pll_ locknum is counted, and start to detect whether the lock indication signal locked meets the locking requirement. That is, the lock detection module 01 may be a count after the phase locked loop PLL starts to operate. Thus, the problem that the lock detection module 01 starts detection and wastes power consumption when the phase-locked loop PLL does not start operation yet can be avoided.

Alternatively, the pll_ locknum may be flexibly set according to a standard clock period of a clock signal generated by the PLL and stored in the lock detection module 01 in advance. That is, the phase-locked count reference pll_ locknum also belongs to the parameter configuration signal. Also, in connection with fig. 3, in an embodiment of the present application, it may be that the lock monitoring unit included in the lock detection module 01 receives the phase-locked enable signal pll_en and the reference clock signal rf_clk, and counts according to the reference clock signal rf_clk in response to the phase-locked enable signal pll_en.

That is, as shown in fig. 3, the lock detection circuit 01 according to the embodiment of the present application may include four units to implement two kinds of detection of unlocked lock and unlocked lock, and the core unit may be a lock monitoring unit. The lock monitor unit may count according to the reference clock signal rf_clk based on the phase-locked count reference pll_ locknum after the level of the phase-locked enable signal pll_en is pulled up, stop counting until the phase-locked count reference pll_ locknum is counted, and further check whether the lock indication signal locked (i.e., pll_lock) meets the lock requirement, and pull up the level of the signal pll_unlock if not. And after the lock indication signal locked meets the locking requirement, the lock monitoring unit can also detect the falling edge of the pll lock so as to pull up the signal pll_ locklose when the falling edge is detected. The synchronization unit may synchronize the unlocked interrupt mask signal unlock inr mask and the unlocked interrupt clear signal unlock inr clr from the outside and synchronize the out-of-lock interrupt mask signal lock lose intr mask and the out-of-lock interrupt clear signal lock lose intr clr from the outside. The synchronized signal is accessed to the interrupt generating unit to instruct the interrupt generating unit to generate an unlocked interrupt signal and an alarm signal, and an unlocked interrupt signal and an alarm signal, respectively.

Optionally, the clock detection module 02 may be further configured to obtain a third count value based on the third count reference according to the reference clock signal rf_clk, obtain a fourth count value based on the fourth count reference according to the clock signal h_clk to be detected, and output a jitter indication signal if it is detected that a difference between the third count value and the fourth count value is greater than a second difference threshold. That is, the clock detection module 02 may also be configured to detect whether jitter abnormality occurs in the clock signal generated by the phase-locked loop PLL. In this way, the detection function can be further enriched.

It will be appreciated that the third count value and the fourth count value should be close when the clock signal h_clk to be measured generated by the phase-locked loop PLL is not dithered or is relatively small, and the third count value and the fourth count value should be relatively different when the clock signal h_clk to be measured generated by the phase-locked loop PLL is abnormally large dithered (e.g., is dithered for a long time). Accordingly, it can be known that the clock detection module 02 can determine whether the clock signal h_clk to be detected generated by the phase-locked loop PLL has abnormal jitter by detecting whether the difference between the third count value and the fourth count value is large. If the difference between the third count value and the fourth count value is larger, the clock detection module 02 may determine that the clock signal h_clk to be detected has abnormal jitter. At this time, the clock detection module 02 may output a jitter indication signal to indicate the jitter of the clock signal generated by the phase locked loop PLL. Of course, if the difference between the third count value and the fourth count value is smaller or is 0, the clock detection module 02 may determine that the clock signal h_clk to be detected does not have abnormal jitter. At this time, the clock detection module 02 may not output a jitter indication signal, or may output a non-jitter indication signal to indicate that the clock signal generated by the phase-locked loop PLL is not jittered. Alternatively, the jitter indication signal and the non-jitter indication signal may be two signals having different levels, for example, the level of the jitter indication signal may be a high level 1 and the level of the non-jitter indication signal may be a low level 0. It is understood that frequency anomaly dithering may refer to a greater dithering or a longer dithering duration.

Alternatively, the second difference threshold may be preset to measure whether the third count value differs from the fourth count value by a larger amount, and the absolute value of the difference between the third count value and the fourth count value detected by the clock detection module 02 may be greater than the second difference threshold. And, the third count reference and the fourth count reference may be set in advance so that the clock detection module 02 counts based on the third count reference, that is, counts to the third count reference stop counting, when counting according to the reference clock signal rf_clk. Accordingly, the third counting reference may also be called a counting reference of the reference clock, and when counting according to the clock signal h_clk to be measured, counting is performed based on the fourth counting reference, that is, counting is stopped from the fourth counting reference. Accordingly, the fourth count reference may also be referred to as a count reference of the clock under test. And, the third counting reference and the fourth counting reference may be flexibly designed according to the specifications of the phase-locked loop PLL, for example, the third counting reference and the fourth counting reference may be the same to ensure counting under the same time period according to different clock signals. In addition, the third count reference, the fourth count reference, the second difference threshold and the like may also be configured with register parameters to be stored in the clock detection module 02 in advance, so as to be called by the clock detection module 02, which belongs to parameter configuration signals.

Also, it is understood that the third count reference, the fourth count reference, and the second difference threshold may be determined based on the frequency of the clock signal under test h_clk, i.e., may be related to the clock signal under test h_clk, rather than being arbitrarily set. This is distinguished from the count reference and difference thresholds used in frequency offset detection. In other words, the clock detection module 02 detects whether the clock signal h_clk to be detected has the same frequency as the principle of whether jitter occurs, except for the setting of the count reference and the difference threshold.

For example, if it is required to detect whether a clock signal h_clk to be measured of 100 megahertz (MHz) exceeds 30 seconds(s), at least a count reference (i.e., a third count reference) of the reference clock is set to 10000 cycles (cycle), and a count reference (i.e., a fourth reference: 100MHz/0.025 MHz) of the reference clock is set to 12000 cycles, and a second difference threshold is set to 30ps×12000 cycles=36. That is, under this setting, if the clock detection module 02 detects that the difference between the third count value and the fourth count value exceeds 36, a jitter indication signal may be output to reliably indicate the jitter of the clock signal generated by the phase-locked loop PLL.

Optionally, in a similar manner, the clock detection module 02 may also output a jitter indication signal to the controller, so as to instruct the controller to adjust parameters in the PLL in time or control the PLL to stop working when abnormal jitter occurs in the clock signal generated by the PLL, so as to avoid that a circuit working based on the clock signal generated by the PLL cannot work normally.

Alternatively, referring to FIG. 4, the clock detection module 02 may be further configured to receive a detection enable signal check_en, and in response to the detection enable signal check_en, count the reference clock signal rf_clk based on a first count basis to obtain a first count value, and count the reference clock signal h_clk to obtain a second count value based on a second count basis. And/or, responding to the detection enabling signal check_en, counting according to the reference clock signal rf_clk based on the third counting standard to obtain a third counting value, and counting according to the clock signal h_clk to be detected based on the fourth counting standard to obtain a fourth counting value.

Alternatively, the clock detection module 02 may be connected to the detection enable terminal, and the detection enable signal check_en may be a high level signal provided by the detection enable terminal, whereas a low level signal provided by the detection enable terminal may refer to a detection disable signal. That is, the detection enable signal check_en may be represented by pulling up the level of the signal provided by the detection enable terminal. The clock detection module 02 may start to operate after receiving the high level detection enable signal check_en. The detection enable signal check_en may also be referred to as an on signal for clock detection. That is, a switch may be provided to instruct the clock detection module 02 to operate or to stop operating.

It will be appreciated that for some circuits with low requirements on clock quality, frequency offset or jitter of the clock signal generated by the phase-locked loop PLL may have less effect on the operation of the circuit, and at this time, it may not be necessary for the clock detection module 02 to detect whether the clock signal is frequency offset or jitter. In this manner, by setting the detection enable signal check_en to instruct the clock detection module 02 to operate, the clock detection module 02 may be controlled not to operate in some scenarios, thereby reducing the operation power consumption of the clock detection module 02.

Alternatively, as shown in FIG. 4, the clock detection module 02 may include a frequency detection module 021 and a jitter detection module 022.

The frequency detection module 021 may be configured to receive a reference clock signal and a clock signal to be detected, count according to the reference clock signal based on a first count reference to obtain a first count value, count according to the clock signal to be detected based on a second count reference to obtain a second count value, and output a frequency offset indication signal if it is detected that a difference between the first count value and the second count value is greater than a first difference threshold. That is, the frequency detection module 021 may detect whether an abnormal frequency offset occurs in the clock signal generated by the phase-locked loop PLL.

The jitter detection module 022 may be configured to receive the reference clock signal and the clock signal to be detected, count according to the reference clock signal based on a third count reference to obtain a third count value, count according to the clock signal to be detected based on a fourth count reference to obtain a fourth count value, and output a jitter indication signal if it is detected that a difference between the third count value and the fourth count value is greater than a second difference threshold. That is, whether abnormal jitter occurs in the clock signal generated by the phase-locked loop PLL may be detected by the jitter detection module 022.

Alternatively, as can be seen with continued reference to FIG. 2, the frequency offset indication signal may include a frequency anomaly interrupt signal and a frequency anomaly alert signal. Accordingly, as shown in FIG. 5, the frequency detection module 021 may include a frequency monitoring unit 0211 and a frequency abort generating unit 0212 connected to each other, and the frequency abort generating unit 0212 may also be used for connection with a controller and a register.

The frequency monitoring unit 0211 may be configured to receive a reference clock signal rf_clk and a clock signal h_clk to be tested, count according to the reference clock signal rf_clk based on a first count reference to obtain a first count value, count according to the clock signal h_clk to be tested based on a second count reference to obtain a second count value, and output a frequency anomaly signal to the frequency anomaly interrupt generating unit 0212 if detecting that the difference between the first count value and the second count value is greater than a first difference threshold. That is, whether or not the clock signal generated by the phase locked loop PLL is frequency offset may be detected by the frequency monitoring unit 0211.

Optionally, in conjunction with fig. 5, when detecting that the difference between the first count value and the second count value is greater than the first difference threshold, the frequency monitor unit 0211 may pull the level of the signal hclk _err output to the frequency abort generating unit 0212 from an initial low level to a high level, that is, output the signal hclk _err of the high level to the frequency abort generating unit 0212 to indicate that the first count value and the second count value are greatly different, that is, indicate that the frequency of the clock signal generated by the phase-locked loop PLL is abnormally shifted. In other words, the frequency anomaly signal output from the frequency monitor unit 0211 to the frequency anomaly interrupt generation unit 0212 may refer to a signal hclk _err of high level. Of course, the level pulling process is not limited, and the level pulling process may be from the initial high level to the low level, which is not limited in the embodiment of the present application.

Optionally, two counters may be included in the frequency monitoring unit 0211. When the detection enable signal check_en is detected, one counter can count according to the reference clock signal rf_clk, and the other counter can be started to count according to the clock signal h_clk to be detected, then the two obtained count values can be compared, and once the two count values differ by more than a difference threshold value, a frequency abnormality signal can be output.

The frequency abort generation unit 0212 may be configured to generate a frequency abort signal and a frequency abort alarm signal based on a frequency abort signal (i.e., a high-level signal hclk _err), and output the frequency abort signal to the controller and the frequency abort alarm signal to the register. That is, the frequency offset indication signal may be generated and output by the frequency abort generation unit 0212 based on the frequency abort signal output from the frequency monitoring unit 0211.

Optionally, the frequency abort generating unit 0212 may also output the generated frequency abort signal and the frequency abort alarm signal to the controller and the register through different output channels, so that the controller may adjust the operation of the PLL based on the frequency abort signal in time, so as to avoid that the clock signal generated by the PLL is abnormal, which results in that a circuit operating based on the clock signal generated by the PLL cannot operate normally, and may also cause the controller to invoke the frequency abort alarm signal from the register by polling or other mechanisms to determine whether the clock signal generated by the PLL is normal. The detection can be made more timely and accurate than the mode that the above embodiment can only poll the call from the register.

Optionally, the frequency monitor unit 0211 may also be used in connection with registers. On the basis of this, the frequency monitoring unit 0211 can also be used to determine the frequency deviation information hclk _ppm and output the frequency deviation information to a register.

Wherein, the frequency deviation information hclk _ppm may refer to a specific frequency deviation parameter, i.e. the magnitude of the frequency deviation. The register can reliably determine whether the clock signal generated by the phase-locked loop PLL generates frequency deviation or not by combining the frequency deviation information and the frequency abnormality alarm information. Of course, in some embodiments, the frequency monitoring unit 0211 may also output the frequency deviation information hclk _ppm to the out-of-lock interruption generating unit 015 so that the out-of-lock interruption generating unit 015 reliably generates the frequency abnormality interruption signal and the frequency abnormality warning signal in combination with the frequency deviation information hclk _ppm.

Optionally, as can be seen with continued reference to fig. 5, the frequency detection module may further comprise a frequency anomaly synchronization unit 0213. The frequency abnormality synchronization unit 0213 is connected to the frequency abnormality interrupt generation unit 0212.

The frequency anomaly synchronization unit 0213 may be used for receiving the frequency anomaly interrupt mask signal freq_ HLCK INRT MASK and the frequency anomaly interrupt clear signal freq_ HLCK INRT CLR, synchronizing the frequency anomaly interrupt mask signal freq_ HLCK INRT MASK and the frequency anomaly interrupt clear signal freq_ HLCK INRT CLR, and outputting the synchronized frequency anomaly interrupt mask signal freq_ HLCK INRT MASK and frequency anomaly interrupt clear signal freq_ HLCK INRT CLR to the frequency anomaly interrupt generation unit 0212.

The frequency abort generating unit 0212 may be configured to generate a frequency abort signal and a frequency abort alarm signal based on the synchronized frequency abort signal, and the synchronized frequency abort mask signal freq_ HLCK INRT MASK and the frequency abort clear signal freq_ HLCK INRT CLR.

That is, as with the unlocking synchronization unit 013, the frequency anomaly synchronization unit 0213 may be provided to synchronize the frequency anomaly interrupt mask signal freq_ HLCK INRT MASK and the frequency anomaly clear signal freq_ HLCK INRT CLR received from the outside, so that the frequency anomaly interrupt generation unit 0212 also refers to the synchronized frequency anomaly interrupt mask signal freq_ HLCK INRT MASK and frequency anomaly clear signal freq_ HLCK INRT CLR when generating the frequency anomaly interrupt signal and frequency anomaly alert signal, to flexibly and reliably generate the frequency anomaly interrupt signal and frequency anomaly alert signal.

It is to be understood that, regarding the frequency anomaly synchronization unit 0213, the frequency anomaly interrupt mask signal freq_ HLCK INRT MASK, the frequency anomaly interrupt clear signal freq_ HLCK INRT CLR, and the like, reference may be made to the foregoing descriptions for the unlocked synchronization unit 013, the unlocked interrupt mask signal unlock inr mask, and the unlocked interrupt clear signal unlock inr clr, and the detailed description will not be repeated.

Alternatively, as can be seen with continued reference to FIG. 2, the jitter indication signal may include a jitter anomaly interrupt signal and a jitter anomaly alert signal. Accordingly, as shown in FIG. 6, the jitter detection module 022 may include a jitter monitoring unit 0221 and a jitter abort generation unit 0222 connected to each other, and the jitter abort generation unit 0222 may also be used for connection with a controller and a register.

The jitter monitoring unit 0221 may be configured to receive the reference clock signal rf_clk and the clock signal to be measured h_clk, count the reference clock signal rf_clk based on a third count value, count the reference clock signal to be measured h_clk based on a fourth count value, and output a jitter abnormal signal to the jitter abnormal interrupt generating unit 0222 if it is detected that a difference between the third count value and the fourth count value is greater than a second difference threshold. That is, whether or not jitter abnormality occurs in the clock signal generated by the phase-locked loop PLL may be detected by the jitter monitoring unit 0221.

Alternatively, in combination with fig. 6, the same-frequency monitoring unit 0211 may also, when detecting that the difference between the third count value and the fourth count value is greater than the second difference threshold, pull the level of the signal hclk _jitter output to the jitter-abort generating unit 0222 from the initial low level to the high level, that is, output the signal hclk _jitter of the high level to the jitter-abort generating unit 0222 to indicate that the third count value and the fourth count value are greatly different, that is, to indicate that the clock signal generated by the phase-locked loop PLL is abnormally jittered. In other words, the jitter abnormal signal output from the jitter monitoring unit 0221 to the jitter abnormal interrupt generation unit 0222 may refer to the signal hclk _jitter of high level. Of course, the level pulling process is not limited, and the level pulling process may be from the initial high level to the low level, which is not limited in the embodiment of the present application.

Alternatively, two counters may be included in the same frequency monitor unit 0211 and the jitter monitor unit 0221. When the detection enable signal check_en is detected, one counter can count according to the reference clock signal rf_clk, and the other counter can be started to count according to the clock signal h_clk to be detected, then the two obtained count values can be compared, and once the two count values differ by more than a difference threshold value, a jitter abnormal signal can be output.

The jitter anomaly generation unit 0222 may be configured to generate a jitter anomaly interrupt signal and a jitter anomaly alert signal based on the jitter anomaly signal (i.e., the high level signal hclk _jitter), and output the jitter anomaly interrupt signal to the controller and the jitter anomaly alert signal to the register. That is, the shake instruction signal may be generated and output by the shake abort generation unit 0222 based on the shake abnormality signal output by the shake monitoring unit 0221.

Optionally, the jitter anomaly interrupt generating unit 0222 may also output the generated jitter anomaly interrupt signal and the jitter anomaly alarm signal to the controller and the register through different output channels, respectively, so that the controller may adjust the operation of the phase-locked loop PLL in time based on the jitter anomaly interrupt signal, so as to avoid that the clock signal generated by the phase-locked loop PLL is abnormal, which results in that a circuit operating based on the clock signal generated by the phase-locked loop PLL cannot operate normally, and may also cause the controller to invoke the jitter anomaly alarm signal from the register through polling or other mechanisms to determine whether the clock signal generated by the phase-locked loop PLL is normal. The detection can be made more timely and accurate than the mode that the above embodiment can only poll the call from the register.

Alternatively, as can be seen with continued reference to fig. 6, the jitter detection module 022 may further include a jitter anomaly synchronization unit 0223. The jitter abnormality synchronization unit 0223 is connected to the jitter abnormality interrupt generation unit 0222.

The jitter anomaly synchronizing unit 0223 may be configured to receive the jitter anomaly masking signal jitter_ HLCK INRT MASK and the jitter anomaly removal signal jitter_ HLCK INRT CLR, synchronize the jitter anomaly masking signal jitter_ HLCK INRT MASK and the jitter anomaly removal signal jitter_ HLCK INRT CLR, and output the synchronized jitter anomaly masking signal jitter_ HLCK INRT MASK and jitter anomaly removal signal jitter_ HLCK INRT CLR to the jitter anomaly generation unit 0222.

The jitter anomaly generation unit 0222 may be configured to generate a jitter anomaly signal and a jitter anomaly alert signal based on the synchronized jitter anomaly signal, and the synchronized jitter anomaly interrupt mask signal jitter_ HLCK INRT MASK and the jitter anomaly clear signal jitter_ HLCK INRT CLR.

That is, in the same manner as the unlock synchronizing unit 013, the shake anomaly synchronizing unit 0223 may be provided to synchronize the shake abort mask signal jitter_ HLCK INRT MASK and the shake abort clear signal jitter_ HLCK INRT CLR received from the outside, so that the shake abort generating unit 0222 also refers to the shake abort mask signal jitter_ HLCK INRT MASK and the shake abort clear signal jitter_ HLCK INRT CLR after the synchronization when generating the shake abort signal and the shake abort alarm signal, to flexibly and reliably generate the shake abort signal and the shake abort alarm signal.

It is to be understood that, regarding the jitter anomaly synchronization unit 0223, the jitter abort mask signal jitter_ HLCK INRT MASK, the jitter abort clear signal jitter_ HLCK INRT CLR, and the like, reference may be made to the foregoing descriptions for the unlocked synchronization unit 013, the unlocked abort mask signal unlock inr mask, and the unlocked abort clear signal unlock inr clr, and the detailed description will not be repeated. Alternatively, as can also be seen in connection with fig. 1 to 6, the phase locked loop PLL may receive a reset signal rst to reset based on the reset signal rst. And, each unit in the detection circuit 00 may receive a reset signal rst to reset based on the reset signal rst. The reset signal rst received by the phase-locked loop PLL and the reset signal rst received by the detection circuit 00 may be identical.

Optionally, based on the foregoing, it can be known that the detection circuit provided by the embodiment of the application can realize continuous monitoring of the loss of lock, unlocking and frequency deviation and jitter of the generated clock signal of the PLL, and also has the functions of enabling control and enhancing the working stability of the circuit. The detection circuit mainly comprises three independent detection modules, namely a locking detection module, a frequency detection module and a jitter detection module. The lock detection module can realize two detection of unlocking detection and unlocking detection, wherein the unlocking detection is to detect whether the phase-locked loop PLL generates a stable clock signal within a certain clock period. Of course, when the phase-locked loop PLL needs to be reconfigured, the level of pll_en may be controlled to be low, and the lock indication signal locked may be detected after waiting for a prescribed clock period again. The lock-out detection is to detect the falling edge of the lock indication signal locked. The frequency detection module can detect any degree of frequency offset error and generate an alarm. For the frequency detection module, the count reference and the difference threshold may be configured as desired. The jitter detection module is similar to the frequency detection module in principle, except for the setting of the counting reference. For frequency detection, the higher the count reference, the higher the detection accuracy, but the minimum value need not be limited. For jitter detection, the count reference needs to set a minimum value, such as 10000 cycles, according to the frequency of the clock signal h_clk to be detected. Therefore, the abnormity of the phase-locked loop PLL can be timely and comprehensively found, and the working stability of a circuit working based on the clock signal generated by the phase-locked loop PLL is improved.

Optionally, each portion of the detection circuit 00 described in the embodiments of the present application may include a register and a logic circuit (e.g., a gate circuit) to implement the detection function described above. Of course, in some embodiments, the controller may also directly obtain the locked indication signal locked output by the PLL to determine whether the PLL generating clock is stable, and may implement jitter detection and frequency detection by an oscilloscope or a spectrum analyzer.

The embodiment of the application also provides a phase-locked loop circuit. As shown in fig. 7, the phase-locked loop circuit comprises a phase-locked loop PLL, and a detection circuit 00 as shown in any of fig. 1 to 6.

The detection circuit 00 is connected to the phase-locked loop PLL and is used for detecting the operation of the phase-locked loop PLL.

It will be appreciated that the technical effects of the pll circuit are not repeated here for the sake of brevity, since the pll circuit has substantially the same technical effects as the detection circuit described above.

The embodiment of the application also provides electronic equipment. As shown in fig. 8, the electronic device includes a controller 100, a register 200, and a phase-locked loop circuit 000 as shown in fig. 7.

The detection circuit 00 in the phase-locked loop circuit 000 is connected to the controller 100 and the register 200, respectively, and is configured to output a detection result for the phase-locked loop PLL to the controller 100 and the register 200.

Optionally, the electronic device according to the embodiment of the present application may include a microprocessor, a digital signal processor, a wireless communication device, or the like.

It will be appreciated that the technical effects of the electronic device are not repeated here for the sake of brevity, since the electronic device has substantially the same technical effects as the phase-locked loop circuit described above.

It is to be understood that the terminology used in the description of the embodiments of the application is for the purpose of describing particular embodiments of the application only, and is not intended to be limiting. Unless defined otherwise, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs.

As used in the specification and claims of this application, the terms "first," "second," or "third," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items. "upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed. "connected" or "coupled" refers to electrical connections. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The above embodiments are merely exemplary embodiments of the present application and are not intended to limit the present application, any modifications, equivalent substitutions, improvements, etc. that fall within the principles of the present application should be included in the scope of the present application.

Claims

1. The detection circuit of the phase-locked loop is characterized by comprising a locking detection module and a clock detection module, wherein the locking detection module and the clock detection module are connected with the phase-locked loop;

2. The detection circuit of claim 1, wherein the unlock indication signal comprises an unlock interrupt signal and an unlock alert signal, wherein the lock detection module comprises a first lock monitor unit and an unlock interrupt generation unit coupled to each other, and wherein the unlock interrupt generation unit is further configured to interface with a controller and a register;

3. The detection circuit of claim 2, wherein the lock detection module further comprises an unlocked synchronization unit, the unlocked synchronization unit being coupled to the unlocked interrupt generation unit;

4. The detection circuit according to any one of claims 1 to 3, wherein the lock detection module is further configured to output an out-of-lock indication signal if a transition edge of the lock indication signal is detected after detecting that the lock indication signal meets a lock requirement.

5. The detection circuit of claim 4, wherein the out-of-lock indication signal comprises an out-of-lock interrupt signal and an out-of-lock alarm signal, the lock detection module comprises a second lock monitoring unit and an out-of-lock interrupt generating unit which are connected with each other, and the out-of-lock interrupt generating unit is further used for being connected with a controller and a register;

6. The detection circuit according to claim 5, wherein the lock detection module further comprises an out-of-lock synchronization unit connected to the out-of-lock interrupt generation unit;

7. The detection circuit of claim 6, wherein the second lock monitor unit is common to a first lock monitor unit included in the lock detection module and/or wherein the out-of-lock synchronization unit is common to an out-of-lock synchronization unit included in the lock detection module.

8. The detection circuit of any one of claims 1 to 3, wherein the lock detection module is further configured to receive a phase-locked enable signal and the reference clock signal input to the phase-locked loop, and in response to the phase-locked enable signal, count based on the reference clock signal, and determine that the phase-locked loop generates a clock signal when the count reaches a phase-locked count reference, wherein the phase-locked count reference is related to a standard clock period at which the phase-locked loop generates the clock signal.

9. The detection circuit according to any one of claims 1 to 3, wherein the clock detection module is further configured to count the reference clock signal based on a third count value, count the clock signal to be detected based on a fourth count value, and output a jitter indication signal if it is detected that a difference between the third count value and the fourth count value is greater than a second difference threshold.

10. The detection circuit of claim 9, wherein the clock detection module is further configured to receive a detection enable signal, and in response to the detection enable signal, count the first count value based on the first count reference and the second count value based on the second count reference and the clock signal under test, and/or in response to the detection enable signal, count the third count value based on the third count reference and the fourth count value based on the fourth count reference and the clock signal under test.

11. The detection circuit of claim 9, wherein the clock detection module comprises a frequency detection module and a jitter detection module;

12. The detection circuit of claim 11, wherein the frequency offset indication signal comprises a frequency abort signal and a frequency abort alarm signal, wherein the frequency detection module comprises a frequency monitoring unit and a frequency abort generation unit that are connected to each other, and wherein the frequency abort generation unit is further configured to be connected to a controller and a register;

13. The detection circuit according to claim 12, wherein the frequency detection module further comprises a frequency abnormality synchronization unit connected to the frequency abnormality interrupt generation unit;

14. The detection circuit of claim 12, wherein the frequency monitor unit is further configured to be coupled to the register, and wherein the frequency monitor unit is further configured to determine frequency deviation information and output the frequency deviation information to the register;

15. The detection circuit of claim 11, wherein the jitter indication signal comprises a jitter abort signal and a jitter abort alarm signal, wherein the jitter detection module comprises a jitter monitoring unit and a jitter abort generation unit connected to each other, and wherein the jitter abort generation unit is further configured to connect with a controller and a register;

16. The detection circuit according to claim 15, wherein the jitter detection module further comprises a jitter anomaly synchronization unit connected with the jitter anomaly interrupt generation unit;

17. A phase-locked loop circuit comprising a phase-locked loop and a detection circuit as claimed in any one of claims 1 to 16;

18. An electronic device comprising a controller, a register, and the phase-locked loop circuit of claim 17;