CN119512485A - GPU video memory and bandwidth adjustment method and system based on bus bandwidth monitoring - Google Patents

Abstract

The present invention provides a GPU video memory and bandwidth adjustment method and system based on bus bandwidth monitoring. The method monitors the information of each internal module, bus and external display device of a GPU chip in real time, calculates the video memory size and display data read-back time required by each internal module and external display device, and then configures the priority and access time of the video memory according to the bus bandwidth, thereby improving the bus bandwidth utilization rate, effectively reducing the bus bandwidth, avoiding data loss, overwriting and large read-back delay caused by bus competition and low bus utilization rate, thereby avoiding image tearing, screen distortion and frame skipping, ensuring real-time and stable display of images, and the design method can effectively reduce system power consumption.

Description

GPU video memory and bandwidth adjusting method and system based on bus bandwidth monitoring

Technical Field

The invention relates to the field of bus bandwidth monitoring, in particular to a method and a system for regulating GPU video memory and bandwidth based on bus bandwidth monitoring.

Background

Along with the continuous improvement of display technology and the update iteration of office equipment, the requirements of various industries on display are higher and higher, and the requirements on multi-display interfaces and multi-resolution simultaneous display are also required to be energy-saving and consumption-reducing in the increasingly competitive market, so the requirements on bus bandwidth, utilization rate and transmission rate are also higher and higher. Conventional GPU display controllers store pixels in a buffer and read from the buffer when the display is active, at a fixed timing and with a prefetch pattern allocated upon register initialization. However, with the increase of the resolution, the data volume will be increased sharply, the requirement for the data reading rate will be higher and higher, and the external display device will be replaced or turned off, which will not be perceived in time, and these will all put new demands on the dynamic configuration of the bus bandwidth and transmission mode.

In the mode that multiple resolution and multiple interfaces work simultaneously, when multiple modules access the bus simultaneously, competition among channels and arbitration of priority all can lead to data delay, loss or coverage, and even phenomena such as tearing of a display image, screen display, frame skip and the like can occur. The existing methods mainly reduce the resolution of each display device or increase the bus bandwidth, and not only waste the bus bandwidth and bring higher production cost, but also greatly reduce the user experience.

Disclosure of Invention

Under the condition that multiple resolutions and multiple interfaces work simultaneously, when multiple modules of the GPU access the video memory simultaneously, the video memory bus access mode is fixed, and the change of external equipment cannot be monitored timely, so that the bus cannot be effectively utilized, and the problems of image tearing, screen display and frame skip are caused.

According to a first aspect of the present invention, there is provided a GPU video memory and bandwidth adjustment method based on bus bandwidth monitoring, including:

Step 1, configuring registers of each module of a GPU chip, configuring clock frequency and resolution of each module, and starting a bandwidth detector when the GPU chip displays, wherein each module of the GPU chip comprises each graphic processor and each display controller;

Step 2, the bandwidth detector acquires the data size and the data rate of each module through a system management bus and acquires the access information of the current bus;

Step 3, according to the acquired data size and rate of each module and the access information of the current bus, reallocating the bandwidth, the video memory and the rate of each module, and writing the allocation information into a function register of a bandwidth monitor;

step 4, after the writing of the function register is completed, the bandwidth monitor informs the host computer in an interrupt mode;

Step 5, the host acquires the allocation information in the function register, configures a CRU module, and reallocates the access memory size, bus bandwidth and rate of each module to complete system initialization;

and step 6, after the initialization is finished, notifying the bandwidth monitor, and starting the system to work.

On the basis of the technical scheme, the invention can also make the following improvements.

Optionally, in step2, obtaining access information of the current bus includes:

counting the read delay time and the data storage size of each port of the bus;

according to the read delay time and the data storage size of each port of the bus, searching a dictionary, determining the clock frequency of the bus, the bandwidth of the data bus and the bandwidth of the address bus, and determining the burst value and the pre-read cycle value of the bus.

Optionally, the dictionary stores bus information, where the bus information includes a bus number, an index entry, and corresponding preferred data, each bus includes a plurality of index entries, one index entry includes a plurality of preferred data, and the index entries include a clock frequency, a data bus width, and an address bus width.

Optionally, step 3, reallocating the bandwidth, the video memory and the rate of each module according to the acquired data size and rate of each module and the access information of the current bus, includes:

if the replacement of the display device is detected, the bus bandwidth information of the display controller needs to be adjusted;

If the display device is not replaced, no adjustment is needed to the bus bandwidth information.

Optionally, if the replacement of the display device is detected, adjustment of bus bandwidth information of the display controller is required, including:

acquiring current bus bandwidth and access information, if the speed of the access bus changes, modifying the bus speed, and configuring a bus speed related register;

if the data size of the access bus is changed, the size of the video memory needs to be modified, and a related register of the video memory is configured;

if the delay time for accessing the bus is required to be changed, the bus bandwidth needs to be modified, and the bus bandwidth related register is configured.

According to a second aspect of the present invention, there is provided a GPU video memory and bandwidth adjustment system based on bus bandwidth monitoring, comprising:

the system comprises a monitor register, a bus configuration register, a bus monitor, a video memory configuration register, an interrupt processing module and a bus management module;

A monitor register for enabling the bus bandwidth function and controlling the switches of the bus monitor, the bus configuration register, the video memory monitor, the video memory configuration register, the interrupt processing module and the bus management module;

The display memory monitor is used for monitoring the replacement of the external equipment of the display controller, acquiring the information of the current display equipment and the replacement display equipment through the system management bus, calculating the display memory size and clock frequency of the display equipment, writing the display memory size and clock frequency into the display configuration register, and informing the host to acquire the change information;

the video memory configuration register is used for storing clock frequency, display resolution and external display equipment information of the display controller;

the bus monitor is used for monitoring the bandwidth, address, clock frequency, burst length and information of the bus interface connection module of the bus interface, writing the information into the bus configuration register, informing the host to acquire the information and configuring the parameters of each bus interface;

the bus configuration register is used for storing initialization information, pre-configuration information and current real-time configuration information of the bus;

the interrupt processing module is used for generating video memory configuration interrupt and bus configuration interrupt, notifying a host of the interrupt in an IO and register mode, and processing various interrupts of external equipment;

the bus management module is used for managing the configuration modes of the video memory bus and the internal bus, updating and maintaining configuration information, and communicating with the host and the external device through the SMBus, the AMBA and the custom bus.

According to the GPU video memory and bandwidth adjusting method and system based on bus bandwidth monitoring, the information of each internal module, the bus and the external display device of the GPU chip is monitored in real time, the video memory size and the display data read-back time required by each internal module and the external display device are calculated, the priority and the access time of accessing the video memory are configured according to the bus bandwidth, the bus bandwidth utilization rate is improved, the bus bandwidth is effectively reduced, the problems of image tearing, screen display and frame skip caused by large data loss, coverage and read-back delay due to bus competition and low bus utilization rate are avoided, the real-time stable display of images is ensured, and the design method can effectively reduce the system power consumption.

Drawings

FIG. 1 is a flow chart of a GPU video memory and bandwidth adjustment method based on bus bandwidth monitoring provided by the invention;

FIG. 2 is an overall flowchart of a GPU video memory and bandwidth adjustment method based on bus bandwidth monitoring;

FIG. 3 is a flow chart for obtaining bus access information;

FIG. 4 is a schematic diagram of a data structure of a dictionary storing bus information;

FIG. 5 is a schematic diagram of a bus read cycle and read latency;

FIG. 6 is a flow chart of modifying configuration information when an external display device is replaced;

fig. 7 is a block diagram of a GPU video memory and bandwidth adjustment system based on bus bandwidth monitoring according to the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. In addition, the technical features of each embodiment or the single embodiment provided by the invention can be combined with each other at will to form a feasible technical scheme, and the combination is not limited by the sequence of steps and/or the structural composition mode, but is necessarily based on the fact that a person of ordinary skill in the art can realize the combination, and when the technical scheme is contradictory or can not realize, the combination of the technical scheme is not considered to exist and is not within the protection scope of the invention claimed.

The existing bandwidth monitoring method is used for reading back data by monitoring data errors of the bus bandwidth or realizing data prefetching by multi-level caching and reducing bus load by reducing the clock frequency of the bus. The existing method cannot avoid display screen and image tearing, can not improve the exchange efficiency of the bus under the existing bandwidth, and can reasonably adjust the bus priority and burst length.

According to the invention, whether each internal module, the bus and the external display device of the GPU chip are changed or not is monitored in real time, the display memory size and the display data read-back time required by each internal module and the external display device are calculated through the calculation module, the priority and the access time of the access display memory are configured according to the bus bandwidth, the bus bandwidth utilization rate is improved, the bus bandwidth is effectively reduced, the problems of image tearing, screen display and frame skip caused by bus competition and low bus utilization rate are avoided, the real-time stable display of images is ensured, and the design method can effectively reduce the system power consumption.

Fig. 1 is a flowchart of a method for GPU video memory and bandwidth adjustment based on bus bandwidth monitoring, as shown in fig. 1 and fig. 2, and the method includes:

Step 1, configuring registers of all modules of the GPU chip, configuring clock frequency and resolution of all modules, and starting a bandwidth detector when the GPU chip displays, wherein all modules of the GPU chip comprise all graphics processors and all display controllers.

Specifically, when the GPU chip performs display, registers of each graphics processing module and each display controller in the GPU chip need to be configured, clocks and resolutions of different display controllers are configured, and a functional register of the bandwidth monitor is opened.

And 2, the bandwidth detector acquires the data size and the data rate of each module through the system management bus and acquires the access information of the current bus.

Specifically, the bandwidth monitor obtains the data throughput of each graphics processing module through the system management bus, and detailed information and resolution requirements of the external display device of the display controller, such as the size of the external display device, the standard resolution and the non-standard resolution supported by the external display device.

The bandwidth detector acquires the data size and the data rate of each module through the system management bus and acquires the access information on the current bus. The access information on the current bus is obtained by referring to fig. 3, which includes counting the read delay time and the data storage size of each port of the bus, searching a dictionary according to the read delay time and the data storage size of each port of the bus, determining the clock frequency, the data bus bandwidth and the address bus bandwidth of the bus, and determining the burst value and the bus pre-reading period value of the bus.

The data structure of the dictionary storing the bus information can be seen in fig. 4, and the bus information is stored in the dictionary, and the bus information includes a bus number, an index item and corresponding preferred data. Each bus includes a plurality of index entries, for example, a clock frequency of the bus, a data bus width, and an address bus width, and one index entry includes a plurality of preferred data, that is, a plurality of preferred data is configured for one index entry, for example, a plurality of preferred clock frequencies may be configured.

The clock frequency, the data bus width and the address bus width of the bus are determined according to the data size of the bus and the read delay information, and the burst value and the bus pre-read period value of the bus are determined, and the process is shown in fig. 5. The minimum data delay of each module on the bus is ensured, and the bus transmission efficiency is highest.

And step 3, reallocating the bandwidth, the video memory and the speed of each module according to the acquired data size and the speed of each module and the access information of the current bus, and writing the allocation information into a function register of the bandwidth monitor.

Specifically, referring to fig. 6, in the step 3, the bandwidth, the video memory and the rate of each module are redistributed according to the acquired data size and rate of each module and the access information of the current bus, which includes that if the display device is detected to be replaced, the bus bandwidth information of the display controller needs to be adjusted, and if the display device is not replaced, the bus bandwidth information does not need to be adjusted.

The method comprises the steps of obtaining current bus bandwidth and access memory information, if the change of the access bus speed is detected, modifying the bus speed, configuring a bus speed related register, if the change of the data volume of the access bus is detected, modifying the video memory, configuring the video memory related register, and if the change of the delay time of the access bus is detected, modifying the bus bandwidth, and configuring the bus bandwidth related register.

It will be appreciated that the bus and memory sizes and bandwidths are reassigned according to different change information for the display device and the reassignment information is stored in a register that stores the module that needs reassignment and which information the module reassigns, e.g., whether to modify the bus rate or the memory size or modify the bus bandwidth, and the reassignment information is stored in the associated register.

And 4, after the writing of the function register is completed, the bandwidth monitor informs the host in an interrupt mode.

It will be appreciated that when the reassigned information is written to a register, the host is notified in the form of an interrupt informing the host that the bandwidth monitor detects that the rate, bandwidth or resolution information of the corresponding module needs to be adjusted.

And step 5, the host acquires the allocation information in the function register, configures a CRU module, and reallocates the access memory size, bus bandwidth and rate of each module to complete system initialization.

It can be understood that after the host receives the interrupt, the host accesses the register of the bandwidth monitor, acquires modification information (reassignment information), configures a CRU (clock reset unit) to change the bus clock rate of the corresponding module, sets registers such as the access size of the bus and the burst size of the bus, configures the data width of the bus, and completes the initialization of the configuration module.

And step 6, after the initialization is finished, notifying the bandwidth monitor, and starting the system to work.

It can be understood that after the initialization of the configuration module is completed, the register is written to notify the bus monitor that the configuration is completed and the system starts to work.

Referring to fig. 7, the invention further provides a GPU video memory and bandwidth adjusting system based on bus bandwidth monitoring, which can realize GPU video memory and bandwidth adjustment, and mainly comprises a monitor register, a bus configuration register, a bus monitor, a video memory configuration register, an interrupt processing module and a bus management module.

The monitor register is used for enabling the bus bandwidth function and controlling the switches of the bus monitor, the bus configuration register, the video memory monitor, the video memory configuration register, the interrupt processing module and the bus management module;

The display memory monitor is used for monitoring the replacement of the external equipment of the display controller, acquiring the information of the current display equipment and the replacement display equipment through the system management bus, calculating the display memory size and clock frequency of the display equipment, writing the display memory size and clock frequency into the display configuration register, and informing the host to acquire the change information;

the video memory configuration register is used for storing clock frequency, display resolution and external display equipment information of the display controller;

the bus monitor is used for monitoring the bandwidth, address, clock frequency, burst length and information of the bus interface connection module of the bus interface, writing the information into the bus configuration register, informing the host to acquire the information and configuring the parameters of each bus interface;

the bus configuration register is used for storing initialization information, pre-configuration information and current real-time configuration information of the bus;

the interrupt processing module is used for generating video memory configuration interrupt and bus configuration interrupt, notifying a host of the interrupt in an IO and register mode, and processing various interrupts of external equipment;

the bus management module is used for managing the configuration modes of the video memory bus and the internal bus, updating and maintaining configuration information, and communicating with the host and the external device through the SMBus, the AMBA and the custom bus.

It can be understood that the GPU video memory and bandwidth adjusting system provided by the invention can realize the video memory and bandwidth allocation of each module and the display controller in the GPU chip. And enabling the bus monitor, the bus configuration register, the video memory monitor, the video memory configuration register and the interrupt processing module through the configuration monitor register when the system is initialized. The display memory monitor obtains the display resolution and the current display resolution of each display controller external device through the display memory configuration register and the system management bus. And generating an interrupt by the interrupt processing module to inform the host to acquire the display information and allocate the display memory size of each display device. The bus monitor obtains the protocol type, transmission bandwidth, clock frequency, burst length of each bus and the actual transmission information of the current bus through the bus configuration register and the system management bus. And the host is informed to acquire bus information by generating an interrupt through the interrupt processing module, calculates the bandwidth, address, clock frequency, burst length and priority of the bus according to the module function connected with each bus port, configures a bus configuration register through the system management module, completes configuration, and monitors bus change in real time.

It can be understood that the GPU video memory and bandwidth adjusting system based on bus bandwidth monitoring provided by the present invention corresponds to the GPU video memory and bandwidth adjusting method based on bus bandwidth monitoring provided in the foregoing embodiments, and the relevant technical features of the GPU video memory and bandwidth adjusting system based on bus bandwidth monitoring may refer to the relevant technical features of the GPU video memory and bandwidth adjusting method based on bus bandwidth monitoring, which are not described herein again.

The GPU video memory and bandwidth adjusting method and system based on bus bandwidth monitoring provided by the embodiment of the invention have the following advantages:

(1) The system does not need to increase the memory and bus bandwidth, realizes real-time allocation from hardware by adding a logic control module, flexibly schedules, monitors each module and the bus in real time, monitors whether external display equipment is changed or not, calculates the size of the memory and the read-back time of display data required by the module, and configures the priority and access time of accessing the memory according to the bus bandwidth.

(2) The bus bandwidth monitoring configuration and the video memory monitoring configuration are realized by minimum resources, the bus bandwidth utilization rate is improved, the bus bandwidth is effectively reduced, the problems of image tearing, screen display and frame skip caused by large data loss, coverage and read-back delay due to bus competition and low bus utilization rate are avoided, the image display is facilitated, the instantaneity and the accuracy of the image display are facilitated, the system overhead is reduced, the production cost is saved, and the user experience is improved.

In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.

It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (6)

1. The GPU video memory and bandwidth adjusting method based on bus bandwidth monitoring is characterized by comprising the following steps of:

Step 1, configuring registers of each module of a GPU chip, configuring clock frequency and resolution of each module, and starting a bandwidth detector when the GPU chip displays, wherein each module of the GPU chip comprises each graphic processor and each display controller;

Step 2, the bandwidth detector acquires the data size and the data rate of each module through a system management bus and acquires the access information of the current bus;

Step 3, according to the acquired data size and rate of each module and the access information of the current bus, reallocating the bandwidth, the video memory and the rate of each module, and writing the allocation information into a function register of a bandwidth monitor;

step 4, after the writing of the function register is completed, the bandwidth monitor informs the host computer in an interrupt mode;

Step 5, the host acquires the allocation information in the function register, configures a CRU module, and reallocates the access memory size, bus bandwidth and rate of each module to complete system initialization;

and step 6, after the initialization is finished, notifying the bandwidth monitor, and starting the system to work.

2. The GPU video memory and bandwidth adjustment method according to claim 1, wherein in the step 2, obtaining access information of a current bus comprises:

counting the read delay time and the data storage size of each port of the bus;

according to the read delay time and the data storage size of each port of the bus, searching a dictionary, determining the clock frequency of the bus, the bandwidth of the data bus and the bandwidth of the address bus, and determining the burst value and the pre-read cycle value of the bus.

3. The GPU video memory and bandwidth adjustment method of claim 2, wherein the dictionary stores bus information, the bus information including a bus number, an index entry, and corresponding preference data, wherein each bus includes a plurality of index entries, one index entry includes a plurality of preference data, and the index entries include a clock frequency, a data bus width, and an address bus width.

4. The GPU video memory and bandwidth adjustment method according to claim 3, wherein the step 3 of reallocating the bandwidth, video memory and rate of each module according to the acquired data size and rate of each module and the access information of the current bus comprises:

if the replacement of the display device is detected, the bus bandwidth information of the display controller needs to be adjusted;

If the display device is not replaced, no adjustment is needed to the bus bandwidth information.

5. The GPU video memory and bandwidth adjustment method of claim 4, wherein the adjusting the bus bandwidth information of the display controller if the replacement of the display device is detected comprises:

acquiring current bus bandwidth and access information, if the speed of the access bus changes, modifying the bus speed, and configuring a bus speed related register;

if the data size of the access bus is changed, the size of the video memory needs to be modified, and a related register of the video memory is configured;

if the delay time for accessing the bus is required to be changed, the bus bandwidth needs to be modified, and the bus bandwidth related register is configured.

6. The GPU video memory and bandwidth regulating system based on bus bandwidth monitoring is used for realizing the GPU video memory and bandwidth regulating method according to claim 1, and is characterized by comprising a monitor register, a bus configuration register, a bus monitor, a video memory configuration register, an interrupt processing module and a bus management module;

A monitor register for enabling the bus bandwidth function and controlling the switches of the bus monitor, the bus configuration register, the video memory monitor, the video memory configuration register, the interrupt processing module and the bus management module;

The display memory monitor is used for monitoring the replacement of the external equipment of the display controller, acquiring the information of the current display equipment and the replacement display equipment through the system management bus, calculating the display memory size and clock frequency of the display equipment, writing the display memory size and clock frequency into the display configuration register, and informing the host to acquire the change information;

the video memory configuration register is used for storing clock frequency, display resolution and external display equipment information of the display controller;

the bus monitor is used for monitoring the bandwidth, address, clock frequency, burst length and information of the bus interface connection module of the bus interface, writing the information into the bus configuration register, informing the host to acquire the information and configuring the parameters of each bus interface;

the bus configuration register is used for storing initialization information, pre-configuration information and current real-time configuration information of the bus;

the interrupt processing module is used for generating video memory configuration interrupt and bus configuration interrupt, notifying a host of the interrupt in an IO and register mode, and processing various interrupts of external equipment;

the bus management module is used for managing the configuration modes of the video memory bus and the internal bus, updating and maintaining configuration information, and communicating with the host and the external device through the SMBus, the AMBA and the custom bus.