CN119521701A - Semiconductor device manufacturing method and semiconductor device - Google Patents
Semiconductor device manufacturing method and semiconductor device Download PDFInfo
- Publication number
- CN119521701A CN119521701A CN202411657900.3A CN202411657900A CN119521701A CN 119521701 A CN119521701 A CN 119521701A CN 202411657900 A CN202411657900 A CN 202411657900A CN 119521701 A CN119521701 A CN 119521701A
- Authority
- CN
- China
- Prior art keywords
- gate structure
- gate
- substrate
- target shape
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application provides a semiconductor device manufacturing method and a semiconductor device. The method for manufacturing the semiconductor device comprises the steps of providing a substrate, forming a first gate structure with a target shape on the substrate, wherein the target shape comprises the fact that the size of the first gate structure close to a first surface of the substrate is smaller than the size of the first gate structure far away from a second surface of the substrate, the first surface is opposite to the second surface, the first gate structure comprises a polycrystalline silicon gate, covering a stress film on the substrate and the first gate structure and performing stress treatment to enable the stress film to match the first gate structure with the target shape to improve the stress of a channel region of the substrate under the first gate structure, removing the stress film on the second surface of the first gate structure, and reserving residual stress films covered on two sides of a non-gate structure region of the substrate and the first gate structure. The application also provides a semiconductor device. The application can improve the channel stress, further improve the DC performance and reduce the overlap capacitance.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
With the continuous development of semiconductor technology, the size of transistors is continuously reduced, and as the channel length is reduced to 22nm node and below, the device dc and ac performance is continuously improved, which must be considered.
In addition, as the size of the transistor is reduced, the capacitance value of parasitic capacitance between the grid electrode and a source region or a drain region of the transistor is increased, and the performance of the device is greatly influenced.
Disclosure of Invention
The application provides a method for manufacturing a semiconductor device, which can simultaneously increase the direct current efficiency of the device and relieve the problem of overlap capacitance generated by the shrinkage of the transistor size in the related technology, effectively reduce the overlap capacitance and improve the channel stress.
In order to solve the technical problem, the first aspect of the application provides a manufacturing method of a semiconductor device, which comprises the steps of providing a substrate, forming a first gate structure with a target shape on the substrate, wherein the target shape comprises a dimension of the first gate structure close to a first surface of the substrate, which is smaller than a dimension of the first gate structure far away from a second surface of the substrate, the first surface is opposite to the second surface, the first gate structure with the target shape comprises a polysilicon gate, covering a stress film on the substrate and the first gate structure with the target shape, and performing stress treatment to enable the stress film to match with the first gate structure with the target shape to improve the stress of a channel region of the substrate under the first gate structure with the target shape, and removing the stress film on the second surface of the first gate structure with the target shape, and reserving residual stress films covered on two sides of a non-gate structure region of the substrate and the first gate structure with the target shape.
In some embodiments, the steps of providing a substrate and forming a first gate structure with a target shape on the substrate comprise providing the substrate, forming the first gate structure on the substrate, wherein the first gate structure has a uniform width along a direction approaching the substrate, and etching the first gate structure to form the first gate structure with the target shape, wherein the first gate structure with the target shape has a gradually reduced width along the direction approaching the substrate, or the first surface of the first gate structure with the target shape has a notch relative to the second surface.
In some embodiments, after the substrate is provided and the first gate structure with the target shape is formed on the substrate, the manufacturing method further comprises forming side walls on two sides of the first gate structure with the target shape, and forming a source region and a drain region in the substrate by using the first gate structure with the target shape and the side walls as masks.
In some embodiments, the removing the stress film on the second surface of the first gate structure having the target shape includes overlaying a first dielectric layer on the stress film, and grinding away portions of the dielectric layer and portions of the stress film until the second surface of the first gate structure having the target shape is exposed.
In some embodiments, a second dielectric layer is formed on the remaining first dielectric layer, and a gate contact plug connected to the first gate structure with the target shape is formed in the second dielectric layer, wherein the polysilicon gate in the first gate structure with the target shape is used as a gate.
In some embodiments, the polysilicon gate in the first gate structure with the target shape is removed, and a metal gate is filled in an original region of the polysilicon gate to form a second gate structure, and a second dielectric layer is formed on the residual first dielectric layer, and a gate contact plug connected with the metal gate is formed in the second dielectric layer, wherein the metal gate is used as a gate.
In order to solve the technical problem, the second aspect of the application also provides a semiconductor device, which comprises a substrate, a grid structure with a target shape, and a residual stress film, wherein the target shape is arranged on the substrate, the size of the first surface of the grid structure, which is close to the substrate, is smaller than the size of the second surface of the grid structure, which is far away from the substrate, and the first surface is opposite to the second surface, and the residual stress film covers the non-grid structure area of the substrate and covers two sides of the grid structure.
In some embodiments, the gate structure has a width that gradually decreases in a direction toward the substrate, or the first surface of the gate structure has a notch with respect to the second surface.
In some embodiments, the gate structure includes a gate and a gate oxide layer between the gate and the substrate, wherein the first surface of the gate structure is a surface of the gate oxide layer proximate to the substrate and the second surface of the gate structure is a surface of the gate distal from the substrate.
In some embodiments, the gate comprises a polysilicon gate or a metal gate.
Some embodiments of the present application provide a method for forming a first gate structure having a target shape on a substrate by providing a substrate, wherein the target shape includes a first gate structure having a smaller dimension proximate to a first surface of the substrate than a second surface of the first gate structure distal from the substrate, the first surface being opposite to the second surface, the first gate structure having the target shape including a polysilicon gate, overlaying a stress film on the substrate and the first gate structure having the target shape and performing a stress treatment such that the stress film matches the first gate structure having the target shape to improve stress of a channel region of the substrate under the first gate structure having the target shape, and removing the stress film on the second surface of the first gate structure having the target shape, leaving a residual stress film overlaying both a non-gate structure region of the substrate and the first gate structure having the target shape. Compared with the related art, the method and the device have the advantages that the stress film is covered on the substrate and the first gate structure with the target shape and stress treatment is carried out, so that the stress film can be matched with the first gate structure with the target shape to improve the stress of the channel region of the substrate under the first gate structure with the target shape, the channel stress is improved, the carrier mobility of the device can be effectively improved, and the problem of overlap capacitance is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Wherein:
fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a semiconductor device providing a first gate structure;
Fig. 3 is a schematic view of a semiconductor device forming a first gate structure having a target shape;
Fig. 4 is a schematic view of a first gate structure of a semiconductor device having a target shape;
FIG. 5 is a schematic diagram of a semiconductor device with sidewalls, source and drain regions formed;
FIG. 6 is a schematic diagram of a semiconductor device overlying a stressed film;
FIG. 7 is a schematic diagram of a semiconductor device overlying a first dielectric layer;
fig. 8 is a schematic view of the semiconductor device of fig. 7 after grinding;
Fig. 9 is a schematic view of the semiconductor device of fig. 8 forming a gate contact plug;
Fig. 10 is a schematic view of the semiconductor device of fig. 8 with the polysilicon gate removed;
fig. 11 is a schematic view of a semiconductor device fill metal gate of fig. 10;
fig. 12 is a schematic view of the semiconductor device of fig. 11 forming a gate contact plug.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first" and "second" in the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
All directional indications (such as up, down, left, right, front, rear, top, bottom) in embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular pose (as shown in the drawings), and if the particular pose changes, the directional indication changes accordingly.
Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
In the prior art, when the size of the transistor is reduced to reduce the channel length to 22nm node and below, the overlap capacitance and the dc performance become key factors for limiting the continuous improvement of the device. In addition, due to the reduction of the size of the transistor, the distance between the grid electrode and the source electrode or the drain electrode of the transistor is correspondingly reduced, and parasitic capacitance between the grid electrode and the source region or the drain region of the transistor is easily caused to be larger, so that the performance of the device is also influenced.
In order to solve the above technical problems, some embodiments of the present application provide a method for manufacturing a semiconductor device. The present application will be described in detail with reference to the accompanying drawings and examples.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application, where the method specifically includes:
Providing a substrate, and forming a first gate structure with a target shape on the substrate, wherein the target shape comprises that the size of the first gate structure close to a first surface of the substrate is smaller than that of the first gate structure far away from a second surface of the substrate, the first surface is opposite to the second surface, and the first gate structure with the target shape comprises a polysilicon gate.
In the implementation process, referring to fig. 2 to 5, fig. 2 is a schematic view of providing a first gate structure for a semiconductor device, fig. 3 is a schematic view of forming a first gate structure with a target shape for a semiconductor device, fig. 4 is a schematic view of forming a first gate structure with a target shape for a semiconductor device, and fig. 5 is a schematic view of forming a sidewall, a source region and a drain region for a semiconductor device. Specifically, step S11 includes:
And step S111, providing the substrate.
Referring to fig. 2, fig. 2 is a schematic diagram of a semiconductor device providing a first gate structure. The substrate 100 may be any suitable substrate known in the art, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, but may also be a layered substrate of Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator (SOI), which is not a limitation of the present application.
In some embodiments, a substrate 100 is provided that includes a well region 101 formed in the substrate 100 and shallow trench isolation 102 (shallow trench isolation, STI) isolating the well region 101.
And step S112, forming a first gate structure on the substrate, wherein the width of the first gate structure is consistent along the direction approaching to the substrate.
Referring to fig. 2, fig. 2 is a schematic view of a first gate structure provided in the semiconductor device. The first gate structure 115 includes a gate and a gate oxide 114, the gate oxide 114 is located between the gate and the substrate 100, the gate may be a polysilicon gate 113, the gate oxide 114 may be silicon oxide or the like, wherein the first gate structure 115 includes the polysilicon gate 113 and the gate oxide 114.
The first gate structure 115 has at least a first surface 111 and a second surface 112, wherein the first surface 111 of the first gate structure 115 is a surface of the gate oxide layer 114 near the substrate 100, the second surface 112 of the first gate structure 115 is a surface of the gate away from the substrate 100, and the second surface 112 is opposite to the first surface 111. The cross-sectional view of the first gate structure 115 is rectangular, for example, as shown in fig. 2, wherein the width of the first surface 111 is consistent with the width of the second surface 112. Of course, the width of the first surface 111 and the width of the second surface 112 may not be completely consistent due to the process error during the formation of the first gate structure 115, and the foregoing consistent width of the first gate structure 115 also includes the case of generating the process error.
And step S113, etching the first gate structure to form the first gate structure with the target shape, wherein the width of the first gate structure with the target shape gradually decreases along the direction approaching to the substrate, or the first surface of the first gate structure with the target shape is provided with a notch relative to the second surface.
Specifically, referring to fig. 3 and 4, fig. 3 is a schematic view of a semiconductor device forming a first gate structure having a target shape, and fig. 4 is a schematic view of a semiconductor device forming a first gate structure having a target shape. In one embodiment, as shown in fig. 4 (a), the first gate structure 115 is etched to form a first gate structure 115 conforming to a target shape, wherein the width of the first gate structure 115 having the target shape gradually decreases in a direction approaching the substrate 100, that is, the first surface 111 of the first gate structure 115 having the target shape is smaller in size than the second surface 112, and the first gate structure 115 having the target shape takes a shape with a top large bottom small.
In one embodiment, as shown in fig. 4 (b), the first surface 111 of the first gate structure 115 is etched to form a first gate structure 115 conforming to the target shape, the first surface 111 of the first gate structure 115 having the target shape forms a notch with respect to the second surface 112, the notch is located on two sides of the first gate structure 115 having the target shape, where the notch may be a circular arc notch or a triangular notch, or may be other irregular notch, and the first gate structure 115 having the target shape has a shape with a top large bottom small.
The first gate structure 115 is etched according to a target shape, and dry etching may be used, wherein an etching gas used for the dry etching includes chlorine, oxygen, hydrogen bromide, and the like.
In the present embodiment, the following two steps are further included after step S113:
and step S114, forming side walls on two sides of the first grid structure with the target shape.
Specifically, referring to fig. 5, fig. 5 is a schematic diagram illustrating formation of a sidewall, a source region and a drain region of a semiconductor device. The sidewall 130 is disposed on the substrate 100 and formed on sidewalls of both sides of the first gate structure 115 having the target shape.
And step S115, forming a source region and a drain region in the substrate by using the first grid structure with the target shape and the side wall as masks.
Specifically, with continued reference to fig. 5, in the present embodiment, source region ion and drain region ion implantation is performed using the first gate structure 115 and the sidewall 130 having the target shape as masks, and an annealing process is performed to form the source region 140 and the drain region 150 in the substrate 100 under the first gate structure 115 and the sidewall 130 having the target shape, the source region 140 and the drain region 150 being located at both sides of the first gate structure 115 and the sidewall 130 having the target shape, respectively. In addition, in some embodiments, lightly doped regions 160 (Lightly Doped Drain, LDD) are also formed in the substrate 100 under the sidewalls 130.
And S12, covering a stress film on the substrate and the first gate structure with the target shape and performing stress treatment so that the stress film is matched with the first gate structure with the target shape to improve the stress of a channel region of the substrate under the first gate structure with the target shape.
In a specific implementation, referring to fig. 6, fig. 6 is a schematic view of a semiconductor device covered with a stress film, wherein the stress film 120 is formed along the second surface 112, the sidewall 130 surface and the substrate 100 surface of the first gate structure 115 having a target shape by covering the substrate 100 and the first gate structure 115 having a target shape with the stress film 120, wherein the stress film 120 may be formed by Deposition (DEP) and a stress treatment is performed during the Deposition of the stress film 120 such that the stress film 120, which is originally stress-free, has a tensile stress or a compressive stress, and the tensile stress or the compressive stress is conducted into the channel region along the first gate structure 115 having a target shape. The magnitude of the stress of the final channel region is related to the thickness of the stressed film 120, the shape of the first gate structure 115, and the height of the first gate structure 115. The stress film 120 may be silicon nitride and/or silicon oxynitride, etc., and the stress layer with a desired stress level may be realized by adjusting the ratio of nitrogen, silicon, etc. in the process gas during the deposition process to adjust the level of the specific stress.
Since the first surface 111 of the first gate structure 115 having the target shape is smaller in size, resulting in a smaller channel region in the substrate 100 under the first gate structure 115 having the target shape, when the stress treatment is performed, the first gate structure 115 having the target shape with a large top and a small bottom is matched with the stress film 120, so that the stress can be better conducted to the channel region, and the stress of the reduced channel region can be greatly improved.
And S13, removing the stress film on the second surface of the first grid structure with the target shape, and reserving residual stress films which cover the non-grid structure area of the substrate and two sides of the first grid structure with the target shape.
Specifically, referring to fig. 7 and 8, fig. 7 is a schematic view of a semiconductor device covering a first dielectric layer, fig. 8 is a schematic view of a semiconductor device after polishing in fig. 7, and step S13 includes:
and S131, covering a first dielectric layer on the stress film.
Specifically, referring to fig. 7, fig. 7 is a schematic view of a semiconductor device covering a first dielectric layer, in this embodiment, after forming a stress film 120, a first dielectric layer 171 is formed on a surface of the stress film 120, a thickness of the first dielectric layer 171 is at least not less than a thickness of a first gate structure 115 having a target shape, the first dielectric layer 171 may be formed by a deposition process, and the first dielectric layer 171 may be silicon dioxide or a compound of silicon and oxygen.
And step S132, grinding away part of the dielectric layer and part of the stress film until the second surface of the first grid structure with the target shape is exposed.
Specifically, referring to fig. 8, fig. 8 is a schematic diagram of the semiconductor device in fig. 7 after Polishing, in this embodiment, a CMP (CHEMICAL MECHANICAL Polishing) process is used to perform thinning and top planarization of the first gate structure 115 with the target shape, and the portion of the first dielectric layer 171 and the portion of the stress film 120 are polished away until the second surface 112 of the first gate structure 115 with the target shape is exposed, and stopping, the residual stress film 121 covering the region of the first gate structure 115 with the non-target shape and both sides of the first gate structure 115 with the target shape of the substrate 100 is retained, and the residual stress film 121 improves the stress of the reduced channel region.
In some embodiments, referring to fig. 9, fig. 9 is a schematic diagram of forming a gate contact plug of the semiconductor device in fig. 8, and after step S132, the manufacturing method further includes:
step S1330, forming a second dielectric layer on the remaining first dielectric layer, and forming a gate contact plug in the second dielectric layer, where the gate contact plug connects the first gate structure with the target shape, and the polysilicon gate in the first gate structure with the target shape is used as a gate.
Specifically, referring to fig. 9, fig. 9 is a schematic diagram of forming a gate contact plug in the semiconductor device in fig. 8, in this embodiment, a second dielectric layer 172 is formed on the remaining first dielectric layer 171, where the second dielectric layer 172 covers the first dielectric layer 171 and the first gate structure 115 with the target shape, where the second dielectric layer 172 may be formed by a deposition process, and further, the material of the second dielectric layer 172 and the material of the first dielectric layer 171 may be the same or different.
With continued reference to fig. 9, a gate contact plug 180 connected to the first gate structure 115 having the target shape is formed in the second dielectric layer 172, so as to implement interconnection between the first gate structure 115 having the target shape and other metal layers, and the gate contact plug 180 may be made of a conductive material such as tungsten or aluminum.
With continued reference to fig. 9, source-drain contact plugs 190 connecting the source region 140 and the drain region 150 are formed in the second dielectric layer 172, the first dielectric layer 171, and the stress film 120, and the source-drain contact plugs 190 include a source-region contact plug and a drain-region contact plug, so as to implement interconnection between the source region 140 and the drain region 150 and other metal layers, and the source-drain contact plugs 190 may be made of conductive materials such as tungsten, aluminum, and the like. That is, in the present embodiment, the polysilicon gate 113 is directly used as the gate. The first gate structure 115 having the target shape forms the gate structure 110 of the semiconductor device 10.
In other embodiments, referring to fig. 10 to 12, fig. 10 is a schematic view of removing polysilicon gate of the semiconductor device of fig. 8, fig. 11 is a schematic view of filling metal gate of the semiconductor device of fig. 10, and fig. 12 is a schematic view of forming gate contact plug of the semiconductor device of fig. 11. After step S132, the manufacturing method further includes:
And S1331, removing the polycrystalline silicon grid electrode in the first grid electrode structure with the target shape, and filling a metal grid electrode in the original area of the polycrystalline silicon grid electrode to form a second grid electrode structure.
Referring to fig. 10 and 11, fig. 10 is a schematic view of the semiconductor device of fig. 8 with the polysilicon gate removed, and fig. 11 is a schematic view of the semiconductor device of fig. 10 with the metal gate filled. The polysilicon gate 113 in the first gate structure 115 having the target shape is removed using a post gate process, and the removal operation may be performed using an etching process. Voids are formed in the region of the original polysilicon gate, as shown in fig. 10. As shown in fig. 11, the metal gate 117 is filled in the gap, and the metal gate 117 is formed by depositing a metal material in the gap, and the material of the metal gate 117 may be selected in consideration of the conductivity, thermal stability, and compatibility with a dielectric material. Generally, metals such as tungsten and aluminum are common options. The second gate structure 116 includes the metal gate 117 and the gate oxide 114 described above. In other embodiments, polysilicon gate 113 may be removed in other ways, such as chemical etching, reactive ion etching, or other dry etching, etc.
And S1332, forming a second dielectric layer on the residual first dielectric layer, and forming a gate contact plug connected with the metal gate in the second dielectric layer, wherein the metal gate is used as a gate.
Specifically, referring to fig. 12, fig. 12 is a schematic diagram of forming a gate contact plug in the semiconductor device of fig. 11, in this embodiment, a second dielectric layer 172 is formed on the remaining first dielectric layer 171, and the second dielectric layer 172 covers the first dielectric layer 171 and the second gate structure 116, where the second dielectric layer 172 may be formed by a deposition process, and the second dielectric layer 172 may be silicon dioxide or a compound of silicon and oxygen, and further, the material of the second dielectric layer 172 may be the same as or different from that of the first dielectric layer 171.
With continued reference to fig. 12, a gate contact plug 180 is formed in the second dielectric layer 172 to connect the second gate structure 116, so as to further interconnect the second gate structure 116 and other metal layers, where the gate contact plug 180 may be made of a conductive material such as tungsten or aluminum.
With continued reference to fig. 12, source-drain contact plugs 190 connecting the source region 140 and the drain region 150 are formed in the second dielectric layer 172, the first dielectric layer 171, and the stress film 120, and the source-drain contact plugs 190 include a source-region contact plug and a drain-region contact plug, so as to implement interconnection between the source region 140 and the drain region 150 and other metal layers, and the source-drain contact plugs 190 may be made of conductive materials such as tungsten, aluminum, and the like. In the present embodiment, the polysilicon gate 113 is used as a dummy gate, and the metal gate 117 is used as a subsequent actual gate. At this time, the second gate structure 116 forms the gate structure 110 of the semiconductor device 10. The gate structure 110 may further include a HK layer and a work function layer (not shown) between the metal gate 117 and the gate oxide 114, which are not described herein.
According to the manufacturing method of the semiconductor device 10 provided by the embodiment, the gate structure 110 is etched to form the gate structure 110 with the top large and the bottom small, and as the bottom of the gate structure 110 is smaller, when the stress treatment is performed, the gate structure 110 with the target shape is combined with the stress film 120, so that the stress can be more effectively conducted to the channel region through the gate structure 110, the stress of the reduced channel region is greatly improved, the device performance of the semiconductor device 10 can be effectively improved, and referring to fig. 9 and 12, the size of the first surface 111 of the gate structure 110 is etched smaller, and compared with the prior art, the channel region in the substrate 100 below the gate structure 110 is smaller. C= ≡a/d according to the capacitance formula. Where, ζ is the dielectric constant, A is the capacitance area, and d is the inter-electrode distance. When the gate structure 110 has a shape with a large top and a small bottom, the distance between the gate and the drain 150 becomes larger, the capacitance becomes smaller correspondingly, and the problem of overlap capacitance caused by the size shrinkage is reduced, so that the device performance of the semiconductor device 10 is further improved.
Further, in order to solve the above-described problems, a second aspect of the present application provides a semiconductor device 10. See, in particular, fig. 9 and 12. The semiconductor device 10 includes a substrate 100, a gate structure 110 having a target shape, and is disposed on the substrate 100. The gate structure 110 has at least a first surface 111 and a second surface 112, wherein the first surface 111 is a surface of the gate structure 110 contacting the substrate 100, the second surface 112 is opposite to the first surface 111, and the second surface 112 is a surface of the gate structure 110 away from the substrate 100. The target shape includes a first surface 111 of the gate structure 110 near the substrate 100 having a smaller dimension than a second surface 112 of the gate structure 110 far from the substrate 100, the first surface 111 being opposite to the second surface 112, and a residual stress film 121 covering a non-gate structure 110 region of the substrate 100 and covering both sides of the gate structure 110, the residual stress film 121 being combined with the gate structure 110 to facilitate retention of stress in a channel region under the gate structure 110, improving carrier mobility and thus performance of the semiconductor device 10.
In some embodiments, referring to fig. 4, the width of the gate structure 110 gradually decreases along the direction approaching the substrate 100, as shown in fig. 4 (a), or the first surface 111 of the gate structure 110 has a notch with respect to the second surface 112, as shown in fig. 4 (b), where the notch may be a circular arc notch or a triangular notch, or may be any other irregular notch, as long as the gate structure 110 can have a shape with a top large and a bottom small.
In some embodiments, the gate structure 110 includes a gate and a gate oxide 114, and in particular, the gate oxide 114 may be silicon oxide or the like, with the gate oxide 114 being located between the gate and the substrate 100. The first surface 111 of the gate structure 110 is a surface of the gate oxide layer 114 close to the substrate 100, the second surface 112 of the gate structure 110 is a surface of the gate away from the substrate 100, and the second surface 112 is opposite to the first surface 111.
In some embodiments, the gate includes a polysilicon gate 113 or a metal gate 117.
The semiconductor device 10 provided in this embodiment is formed by forming the gate structure 110 of the target shape on the substrate 100, wherein the size of the first surface 111 of the gate structure 110 close to the substrate 100 is smaller than the size of the second surface 112 of the gate structure 110 far from the substrate 100. And the residual stress film 121 is covered on the non-gate structure 110 region of the substrate 100 and both sides of the gate structure 110. The residual stress film 121 cooperates with the gate structure 110 to greatly improve the stress of the reduced channel region, and as the bottom of the gate structure 110 becomes smaller, the distance between the gate and the drain region 150 becomes larger, the gate-drain capacitance becomes further smaller, and the overlap capacitance is improved.
It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411657900.3A CN119521701A (en) | 2024-11-19 | 2024-11-19 | Semiconductor device manufacturing method and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411657900.3A CN119521701A (en) | 2024-11-19 | 2024-11-19 | Semiconductor device manufacturing method and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119521701A true CN119521701A (en) | 2025-02-25 |
Family
ID=94659394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411657900.3A Pending CN119521701A (en) | 2024-11-19 | 2024-11-19 | Semiconductor device manufacturing method and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119521701A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070224745A1 (en) * | 2006-03-21 | 2007-09-27 | Hui-Chen Chang | Semiconductor device and fabricating method thereof |
| JP2008053587A (en) * | 2006-08-28 | 2008-03-06 | Renesas Technology Corp | Semiconductor device manufacturing method |
| US20080261408A1 (en) * | 2007-04-23 | 2008-10-23 | Advanced Micro Devices, Inc. | Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors |
| US20110079854A1 (en) * | 2009-10-02 | 2011-04-07 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| WO2013026243A1 (en) * | 2011-08-19 | 2013-02-28 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN109309121A (en) * | 2017-07-26 | 2019-02-05 | 比亚迪股份有限公司 | Semiconductor power device and preparation method thereof |
-
2024
- 2024-11-19 CN CN202411657900.3A patent/CN119521701A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070224745A1 (en) * | 2006-03-21 | 2007-09-27 | Hui-Chen Chang | Semiconductor device and fabricating method thereof |
| JP2008053587A (en) * | 2006-08-28 | 2008-03-06 | Renesas Technology Corp | Semiconductor device manufacturing method |
| US20080261408A1 (en) * | 2007-04-23 | 2008-10-23 | Advanced Micro Devices, Inc. | Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors |
| US20110079854A1 (en) * | 2009-10-02 | 2011-04-07 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| WO2013026243A1 (en) * | 2011-08-19 | 2013-02-28 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN109309121A (en) * | 2017-07-26 | 2019-02-05 | 比亚迪股份有限公司 | Semiconductor power device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7972914B2 (en) | Semiconductor device with FinFET and method of fabricating the same | |
| US7488650B2 (en) | Method of forming trench-gate electrode for FinFET device | |
| CN102456579B (en) | Semiconductor device having localized extremely thin silicon on insulator channel region | |
| US7399679B2 (en) | Narrow width effect improvement with photoresist plug process and STI corner ion implantation | |
| US7560759B2 (en) | Semiconductor device and method of manufacturing the same | |
| US20200105581A1 (en) | Semiconductor device and manufacturing method thereof | |
| US8962430B2 (en) | Method for the formation of a protective dual liner for a shallow trench isolation structure | |
| KR100498476B1 (en) | MOSFET having recessed channel and fabricating method thereof | |
| CN110517989A (en) | Semiconductor structure and forming method thereof | |
| WO2013152535A1 (en) | Preparation method for finfet in large-scale integrated circuit | |
| CN112151376B (en) | Semiconductor structure and forming method thereof | |
| US9337350B2 (en) | Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same | |
| CN110634798A (en) | Semiconductor structure and method of forming the same | |
| CN104425373A (en) | Method for forming CMOS structure | |
| US20070170511A1 (en) | Method for fabricating a recessed-gate mos transistor device | |
| CN111816562A (en) | Semiconductor structure and method of forming the same | |
| US20090256207A1 (en) | Finfet devices from bulk semiconductor and methods for manufacturing the same | |
| CN106298526B (en) | The production method of silicon field-effect transistor device on quasi-insulator | |
| CN113517290A (en) | Semiconductor element and method for manufacturing the same | |
| CN101465373B (en) | Semiconductor device and method for manufacturing the device | |
| CN109003899A (en) | The forming method of semiconductor structure and forming method thereof, fin formula field effect transistor | |
| CN119521701A (en) | Semiconductor device manufacturing method and semiconductor device | |
| CN113838934B (en) | Semiconductor structure and forming method thereof | |
| CN112582471B (en) | Semiconductor device and forming method | |
| US7179713B2 (en) | Method of fabricating a fin transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |