CN119536614A

CN119536614A - An IMA system and method for realizing deterministic large-capacity high-speed storage

Info

Publication number: CN119536614A
Application number: CN202311092730.4A
Authority: CN
Inventors: 刘源; 李军; 刘峥嵘; 吴智敏
Original assignee: Avic General Electric Civil Avionics System Co ltd
Current assignee: Avic General Electric Civil Avionics System Co ltd
Priority date: 2023-08-28
Filing date: 2023-08-28
Publication date: 2025-02-28

Abstract

The invention relates to a comprehensive modularized avionics IMA system which comprises a main computing module, a storage module and a hardware resource, wherein the main computing module comprises a plurality of IMA partitions, each IMA partition comprises an application, the hardware resource comprises a processor and a memory, the storage module is configured outside the main computing module and is communicatively coupled with the main computing module, and the memory of the main computing module and the storage module form memory mapping, so that the operation of the main computing module on the memory can cause the storage module to execute corresponding operation.

Description

IMA system and method for realizing deterministic high-capacity high-speed storage

Technical Field

The present invention relates generally to Integrated Modular Avionics (IMA) systems and, more particularly, to an IMA system that enables deterministic mass high-speed storage and a method of enabling deterministic mass high-speed storage in an IMA system.

Background

Avionics systems have undergone a process of development from discrete, joint, comprehensive to highly comprehensive since their birth, ranging from independent of each other to the adoption of modular, highly comprehensive hierarchical architectures. The comprehensive and modularized avionic (INTEGRATED MODULAR AVIONICS, IMA) system architecture is a mainstream architecture model of the current avionic system, and a complex avionic system is built by adopting a reconfigurable universal module, so that the usability of the system is improved, the robustness of the system is improved, and the volume, the power consumption and the total life cycle cost of the system are greatly reduced. The design concept of the standardized module puts new requirements on the avionics system, namely, the design of software needs to meet ARINC 653 standard.

With the rapid development of avionics technology, resolution and sampling rate are greatly improved, so that high-speed storage and reading and writing requirements of large-capacity data are brought. Based on the current market storage technology, NAND FLASH is generally considered as a storage medium when considering the storage and read-write requirements of large files. However, NAND FLASH-based storage systems may have the following problems when operating in an ARINC 653-based system:

1. Writing, erasing and other operations are performed on NAND FLASH, and the certainty and the integrity of partition operation based on ARINC 653 standard are affected due to the characteristics of buses and Flash;

2, the NAND Flash has bad block problem, and the block handling required to be performed during bad block management and normal programming also affects the time of each operation, so as to cause uncertainty of ARINC 653 partition operation;

3. Direct operation and maintenance NAND FLASH in the ARINC 653 partition may cause congestion by waiting for a completion response of NAND FLASH, thereby affecting the operational efficiency of the ARINC 653 system.

The article "design of an onboard high-safety high-reliability data storage module" published in journal "electro-optic and control" describes a design of NAND FLASH-based data storage in an IMA system. Specifically, fig. 1 shows a schematic diagram of a system architecture of an on-board high-security high-reliability data storage module. The IMA calculation module 102 may, for example, conform to the ARINC 653 standard. The IMA computing module 103 may include multiple partitions, such as partition 1 104a, partition 2 104b, partition n 104 n. Each partition may include an application. These applications may constitute the application layer of the IMA calculation module 102. The various partitions are in the user mode 104 of the IMA core computing module 102. The IMA computing module 102 may also include an operating system layer 108, a module support layer 112, and an OEM hardware platform layer 116, which are in the kernel mode 106 of the IMA computing module 102. NAND FLASH 118 resides in the OEM hardware platform layer 116. Included in the module support layer 112 is a Flash driver 114, which is the bottommost driver that directly operates the OEM hardware chip. The operating system layer 108 includes FlashFX layers 110 that may be used, for example, to implement bad block management and wear leveling of NAND FLASH, and the like.

However, this design does not address the deterministic and high integrity issues of NAND FLASH-based storage systems when operating in an IMA system based on the ARINC 653 standard. In addition, the design operates and maintains NAND FLASH directly in the system partition, so as described above, this situation may be blocked by waiting for the completion response of Flash, which may seriously affect the operation efficiency of the system.

Disclosure of Invention

Some embodiments of the invention relate to an integrated modular avionics IMA system comprising a host computing module including a plurality of IMA partitions, each IMA partition including an application, a hardware resource including a processor and memory, and a storage module configured external to and communicatively coupled with the host computing module, wherein the memory of the host computing module and the storage module form a memory map such that operations performed by the host computing module on its memory can cause the storage module to perform corresponding operations.

Some embodiments of the invention relate to a method for integrating memory operations of a modular avionics IMA system comprising sending, by an application in a partition of a host computing module, an operation request to a memory of the host computing module, the operation request causing a change in the memory of the host computing module, detecting, by a memory module in communication with and external to the host computing module, a corresponding change in the memory of the memory module, wherein the memory of the host computing module and the memory module form a memory map, and performing, by the memory module, a corresponding operation on a flash memory mounted on the memory module in response to the change in the memory thereof.

Some embodiments of the invention relate to a method for integrating memory operations of a modular avionics IMA system comprising scanning, by a memory module external to a host computing module of the IMA system, memory of the memory module to obtain operation requests from a memory map of the host computing module in the memory of the memory module, and performing, by the memory module, corresponding operations on a flash memory mounted on the memory module in response to detecting the operation requests of the memory module.

Some embodiments of the invention relate to a machine-readable storage medium having stored thereon instructions which, when executed, cause an integrated modular avionics IMA system to perform a method as set out in any one of the above methods.

Some embodiments of the invention relate to an integrated modular avionics IMA system comprising means for performing a method as set out in any one of the methods above.

Drawings

To further clarify the features and advantages of the various embodiments of the present invention, a more particular description of the preferred embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope.

In addition, the main connection relationships or relative positional relationships of the individual components are shown in the drawings, not all of them, and the individual components and connections in the drawings are not necessarily drawn to scale in practice.

Fig. 1 shows a block diagram of a typical IMA computation module based on NAND FLASH.

Fig. 2 shows a schematic diagram of an IMA system capable of deterministic high-speed storage according to an embodiment of the invention.

Fig. 3 shows a schematic diagram of details between the IMA host computing module in fig. 2 and a storage module residing outside thereof, according to an embodiment of the invention.

FIG. 4 shows a timing diagram of a master computing module and a memory module block according to an embodiment of the invention.

Fig. 5 illustrates a method of implementing deterministic high-speed storage in an IMA system according to an embodiment of the present invention.

Fig. 6 illustrates another method of implementing deterministic high-speed storage in an IMA system according to an embodiment of the present invention.

Fig. 7 illustrates a machine-readable medium according to an embodiment of the invention.

Detailed Description

The following detailed description refers to the accompanying drawings. The drawings show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. It should be understood that the following specific examples are intended to be illustrative of exemplary embodiments and are not to be construed as limiting the invention, and that appropriate modifications and adaptations to the disclosed embodiments may be made by those skilled in the art without departing from the spirit and scope of the claimed subject matter.

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. It will be apparent, however, to one skilled in the art that the various embodiments described may be practiced without these specific details. In other instances, well-known structures have not been described in detail so as not to unnecessarily obscure aspects of the embodiments. Unless defined otherwise, terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

IMA architecture is widely used by avionics systems of aircraft. The IMA architecture is a hierarchical architecture in which the reliability of the overall system operation is ensured by partitioning (partition) for the program portion including code and data.

Spatial partitioning is to ensure that applications in a partition cannot write to memory or data of applications running on different partitions. Each partition is isolated from each other by an isolation mechanism such that each partition has independent memory space, is able to independently use the processing resources of the IMA computation module, and has independent running contexts, i.e., each partition's data and its operations are independent of each other.

Time partitioning is to ensure that activity in one partition does not affect the timing of activity in other partitions. In a system conforming to the ARINC 653 standard, time partitioning is ensured by a fixed, cycle-based schedule. The operating system maintains a fixed duration main time frame (MAF) that is periodically repeated during runtime operation of the module. The partition is activated by allocating one or more partition windows within this primary time frame. The order of partition activation is defined offline at configuration time using a configuration table. This provides a deterministic scheduling method because the partitions are equipped with a predefined amount of time to access the processor resources.

Flash Memory (Flash Memory) with rapid development is gradually becoming a design and usage scheme for many Memory systems due to its small size, low cost, low power consumption, long life, vibration resistance, and wide temperature application range. The current Flash chip is mainly divided into NOR Flash and NAND FLASH. The NOR Flash has the advantages of high reliability, high random reading speed and the like. NAND FLASH is a linear storage device suitable for the storage of large volumes of data and files. Therefore NAND FLASH is widely used in the development of high-capacity high-speed memory devices.

NAND FLASH employs a nonlinear macro cell mode, reads and writes data in units of pages, erases data in units of blocks, and must erase data before writing. NAND FLASH chips have the advantages of large storage capacity, high writing speed and the like, and meanwhile, have the problems of bit flipping, limited service life, bad blocks and the like. NAND FLASH the chip is shipped from the factory, and bad blocks are randomly distributed in the chip, wherein a bad block means that one or more data units contained in one block cannot be operated, and new bad blocks are inevitably added in the long-term use process of the chip. Erase and program operations are not allowed for bad blocks, as this can result in storage errors of the data.

The safety of avionics systems is important. For high security considerations for avionics systems, it is desirable to ensure high certainty of partition operation in an IMA system. One aspect of the deterministic requirements of an IMA system is that the timing of the partition application is deterministic. However, due to the above-described characteristics of NAND FLASH (e.g., including bad blocks, etc.), NAND FLASH-based storage systems may affect the certainty and integrity of the avionics system when operated in an avionics system based on the ARINC 653 standard, and thus, corresponding measures may need to be taken to ensure the certainty and integrity of the avionics system, and in addition, the operational efficiency of the avionics system may be affected by some of the characteristics of NAND FLASH.

Based on the characteristics of the IMA system architecture and NAND FLASH, the invention designs a deterministic high-capacity high-speed storage system based on an ARINC 653 operating system. The system designed by the invention can perform the rapid memory operation of large-capacity data on the premise of meeting the integrity and certainty of the ARINC 653 system, and can improve the operation efficiency of the system. The following detailed description will be given with reference to the accompanying drawings.

Fig. 2 shows a schematic diagram of an IMA system capable of deterministic high-speed storage according to an embodiment of the invention. As shown in fig. 2, the inventive solution designs the storage module 206 to reside outside the IMA host computing module 202.

In a particular exemplary embodiment, the IMA host computing module 202 may, for example, run the ARINC 653 operating system. The IMA host computing module 202 may communicate via a bus 204 with a storage module 206 residing external thereto. A suitable bus may be employed to communicatively couple the IMA host computing module 202 with a storage module 206 residing external thereto. In a preferred embodiment of the present invention, bus 204 may comprise a PCIE (PCI-Express, PERIPHERAL COMPONENT INTERCONNECT EXPRESS) bus, which may be used to enable efficient, fast communication between host computing module 202 and memory module 206. To enable such communication with the storage module 206, the IMA host computing module 202 may include drivers and interfaces associated with the external storage module 206.

In a specific and preferred embodiment of the present invention, the memory module 206 may be implemented as an MCU (Microcontroller Unit, micro-control unit). In this embodiment, the memory module 206 may include the basic structure or circuitry of the MCU, however, for simplicity and convenience of description, only portions associated with memory operations are shown herein and in the drawings. The scheme of the present invention places the storage medium, including Flash (Flash), and all underlying operations on Flash-mounted storage module 206. The main computing module 202 only needs to perform memory operations specific to itself when the memory operations are needed, and the rest of the bottom memory operations can be completed by the storage module 206. The storage module 206 may be plugged into the IMA host computing module 202 as stand-alone hardware.

The storage module 206 may be configured to execute a storage program to read a memory operation request of the host computing module 202 and to perform related operations on Flash based on the request when needed, as described in more detail below.

Fig. 3 shows a schematic diagram of details between the IMA host computing module 202 in fig. 2 and a storage module 206 residing outside thereof, according to an embodiment of the invention. The IMA host computing module 202 may include multiple partitions, e.g., partition 1 208a, partition 2 208b, partition n 208n. Wherein each of the partitions 208a-208n is in a user mode of the IMA host computing module 202. Each partition may include a respective application. The respective applications of the partitions may constitute an application layer of the IMA host computing module 202. As described above, the various partitions 208a, 208b, & gt, 208n are isolated from each other by an isolation mechanism. The partitions being isolated from each other means that each partition can be allocated a separate memory space for the IMA host computing module 202 and each partition monopolizes the timing of the processing resources (e.g., processors) of the IMA host computing module 202, while the operating environment (e.g., operating system) and operating context of the applications within the partition can also be independent of each other. The isolation mechanism of such partitions of the IMA host computing module 202 ensures the stability and reliability of operation of the IMA host computing module 202 and the overall avionics system.

The IMA host computing module 202 may also include a module support layer. The module support layer is in kernel mode of the IMA host computing module 202. The module support layer may include storage system kernel drivers 212 and some hardware resources, including processing resources (not shown), host computer memory 214, and input/output (I/O) resources. The input output resources may include the necessary communication configuration, such as interfaces and the like. In one embodiment, the communication configuration may include PCIE and DMA (Direct Memory Access ) 216 configurations. PCIE and DMA (preferably QDMA, quick DMA) configurations may enable high-speed communication of large data between the IMA host computing module 202 and the storage module 206.

Applications in each of the partitions 208a-208n can manage and schedule host computer memory 214 at the module support layer through storage system interface 218. In one embodiment, storage system interface 218 may be an API (Application Programming Interface ).

In an embodiment of the invention, the memory 214 of the IMA host computing module 202 may be configured as a memory map of the storage module 206, with the storage module 206 external to the IMA host computing module 202. In other words, the operation of the IMA host computing module 202 with its memory 214 may be synchronized to the memory 220 of the storage module 206 residing external to the IMA host computing module 202. The IMA host computing module 202 may form a memory map for the storage module 206 through PCIE and DMA configurations, so that data mapping between the memory 220 of the storage module 206 and the memory 214 of the host computing module 202 may be implemented at high speed, and operations of the IMA host computing module 202 on the memory 214 thereof may be synchronously mapped to the memory 220 of the storage module 206 at high speed. More specifically, a memory map may be formed by the memory system kernel driver 212 of the IMA host computing module 202 to the "flash shadow" area 220 of the memory module 206 via PCIE and DMA configuration.

Also shown in fig. 3 is a separate storage module 206 residing outside of the IMA host computing module 202. Storage module 206 may include control logic 224, memory 220, and Flash 222.

As described in connection with fig. 2, the storage module 206 may be implemented as an MCU. The MCU 206 may be mounted with a flash memory (preferably NAND flash memory or NAND FLASH) 222.MCU 206 may also include MCU memory 220. The MCU memory 220 may be configured as a shadow of NAND FLASH 222,222, i.e., the MCU memory 220 may be a logical mapping of NAND FLASH 222,222. MCU memory 220 may have NAND FLASH data 222.

In the present invention, the memory map formed by the memory 214 of the main computing module 202 and the storage module 206 may be a full flash map or a partition-based partial map (e.g., a map of partition flash memory at each partition switch). In the preferred embodiment of the invention, a full flash mapping mode can be adopted, and the certainty and the working efficiency of the system can be ensured.

With full flash mapping, when the storage module 206 is initialized, such as by power up, the storage module 206 may read all NAND FLASH of the data into the memory 220 of the storage module 206, such that the memory 220 of the storage module 206 forms a region that may be referred to as a "flash shadow". Furthermore, as described above, the memory 214 of the IMA host computing module 202 may map, and preferably fully map, the memory (i.e., flash shadow) 220 of the storage module 206 via the PCIE and DMA interfaces. Thus, the memory 214 of the IMA host computing module 202 may have all of its data at NAND FLASH's 222 external thereto. The memory 220 of the storage module 206 is capable of mapping out the operations or changes to the memory 214 by the partitioned application of the IMA host computing module 202. If desired, control logic 224 of storage module 206 may further perform the associated operations on NAND FLASH 222,222 based on the changes to memory 220.

The control logic 224 of the storage module 206 may be configured to execute a program to detect whether there is a change in its memory 220 (flash shadow) that reflects a memory operation request from the host computing module 202. Preferably, the control logic 222 of the storage module 206 may be configured to cyclically scan for changes in its memory (flash shadow) 220 to detect whether there is an operation request from the host computing module 202. The control logic 224 of the storage module 206 may be further configured to operate NAND FLASH on the change in memory (flash shadow) 220 accordingly if such a change is detected. In addition, the control logic 224 of the memory module 206 may be further configured to perform other underlying operations related to the flash memory, such as flash memory maintenance operations, flash memory block management, data integrity processing (e.g., verification), and the like. In one particular embodiment, flash block management may include NAND FLASH initializing full data read maps, data status polling, read and write operations, etc., and flash maintenance may include NAND FLASH bad block management, data erasure maintenance handling, and other NAND FLASH general maintenance functions. Thus, in an embodiment of the invention, all underlying operations on NAND FLASH 222,222 can be performed outside the IMA host computing module 202 by the separate storage module 206. The underlying operations may include reading, writing, erasing, etc. to NAND FLASH 222,222 in the memory module 206. In addition, the underlying operations may also include additional underlying operations associated with flash maintenance as described above.

In a preferred embodiment, control logic 224 of storage module 206 may be configured to cyclically execute one or more of scanning memory 220, operating Flash222, and performing additional underlying operations on Flash222, in response to instructions stored in storage module 206.

The corresponding application in each partition on the IMA host computing module 202 may access the associated host computer memory 214, for example, by calling if a memory operation is required (i.e., to operate NAND FLASH 222,222 in the storage module 206). The host computer memory 214 may be changed accordingly to reflect the operational request of a particular application. Correspondingly, the memory 220 of the storage module 206 may reflect such changes in the host computer memory 214, such that the storage module 206 may receive a request from the IMA host computing module 202 for an operation on NAND FLASH 222 by a particular application and perform the operation on NAND FLASH according to the received operation request. As an example embodiment, a partition application of the IMA host computing module 202 may perform a write operation to the host computer memory 214. Since memory mapping may be performed over bus 204, this change in write operation of host computer memory 214 may be synchronized to memory 220 of storage module 206. The storage module 206 may detect a change in its memory 220 (i.e., receive a write request) and further perform a write operation to NAND FLASH 222,222 based on this change. For example, the storage module 206 may perform a write operation to NAND FLASH 222 based on the NAND FLASH storage management table.

In an embodiment of the invention, the storage module 206 may run in parallel with the IMA host computing module 202. Applications in the partition of the IMA host computing module 202 need only operate directly on their internal host computer memory 214, and need not operate directly on their external NAND FLASH. After the application in the partition of the IMA host computing module 202 finishes the relevant operation on the host computer memory 214, the next instruction may continue to execute without blocking wait NAND FLASH to reply or wait NAND FLASH for the operation to complete. Thus, in the inventive approach, the IMA host computing module 202 no longer needs to allocate overhead for operation, maintenance, and management of NAND FLASH. Compared with the prior art, the scheme of the invention greatly improves the system operation efficiency.

Furthermore, in the present approach, NAND FLASH operations affecting certainty and integrity are all completed on the storage module 206, and the system only needs to configure the partition with enough time windows for accessing the host computer memory 214, without waiting for NAND FLASH reaction or reply, which makes the memory operations (e.g., read, write, erase, etc.) of different partition applications of the IMA host computing module 202 or the time spent by different memory operations of the same application substantially consistent and deterministic, thereby improving the certainty of the avionics system. In the case of NAND FLASH being provided within the main computing module, however, due to the nature of NAND FLASH (e.g., the presence of bad blocks, etc.), the time spent for each memory operation (e.g., write operation) may be different or not be completed within a preset time threshold, thereby affecting the certainty of the system.

Embodiments of the present invention are described primarily in conjunction with NAND FLASH. NOR Flash may also be used in cases where data capacity requirements are not high. The capacity of NOR Flash is small compared to NAND FLASH. Furthermore, NOR Flash is limited under a particular architecture by, for example, the CPU bus. Thus, the present invention preferably uses NAND FLASH to enable large capacity data storage while being less limited by the system.

FIG. 4 shows a timing diagram of a host computing module and a memory module according to an embodiment of the invention. Timing 410 indicates a timing diagram example of the master computing module 402. The master computing module 402 may be the IMA master computing module 202 of fig. 2 or 3. Timing 420 indicates a timing diagram associated with the operation of memory module 406. The storage module 406 may be the storage module 206 of fig. 2 or 3.

Timing 410 illustrates two memory operations of partition application 412 of main computing module 402. Partition application 412 may be a corresponding application in any of partition 1, partition 2, partition n of fig. 3. Both memory operations of partition application 412 continue to execute application instructions after operating the memory of main computing module 402 (e.g., host computer memory 214 of FIG. 3) without waiting for a NAND FLASH reply on storage module 406 or for NAND FLASH operations to complete. The storage module 406, upon receiving a memory operation request from the host computing module 402, may perform the requested memory operation in parallel with the operations performed by the host computing module 402.

In an embodiment of the present invention, because PCIE and DMA may be employed to enable communication between the IMA host computing module 402 and its external storage module 406 as described above, operations of the host computing module 402 to its memory (e.g., host computer memory 214) may be quickly mapped to the memory (e.g., memory 220) of the storage module 406. Thus, the storage module 406 may receive the request for an operation to memory substantially at the same time as the partition application 412 of the main computing module 402 requests the operation, or only after a very short time interval. In a read operation of the IMA host computing module 402 to the storage module 406, only the memory mapped region (e.g., host computer memory 214 in FIG. 3) on the host computing module 402 needs to be read directly, and the operating time is only affected by the rate at which the memory (e.g., DDR) is read, and is therefore negligible. In the writing operation of the IMA host computing module 402 to the storage module 406, the writing speed of DDR and the PCIE transmission speed are mainly affected. Wherein the PCIE transmission rate occupies a relatively large area. Taking the LS1046A CPU as an example, for example, the PCIE 3.0/LANE1 configuration is used, and the transmission rate can reach 984.6MB/s. Therefore, the design of the invention can complete rapid read-write operation.

Timing diagram 410 illustrates two memory operations of one of the partition applications of the main computing module 402, and accordingly, timing diagram 520 illustrates two flash operations performed by the memory module 406 corresponding thereto. However, it should be understood that this is by way of example only and not limitation, and that the main computing module 402 and the storage module 406 may each perform more operations. In addition, the host computing module 402 may continue to execute instructions other than the store instruction after performing operations on its memory without waiting for a reply from the flash memory on the storage module 406.

In the conventional NAND FLASH-resident approach to the main computing module, the partition application of the main computing module, after issuing a memory operation request, needs to wait for the memory operation to NAND FLASH to complete before proceeding with the next instruction. While it can be seen from fig. 5 that in an embodiment of the present invention, operations on NAND FLASH may be performed independently by the storage module 406, the main computing module 402 may be executed in parallel with the storage module 406. Thus, as described above, this not only greatly improves the operating efficiency of the system, but also improves the certainty and integrity of the system operation.

Fig. 5 illustrates a method 500 of implementing deterministic high-speed memory operation in an IMA system according to an embodiment of the invention. The method 500 may be performed in an IMA system. Method 500 includes, at step 502, sending, by an application in a partition of a host computing module, an operation request to a memory of the host computing module, causing the memory of the host computing module to change based on the request.

The method 500 further includes, at step 504, a memory module in communication with and external to the host computing module detecting a corresponding change in memory of the memory module, wherein the memory of the host computing module forms a memory map to the memory module. The memory of the main computing module may form a memory map to the memory of the storage module through PCIE and DMA configuration.

In one embodiment, the memory module may be implemented as a micro control unit MCU. The MCU may include MCU memory and flash memory. The MCU memory and the flash memory may be communicatively coupled, and the memory of the main computing module is configured to map the MCU memory. The mapping may be a full mapping or a partition-based mapping. In a preferred embodiment, full mapping may be employed. In one embodiment, the data of the flash memory may be read into the MCU memory entirely when the storage module is initialized, such that the MCU memory is configured as a flash shadow. Furthermore, since the memory of the main computing module is configured to fully map the MCU memory, the memory of the main computing module may have all data of the flash memory, and the operation of the main computing module on its own memory may be quickly mapped to the MCU memory, so that the control logic of the MCU may implement the memory operation desired by the main computing module based on the changes in the MCU memory.

In a preferred embodiment, step 504 may include the storage module cyclically scanning its memory and timely retrieving memory mapped operation requests from the master computing module in its memory.

The method 500 may further include, at step 506, the memory module performing a corresponding operation on a flash memory mounted on the memory module in response to a change in its memory. In some embodiments, the operation may be an underlying operation on the flash memory, including reading, writing, erasing, etc. In additional embodiments, the method 500 may include the storage module further performing an underlying operation of one or more of flash block management, flash maintenance, data integrity processing.

Fig. 6 illustrates another method of implementing deterministic high-speed memory operation in an IMA system according to an embodiment of the present invention. The method 600 may be performed by a storage module external to a host computing module of an IMA system. The method 600 may include, at step 602, scanning, by a storage module external to a master computing module of the IMA system, memory of the storage module to obtain memory operation requests from a memory map of the master computing module in the memory of the storage module. The memory of the main computing module may form a memory map to the memory of the storage module through PCIE and DMA configuration.

In a preferred embodiment, step 602 may include the storage module cyclically scanning its memory and timely retrieving memory mapped operation requests from the master computing module in its memory.

The method 600 may further include, at step 604, performing, by the storage module, a corresponding operation on a flash memory installed on the storage module in response to detecting an operation request for a memory of the storage module. In some embodiments, the operation may be an underlying operation on the flash memory, including reading, writing, erasing, etc. In additional embodiments, the method 600 may include the storage module further performing an underlying operation of one or more of flash block management, flash maintenance, data integrity processing.

In either method 500 or 600, the host computing module and the storage module may run in parallel. Further, applications within a partition of the IMA system may continue to execute the next instruction after ending operations on the memory of the host computing module without waiting for a reply to the flash memory residing on the storage module.

The invention also provides a machine readable medium. Fig. 7 illustrates a machine-readable medium 700 according to an embodiment of the invention. The machine-readable medium 700 may include instructions 710. The instructions 710, when executed, may cause the method 500 or 600 of deterministic high-speed memory operation to be implemented in an IMA system.

Thus, as can be seen from the above description of the embodiments of the present invention, the technical solution of the present invention has the following advantages over the prior art:

The certainty and the integrity are high, namely the ARINC 653 system partition application only needs to operate the relevant memory mapping area in the main computing module, and NAND FLASH operations affecting the certainty and the integrity are completed on the storage module. The ARINC 653 system only needs to configure the partition with enough time window for accessing the memory. Thus, the certainty and integrity of the system are greatly improved;

The ARINC 653 system in the main calculation module does not need to allocate the overhead for operation, maintenance and management of NAND FLASH, so that the system operation efficiency is improved;

The maintainability is strong, namely, the storage module is connected with the main computing module by using the PCIE interface, so that the data maintenance and the hardware replacement can be easily carried out by plugging;

the method has strong expandability, and the memory mapping operation of the NAND FLASH by the main computing module can be easily and flexibly packaged and built on the memory frames such as file systems.

Appropriate modifications and adaptations of the embodiments specifically described above may be made by those skilled in the art without departing from the spirit and scope of the present invention. It is intended, therefore, that the claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may also include all implementations falling within the scope of the appended claims, and equivalents thereof.

Some examples of the invention are shown below:

example 1. An integrated modular avionics IMA system, comprising:

A master computing module, the master computing module comprising:

a plurality of IMA partitions, wherein each IMA partition comprises an application;

Hardware resources including a processor and a memory;

A storage module configured external to and communicatively coupled with the host computing module,

The memory of the main computing module and the memory module form memory mapping, so that the operation of the main computing module on the memory can cause the memory module to execute corresponding operation.

Example 2. The IMA system of example 1, the master computing module and the storage module configured to be capable of running in parallel.

Example 3 the IMA system of any of the above examples, the storage module implemented as a micro control unit MCU, the MCU including MCU memory and flash memory, the MCU memory communicatively coupled with the flash memory, and

Wherein the memory of the master computing module is configured to map the MCU memory.

Example 4. An IMA system according to any one of the preceding examples, the storage module being configured to, when initialized, read all data of the flash memory into the MCU memory such that the MCU memory is configured as a flash shadow and the memory of the master computing module is configured to fully map the MCU memory.

Example 5 an IMA system according to any one of the preceding examples, the MCU comprising control logic configured to cyclically scan the MCU memory to obtain operation requests from the memory map of the master computing module in the MCU memory and to perform corresponding operations on the flash memory in accordance with the operation requests.

Example 6 an IMA system according to any one of the preceding examples, the host computing module being configured to enable an application within the IMA partition to continue executing a next instruction after ending an operation on memory of the host computing module without waiting for a reply to the flash memory of the storage module.

Example 7. The IMA system of any one of the above examples, the flash memory comprising a NAND flash memory.

Example 8. The IMA system of any one of the above examples, the master computing module being configured to communicate with the storage module over a PCIE bus and QDMA.

Example 9. An IMA system of any one of the above examples, the operations comprising reading, writing, erasing.

Example 10. An IMA system according to any one of the preceding examples, the storage module further configured to perform underlying operations including one or more of flash block management, flash maintenance, data integrity processing.

Example 11. A method for integrating memory operations of a modular avionics IMA system, comprising:

Transmitting an operation request to a memory of a main computing module by an application in a partition of the main computing module, wherein the operation request causes the memory of the main computing module to change;

A memory module in communication with and external to the host computing module detects a corresponding change in memory of the memory module, wherein the memory of the host computing module and the memory module form a memory map, and

And responding to the change of the memory by the storage module, and executing corresponding operation on the flash memory installed on the storage module.

Example 12. A method for integrating memory operations of a modular avionics IMA system, comprising:

scanning the memory of a memory module located outside the host computing module of the IMA system by the memory module to obtain an operation request of the memory mapping from the host computing module in the memory of the memory module, and

And responding to the detection of the operation request of the memory of the storage module by the storage module, and executing corresponding operation on the flash memory installed on the storage module.

Example 13. The method of any of the above examples, the host computing module and the storage module configured to be capable of running in parallel.

Example 14. The method of any of the above examples, the memory module is implemented as a micro control unit, MCU, the MCU including MCU memory and flash memory, the MCU memory communicatively coupled with the flash memory, and

Example 15. The method of any of the above examples, the memory module, when initialized, the data of the flash memory is all read into the MCU memory such that the MCU memory is configured as a flash shadow and the memory of the master computing module is configured to fully map the MCU memory.

Example 16 the method of any of the above examples, further comprising cyclically scanning, by control logic of the MCU, the MCU memory to obtain operation requests in the MCU memory from the memory map of the master computing module, and performing corresponding operations on the flash memory in accordance with the operation requests.

Example 17. The method of any of the above examples, the application within the partition of the IMA system continuing to execute the next instruction after ending the operation on the memory of the host computing module without waiting for a reply to the flash memory of the storage module.

Example 18. The method of any of the above examples, the flash memory comprising NAND flash memory.

Example 19 the method of any of the above examples, the master computing module being configured to communicate with the storage module over a PCIE bus and QDMA.

Example 20. The method of any of the above examples, the operations comprising reading, writing, erasing.

Example 21. The method of any of the above examples, further comprising performing, by the storage module, an underlying operation comprising one or more of flash block management, flash maintenance, data integrity processing.

Example 22 a machine-readable storage medium having instructions stored thereon that, when executed, cause an integrated modular avionics IMA system to perform the method of any one of examples 11-21.

Example 23. An integrated modular avionics IMA system comprising means for performing the method of any one of examples 11-21.

Claims

1. An integrated modular avionics IMA system, comprising:

A main computing module, the main computing module comprising:

A plurality of IMA partitions, wherein each IMA partition includes an application;

Hardware resources, including processors and memory;

a storage module, the storage module being configured outside the main computing module and communicatively coupled to the main computing module,

The memory of the main computing module forms a memory mapping with the storage module, so that the operation performed by the main computing module on its memory can cause the storage module to perform corresponding operations.

2. The IMA system of claim 1, wherein the main computing module and the storage module are configured to run in parallel.

3. The IMA system according to claim 1 or 2, wherein the storage module is implemented as a microcontroller unit MCU, the MCU includes an MCU memory and a flash memory, the MCU memory is communicatively coupled to the flash memory, and

Among them, the memory of the main computing module is configured to map the MCU memory.

4. The IMA system as described in claim 3 is characterized in that the storage module is configured to read all the data of the flash memory into the MCU memory when initialized, so that the MCU memory is configured as a flash memory shadow, and the memory of the main computing module is configured to fully map the MCU memory.

5. The IMA system as described in claim 3 is characterized in that the MCU includes control logic, which is configured to cyclically scan the MCU memory to obtain operation requests from the memory mapping of the main computing module in the MCU memory, and perform corresponding operations on the flash memory according to the operation requests.

6. The IMA system as described in claim 3 is characterized in that the main computing module is configured to enable the application in the IMA partition to continue to execute the next instruction after completing the operation on the memory of the main computing module without waiting for the reply of the flash memory of the storage module.

7. The IMA system of claim 3, wherein the flash memory comprises a NAND flash memory.

8. The IMA system according to claim 1 or 2, wherein the main computing module communicates with the storage module via a PCIE bus and QDMA configuration.

9. The IMA system according to claim 1 or 2, wherein the operations include reading, writing, and erasing.

10. The IMA system of claim 9, wherein the storage module is further configured to perform low-level operations including one or more of the following: flash memory block management, flash memory maintenance, and data integrity processing.

11. A method for memory operation of an integrated modular avionics IMA system, comprising:

An application in a partition of a main computing module sends an operation request to a memory of the main computing module, wherein the operation request causes a change in the memory of the main computing module;

A storage module in communication with the main computing module and located outside the main computing module detects a corresponding change in a memory of the storage module, wherein the memory of the main computing module forms a memory mapping with the storage module; and

The storage module performs corresponding operations on the flash memory installed on the storage module in response to the changes in the memory thereof.

12. A method for memory operation of an integrated modular avionics IMA system, comprising:

Scanning the memory of the storage module by a storage module located outside the main computing module of the IMA system to obtain an operation request from the memory mapping of the main computing module in the memory of the storage module, and

In response to detecting an operation request of the memory of the storage module, the storage module executes a corresponding operation on the flash memory mounted on the storage module.

13. The method according to claim 11 or 12, characterized in that the main computing module and the storage module are configured to be able to run in parallel.

14. The method according to claim 11 or 12, characterized in that the storage module is implemented as a micro control unit MCU, the MCU includes an MCU memory and a flash memory, the MCU memory is communicatively coupled to the flash memory, and

15. The method as claimed in claim 14 is characterized in that when the storage module is initialized, all the data in the flash memory are read into the MCU memory, so that the MCU memory is configured as a flash memory shadow, and the memory of the main computing module is configured to fully map the MCU memory.

16. The method as claimed in claim 14 further includes: the control logic of the MCU cyclically scans the MCU memory to obtain operation requests from the memory mapping of the main computing module in the MCU memory, and performs corresponding operations on the flash memory according to the operation requests.

17. The method of claim 14, wherein the application within the partition of the IMA system continues to execute the next instruction after completing the operation on the memory of the main computing module without waiting for the reply of the flash memory of the storage module.

18. The method of claim 14, wherein the flash memory comprises a NAND flash memory.

19. The method according to claim 11 or 12, characterized in that the main computing module communicates with the storage module through a PCIE bus and QDMA configuration.

20. The method according to claim 11 or 12, characterized in that the operation comprises reading, writing, and erasing.

21. The method of claim 20, further comprising: the storage module performing low-level operations including one or more of the following: flash block management, flash maintenance, and data integrity processing.

22. A machine-readable storage medium having instructions stored thereon, which, when executed, cause an integrated modular avionics IMA system to perform the method according to any one of claims 11-21.

23. An integrated modular avionics IMA system, comprising means for executing the method according to any one of claims 11-21.