CN119581348B

CN119581348B - A three-dimensional optoelectronic integrated packaging structure and its preparation method

Info

Publication number: CN119581348B
Application number: CN202411746353.6A
Authority: CN
Inventors: 陈彦亨; 林正忠
Original assignee: Shenghejing Micro Semiconductor Jiangyin Co Ltd
Current assignee: SJ Semiconductor Jiangyin Corp
Filing date: 2024-11-29
Publication date: 2025-10-10
Anticipated expiration: 2044-11-29

Abstract

The invention provides a three-dimensional photoelectric integrated packaging structure and a preparation method thereof, wherein the packaging structure comprises a TSV substrate, a rewiring layer, a first electric chip, a second electric chip, a dielectric layer, a conductive column, an optical chip module, a 3D stacked chip and a horizontal storage chip, the optical chip module, the first electric chip and the 3D stacked chip are connected through the TSV substrate and the rewiring layer to form an optical integrated circuit, the 3D stacked chip, the second electric chip and the horizontal storage chip are connected through the TSV substrate and the rewiring layer to form the electric integrated circuit, so that the transmission distance between the optical integrated circuit and the electric integrated circuit is shortened, the packaging area is reduced, the power consumption is reduced, and the high-density integrated packaging of the photoelectric chip is realized.

Description

Three-dimensional photoelectric integrated packaging structure and preparation method thereof

Technical Field

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a three-dimensional photoelectric integrated packaging structure and a preparation method thereof.

Background

With the development of cloud services, internet of things (IoT), 5G applications and the like, the amount of network information has been explosively increased, the requirement on interconnection bandwidth of a data center has been rapidly increased, and integrated circuit packaging technology has been continuously developed towards low cost, high reliability, rapid transmission and high density circuits, but the input/output (I/O) pin number of each packaging structure is different from the I/O total bandwidth in increasing speed, so that higher energy consumption is generated. The optical has the performances of low signal attenuation, low energy consumption, high bandwidth and compatibility with CMOS, and the introduction of the silicon optical technology can increase the bandwidth of I/O to reduce the energy consumption, wherein the optical and electric integration is important, and how to package an optical integrated circuit (PIC) and an Electric Integrated Circuit (EIC) in a good combination way is a problem to be solved.

Most of the existing semiconductor packaging structures directly bond an optical integrated Chip and an electrical integrated Chip on a substrate, and are electrically connected with the substrate in a wire-bonding (wire-bonding) or inverted-bonding (Flip-Chip) mode, so that the direct signal transmission distance between PIC and EIC is too long. And the silicon optical process node is relatively behind the electric chip, for example, the silicon optical process node developed by the current monolithic integration is a 45nm and 32nm process, which is far different from the process node below 10nm of the electric chip, so that the current photoelectric integrated semiconductor packaging structure is difficult to meet the requirement of high-density integrated packaging.

Therefore, how to provide a three-dimensional optoelectronic integrated packaging structure and a preparation method thereof to shorten the transmission distance of each module, realize high-density integrated packaging of optical chips and electrical chips, and reduce transmission power consumption is an important problem to be solved by those skilled in the art.

It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a three-dimensional optoelectronic integrated package structure and a method for manufacturing the same, which are used for solving the problems that it is difficult to perform high-density integrated package on an optical chip and an electrical chip and the transmission distance of each module is too long in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing a three-dimensional optoelectronic integrated package structure, including the following steps:

Providing a TSV substrate, forming a first rewiring layer on a first surface of the TSV substrate, wherein a TSV metal column is arranged in the TSV substrate, the first surface of the TSV substrate exposes the top end of the TSV metal column, and the first rewiring layer is electrically connected with the TSV metal column;

providing a first electrical chip and a second electrical chip, bonding the first electrical chip and the second electrical chip on the first rewiring layer so that the first electrical chip and the second electrical chip are electrically connected with the first rewiring layer respectively;

forming a dielectric layer on the first rewiring layer, wherein the dielectric layer is used for coating the first electric chip and the second electric chip;

forming a conductive post in the dielectric layer, wherein the conductive post penetrates through the dielectric layer to be electrically connected with the first rewiring layer, and thinning the dielectric layer to expose the conductive post, the first electric chip and the second electric chip;

forming a second rewiring layer on the dielectric layer, wherein the second rewiring layer is electrically connected with the top ends of the conductive columns;

forming a metal bump on the second re-wiring layer, the metal bump being electrically connected with the second re-wiring layer;

Providing a supporting substrate, and bonding the metal bump with the supporting substrate;

Thinning the TSV substrate to expose the bottom end of the TSV metal column, and forming a third rewiring layer on the second surface of the TSV substrate, wherein the third rewiring layer is electrically connected with the TSV metal column;

Providing an optical chip module, a 3D stacked chip and a horizontal storage chip, bonding the optical chip module, the 3D stacked chip and the horizontal storage chip on a third rewiring layer, electrically connecting the optical chip module, the 3D stacked chip and the second electric chip through the third rewiring layer to form an optical integrated circuit, and connecting the 3D stacked chip, the horizontal storage chip and the first electric chip through the third rewiring layer to form an electric integrated circuit.

Optionally, after bonding the first electrical chip and the second electrical chip on the first rewiring layer, the method further includes a step of thinning the first electrical chip and the second electrical chip.

Optionally, after bonding the optical chip module, the 3D stacked chip and the horizontal memory chip on the third rewiring layer, the method further includes a step of removing the support substrate.

Optionally, the method of forming the first re-wiring layer includes a damascene process, the method of forming the second re-wiring layer includes a damascene process, and the method of forming the third re-wiring layer includes a damascene process.

Optionally, a perpendicular projection of the optical chip module on the third rewiring layer at least partially overlaps with a perpendicular projection of the second electrical chip on the third rewiring layer.

Optionally, the second electrical chip comprises an ASIC chip for converting electrical signals of the 3D stacked chip into optical signals.

Optionally, the method further includes forming a filling layer in gaps among the optical chip module, the 3D stacked chip, and the horizontal memory chip and the third rewiring layer.

Optionally, after bonding the 3D stacked chip on the third rewiring layer, the method further includes a step of bonding a back plane power supply chip on the 3D stacked chip, wherein the back plane power supply chip is electrically connected with the 3D stacked chip.

Optionally, the 3D stacked chip includes a logic chip and a memory chip, and the memory chip is located on the logic chip and is electrically connected with the logic chip.

Optionally, before forming the second rewiring layer on the dielectric layer, the method further includes a step of forming a first heat dissipation layer on an upper surface of the first electrical chip and/or forming a second heat dissipation layer on an upper surface of the second electrical chip.

Optionally, the number of the horizontal memory chips is one or more, and the number of the first electrical chips is one or more.

The invention also provides a three-dimensional photoelectric integrated packaging structure, which comprises:

a TSV substrate, wherein a TSV metal column is arranged in the TSV substrate, a first surface of the TSV substrate exposes the top end of the TSV metal column, and a second surface of the TSV substrate exposes the bottom end of the TSV metal column;

a first rewiring layer located on the first face of the TSV substrate and electrically connected with the TSV metal posts;

a first electrical chip and a second electrical chip bonded to the first rewiring layer and electrically connected to the first rewiring layer, respectively;

The dielectric layer is positioned on the first rewiring layer and surrounds the periphery of the first electric chip and the periphery of the second electric chip;

The conductive column penetrates through the dielectric layer and is electrically connected with the first rewiring layer;

the second rewiring layer is positioned on the dielectric layer and is electrically connected with the top ends of the conductive columns;

a metal bump on the second re-wiring layer and electrically connected to the second re-wiring layer;

A third re-wiring layer located on the second surface of the TSV substrate and electrically connected with the bottom ends of the TSV metal posts;

The optical chip module, the 3D stacked chip and the horizontal storage chip are bonded on the third rewiring layer, the optical chip module, the 3D stacked chip and the second electric chip are electrically connected through the third rewiring layer to form an optical integrated circuit, and the 3D stacked chip, the horizontal storage chip and the first electric chip are connected through the third rewiring layer to form an electric integrated circuit.

Optionally, the second electrical chip comprises an ASIC chip that converts the electrical signal of the 3D stacked chip into an optical signal.

Optionally, a filling layer is further included, the filling layer being located in gaps between the optical chip module, the 3D stacked chip, and the horizontal memory chip and the third rewiring layer.

Optionally, a back-plate power supply chip is further included, and the back-plate power supply chip is bonded on the 3D stacked chip and electrically connected with the 3D stacked chip.

Optionally, the electronic device further comprises a first heat dissipation layer and/or a second heat dissipation layer, wherein the first heat dissipation layer is located on the upper surface of the first electric chip, and the second heat dissipation layer is located on the upper surface of the second electric chip.

As described above, the three-dimensional optoelectronic integrated package structure and the method for manufacturing the same according to the present invention connect the optical chip module, the first electrical chip and the 3D stacked chip to form the optical integrated circuit through the TSV substrate and the rewiring layer, and connect the 3D stacked chip, the second electrical chip and the horizontal memory chip to form the electrical integrated circuit through the TSV substrate and the rewiring layer, thereby shortening the transmission distance between the optical integrated circuit and the electrical integrated circuit, reducing the package area, reducing the power consumption, and realizing the high-density integrated package of the optoelectronic chip.

Drawings

Fig. 1 is a schematic view of an optoelectronic integrated package structure.

Fig. 2 is a process flow diagram of a method for fabricating a three-dimensional optoelectronic integrated package structure according to the present invention.

Fig. 3 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after forming a first rewiring layer.

Fig. 4 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after bonding a first electrical chip and a second electrical chip.

Fig. 5 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after polishing a first electrical chip and a second electrical chip.

Fig. 6 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after a dielectric layer is formed.

Fig. 7 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after forming a conductive pillar.

Fig. 8 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after grinding a dielectric layer.

Fig. 9 is a schematic structural diagram of the three-dimensional optoelectronic integrated package structure according to the present invention after forming a second rewiring layer.

Fig. 10 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after metal bumps are formed.

Fig. 11 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after forming a supporting substrate.

Fig. 12 is a schematic structural diagram of a three-dimensional integrated package structure according to the present invention after a ground TSV substrate is formed and a third re-wiring layer is formed.

Fig. 13 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after bonding an optical module chip, a 3D stacked chip, and a horizontal memory chip to a third redistribution layer.

Fig. 14 is a schematic structural diagram of a three-dimensional optoelectronic integrated package structure according to the present invention after a back-plate power supply chip is bonded to a 3D stacked chip.

Fig. 15 is a schematic structural diagram of the three-dimensional optoelectronic integrated package structure according to the present invention after removing the supporting substrate.

Description of the reference numerals

11. System board

12. Electrical chip

121. Substrate and method for manufacturing the same

122. Logic chip

123 HBM chip

13. Optical chip module

131. Substrate and method for manufacturing the same

132 ASIC chip

133. Optical chip

21 TSV substrate

22 TSV metal column

23. First rewiring layer

24. First electric chip

25. Second electric chip

26. Dielectric layer

27. Conductive column

28. Second rewiring layer

29. First heat dissipation layer

210. Second heat dissipation layer

211. Metal bump

212. Support substrate

213. Separating layer

214. Third rewiring layer

215. Optical chip module

216 3D stacked chip

2161. Logic chip

2162. Memory chip

217. Horizontal memory chip

218. Filling layer

219. Backboard power supply chip

S1-S9 steps

Detailed Description

Referring to fig. 1, a schematic diagram of an optoelectronic integrated package structure is shown, the optoelectronic integrated package structure includes a system board 11, an electrical chip 12 and an optical chip module 13, wherein the electrical chip 12 and the optical chip module 13 are electrically connected to the system board. The electric chip 12 includes a logic chip 122 and an HBM chip 123, wherein the chinese language of the HBM is called high bandwidth memory, the english language is called High Bandwidth Memory, the HBM chip 123 is connected to the logic chip 122 through a substrate 121, the optical chip module 13 includes an ASIC chip 132 and an optical chip 133, the chinese language of the ASIC is called Application specific integrated Circuit, the english language is called Application SPECIFIC INTEGRATED Circuit, and the ASIC chip 132 is connected to the optical chip 133 through a substrate 131. It can be seen that, in the optoelectronic integrated semiconductor package structure, the electrical chip 12 needs to be connected to the optical chip module 13 through the system board 11, so that the transmission distance between the optoelectronic signals is too long, and the package area is large.

Through a great amount of analysis and research, the inventor of the application provides a three-dimensional photoelectric integrated packaging structure and a preparation method thereof, which realize the short-distance connection of an optical integrated circuit and an electric integrated circuit, reduce the transmission distance of photoelectric signals, reduce the packaging area and reduce the power consumption, thereby meeting the high-density integrated packaging of photoelectric chips.

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.

As described in detail in the embodiments of the present invention, the schematic drawings showing the structure of the apparatus are not partially enlarged to general scale, and the schematic drawings are merely examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Referring to fig. 2, a process flow chart of a method for manufacturing a three-dimensional optoelectronic integrated package structure according to the present invention is shown, comprising the following steps:

The method comprises the steps of S1, providing a TSV substrate, forming a first rewiring layer on a first surface of the TSV substrate, wherein a TSV metal column is arranged in the TSV substrate, the top end of the TSV metal column is exposed on the first surface of the TSV substrate, and the first rewiring layer is electrically connected with the TSV metal column;

S2, providing a first electric chip and a second electric chip, bonding the first electric chip and the second electric chip on the first rewiring layer so that the first electric chip and the second electric chip are respectively electrically connected with the first rewiring layer;

s3, forming a dielectric layer coating the first electric chip and the second electric chip on the first rewiring layer;

S4, forming a conductive column in the dielectric layer, wherein the conductive column penetrates through the dielectric layer to be electrically connected with the first rewiring layer, and thinning the dielectric layer to expose the conductive column, the first electric chip and the second electric chip;

s5, forming a second rewiring layer on the dielectric layer, wherein the second rewiring layer is electrically connected with the top ends of the conductive columns;

S6, forming a metal bump on the second rewiring layer, wherein the metal bump is electrically connected with the second rewiring layer;

S7, providing a supporting substrate, and bonding the metal bump with the supporting substrate;

S8, thinning the TSV substrate to expose the bottom end of the TSV metal column, and forming a third rewiring layer on the second surface of the TSV substrate, wherein the third rewiring layer is electrically connected with the TSV metal column;

and S9, providing an optical chip module, a 3D stacked chip and a horizontal storage chip, bonding the optical chip module, the 3D stacked chip and the horizontal storage chip on the third rewiring layer, wherein the optical chip module, the 3D stacked chip and the second electric chip are electrically connected through the third rewiring layer to form an optical integrated circuit, and the 3D stacked chip, the horizontal storage chip and the first electric chip are connected through the third rewiring layer to form an electric integrated circuit.

The following describes the steps of the method for manufacturing a three-dimensional optoelectronic integrated package according to the present invention in detail with reference to fig. 3 to 15.

Referring first to fig. 2, step S1 is performed by providing a TSV substrate 21, forming a first re-wiring layer 23 on a first surface of the TSV substrate 21, wherein a TSV metal pillar 22 is disposed in the TSV substrate 21, the first surface of the TSV substrate 21 exposes a top end of the TSV metal pillar 22, and the first re-wiring layer 23 is electrically connected with the TSV metal pillar 22.

As an example, the TSV substrate 21 may include a wafer level substrate having a size of 4 inches, 6 inches, 8 inches, 12 inches, etc. to further improve the process efficiency, but the size of the TSV substrate 21 is not limited thereto.

As an example, the first re-wiring layer 23 may be a re-wiring layer using a damascene process, and includes a dielectric layer and a metal wiring embedded in the dielectric layer, where the material of the dielectric layer may include silicon oxide or silicon nitride, and the material of the metal wiring may include copper, aluminum, etc., and the material, layer number, layout, preparation method, etc. of the first re-wiring layer 23 may be selected as required, where the material is not excessively limited.

Referring to fig. 4 again, the step S2 is performed by providing a first electrical chip 24 and a second electrical chip 25, and bonding the first electrical chip 24 and the second electrical chip 25 on the first rewiring layer 23 so that the first electrical chip 24 and the second electrical chip 25 are electrically connected with the first rewiring layer 23, respectively.

As an example, the second electrical chip 25 includes an ASIC chip that can convert an electrical signal of the subsequent 3D stacked chip 218 (fig. 13) into an optical signal, but the kind of the second electrical chip 25 is not limited thereto, and may be specifically selected as needed.

By way of example, the bonding replaces the traditional bump or solder ball interconnection by a direct copper-to-copper connection, which can simplify the process of bonding the interconnection, reduce the size of the stack and package, reduce the power of the interconnection channel, and improve the heat dissipation capability.

As an example, referring to fig. 5, after the first electrical chip 24 and the second electrical chip 25 are bonded on the first rewiring layer 23, the method further includes a step of thinning the first electrical chip 24 and the second electrical chip 25, and processes such as mechanical polishing, chemical mechanical polishing, and dry chemical etching of plasma may be used to thin the first electrical chip 24 and the second electrical chip 25, so as to facilitate the subsequent processes, which are not limited herein, in this embodiment, a mechanical polishing process is used to implement a smooth polishing surface, and thickness reduction of the first electrical chip 24 and the second electrical chip 25 may shorten a transmission distance and reduce a thickness of a package.

Referring to fig. 6 again, the step S3 is performed by forming a dielectric layer 26 on the first rewiring layer 23 to cover the first electrical chip 24 and the second electrical chip 25.

As an example, the material of the dielectric layer 26 may be silicon oxide, but is not limited thereto, and inorganic materials such as silicon nitride or aluminum oxide may be used as needed, which is not limited thereto.

Referring to fig. 7 to 8, the step S4 is performed by forming a conductive pillar 27 in the dielectric layer 26, wherein the conductive pillar 27 penetrates through the dielectric layer 26 to be electrically connected with the first rewiring layer 23, and the dielectric layer 26 is thinned to expose the conductive pillar 27, the first electrical chip 24 and the second electrical chip 25, wherein fig. 7 is a schematic diagram of a structure obtained after the conductive pillar 27 is formed, and fig. 8 is a schematic diagram of a structure obtained after the dielectric layer 26 is thinned.

As an example, forming the conductive pillars 27 may include a step of forming a via (not shown) through the dielectric layer 26, and a step of metal filling the via. The method of punching may include laser punching or mechanical drilling, and may be selected according to the requirement, and the method of filling metal may be electroplating. The specific steps for preparing the conductive pillars 27, the dimensions of the conductive pillars 27 and the distribution of the conductive pillars 27 are not limited herein, and may be selected according to the need, and the conductive pillars 27 may be made of copper metal, but not limited thereto, and may be made of other conductive metal materials.

As an example, the dielectric layer 26 may be thinned by mechanical polishing, chemical mechanical polishing, plasma dry chemical etching, or other suitable process to expose the conductive pillars 27, the first electrical chip 24, and the second electrical chip 25, which is not limited herein, and in this embodiment, a chemical mechanical polishing process is used to obtain a relatively flat surface for facilitating subsequent processes.

Referring to fig. 9 again, the step S5 is performed by forming a second re-wiring layer 28 on the dielectric layer 26, wherein the second re-wiring layer 28 is electrically connected to the top ends of the conductive pillars 27.

As an example, the second re-wiring layer 28 may be a re-wiring layer using a damascene process, and includes a dielectric layer and a metal wiring embedded in the dielectric layer, where the material of the dielectric layer may include silicon oxide or silicon nitride, and the material of the metal wiring may include copper, aluminum, etc., and the material, the number of layers, the layout, the preparation method, etc. of the second re-wiring layer 28 may be selected as required, and the present invention is not limited thereto.

As an example, before the second re-wiring layer 28 is formed on the dielectric layer 26, a step of forming a first heat dissipation layer 29 on the upper surface of the first electrical chip 24 and/or forming a second heat dissipation layer 210 on the upper surface of the second electrical chip 25 may be performed to improve heat dissipation capability and reduce power consumption, and in this embodiment, a metal layer, preferably a copper electroplating layer, is electroplated on the back inactive area (area without electrical connection) of the first electrical chip 24 and the second electrical chip 25 to conduct heat for the first electrical chip 24 and the second electrical chip 25.

Referring to fig. 10 again, step S6 is performed to form a metal bump 211 on the second re-wiring layer 28, wherein the metal bump 211 is electrically connected to the second re-wiring layer 28.

As an example, the metal bump 211 may be a C24 metal bump to facilitate subsequent electrical extraction, but is not limited thereto, and is not limited thereto.

Referring to fig. 11 again, step S7 is performed to provide a supporting substrate 212 and bond the metal bump 211 to the supporting substrate 212.

As an example, the support substrate 212 may include, for example, a glass substrate, a metal substrate, a semiconductor substrate, etc., so that the support substrate 212 may provide support for a subsequent manufacturing process, wherein, in order to facilitate the subsequent removal of the support substrate 212, in this embodiment, a separation layer 213 is preferably formed on a surface of the support substrate 212, where the separation layer 213 includes, but is not limited to, one of an adhesive tape and a polymer layer, and a photo-thermal conversion layer may be selected as the separation layer 213, so that the separation layer 213 may be heated, for example, by a laser, etc., to separate the support substrate 212 from the metal bump 211, thereby improving the operation convenience.

Referring to fig. 12 again, step S8 is performed to thin the TSV substrate 21 to expose the bottom end of the TSV metal post 22, and form a third new wiring layer 214 on the second surface of the TSV substrate 21, wherein the third new wiring layer 214 is electrically connected to the TSV metal post 22.

As an example, a chemical mechanical polishing process may be used to expose the bottom ends of the TSV metal pillars 22, and the TSV substrate 21 with a relatively flat surface may be provided, so that the subsequent process may be performed, or only a process such as mechanical polishing may be used to expose the TSV metal pillars 22, which is not limited herein.

As an example, the third re-wiring layer 214 may be a re-wiring layer using a damascene process, and includes a dielectric layer and a metal wiring embedded in the dielectric layer, where the material of the dielectric layer may include silicon oxide or silicon nitride, and the material of the metal wiring may include copper, aluminum, etc., and the material, the number of layers, the layout, the preparation method, etc. of the third re-wiring layer 214 may be selected as required, and the present invention is not limited thereto.

Referring to fig. 13 again, step S9 is performed by providing an optical chip module 215, a 3D stacked chip 216 and a horizontal memory chip 217, bonding the optical chip module 215, the 3D stacked chip 216 and the horizontal memory chip 217 on the third re-wiring layer 214, wherein the optical chip module 215, the 3D stacked chip 216 and the second electric chip 25 are electrically connected through the third re-wiring layer 214 to form an optical integrated circuit, and the 3D stacked chip 216, the horizontal memory chip 217 and the first electric chip 24 are connected through the third re-wiring layer 214 to form an electric integrated circuit.

Specifically, the optical chip module 215 is electrically connected to the second electrical chip 25 through the third rewiring layer 214, the TSV metal pillar 22 and the first rewiring layer 23, the second electrical chip 25 is electrically connected to the 3D stacked chip 216 through the first rewiring layer 23, the TSV metal pillar 22 and the third rewiring layer 214, so as to form an optical integrated circuit, the 3D stacked chip 216 is electrically connected to the first electrical chip 24 through the third rewiring layer 214, the TSV metal pillar 22 and the first rewiring layer 23, and the first electrical chip 24 is electrically connected to the horizontal storage chip 217 through the first rewiring layer 23, the TSV metal pillar 22 and the third rewiring layer 214, so as to form an electrical integrated circuit.

As an example, the perpendicular projection of the optical chip module 215 onto the third rewiring layer 214 at least partially overlaps with the perpendicular projection of the second electrical chip 25 onto the third rewiring layer 214.

As an example, the perpendicular projection of the 3D stacked chip 216 onto the third rewiring layer 214 at least partially overlaps with the perpendicular projection of the first electrical chip 24 onto the third rewiring layer 214, and the perpendicular projection of the 3D stacked chip 216 onto the second rewiring layer 28 at least partially overlaps with the perpendicular projection of the second electrical chip 25 onto the third rewiring layer 214.

As an example, the vertical projection of the horizontal memory chip 217 on the third re-wiring layer 214 at least partially overlaps with the vertical projection of the first electrical chip 24 on the third re-wiring layer 214.

As an example, the optical chip module 215, the 3D stacked chip 216 and the horizontal memory chip 217 are all electrically connected to the second rewiring layer 28 by means of inverse bonding, and the types of the optical chip module 215, the 3D stacked chip 216 and the horizontal memory chip 217 are not limited here too much.

As an example, a filling layer 218 filling gaps is formed between the optical chip module 215, the 3D stacked chip 216, and the horizontal memory chip 217 and the second re-wiring layer 28 to form a protective layer, to improve bonding strength, and to avoid the influence of moisture, gas, etc. The material of the filling layer 218 may be selected as required, and may be an insulating material, which is not limited thereto.

As an example, the 3D stacked chip 216 includes a logic chip 2161 and a memory chip 2162, the memory chip 2162 being located on the logic chip 2161 and electrically connected to the logic chip 2161, i.e., the memory chip is vertically expanded with a 23D stack on the logic chip.

As an example, referring to fig. 14, the method further includes a step of bonding a back plane power chip 219 to the 3D stacked chip 216, wherein the back plane power chip 219 is electrically connected to the 3D stacked chip 216.

As an example, referring to fig. 15, the method further includes a step of removing the support substrate 212, wherein the support substrate 212 is removed based on the separation layer 213.

As an example, the number of the horizontal memory chips 217 is one or more, the number of the second electrical chips 25 is one or more, and the specific number may be determined according to the specific situation, where no excessive limitation is made, the number of the memory chips is limited by vertically expanding the 3D stacked chips 216, and horizontally expanding the horizontal memory chips 217 can further improve the memory performance, and meet the requirement of high performance and high computation power.

To this end, referring to fig. 15 again, a three-dimensional optoelectronic integrated package structure is manufactured, where the three-dimensional optoelectronic integrated package structure includes a TSV substrate 21, a first rewiring layer 23, a first electrical chip 24, a second electrical chip 25, a dielectric layer 26, a conductive pillar 27, a second rewiring layer 28, a metal bump 211, a third rewiring layer 214, an optical chip module 215, a 3D stacked chip 216, and a horizontal memory chip 217, in which a TSV metal pillar 22 is disposed in the TSV substrate 21, a first surface of the TSV substrate 21 exposes a top end of the TSV metal pillar 22, and a second surface of the TSV substrate 21 exposes a bottom end of the TSV metal pillar 22; the first re-wiring layer 23 is located on the first face of the TSV substrate 21 and electrically connected with the TSV metal pillars 22, the first electrical chip 24 and the second electrical chip 25 are bonded on the first re-wiring layer 23 and electrically connected with the first re-wiring layer 23 respectively, the dielectric layer 26 is located on the first re-wiring layer 23 and surrounds the first electrical chip 24 and the second electrical chip 25, the conductive pillars 27 penetrate through the dielectric layer 26 and electrically connected with the first re-wiring layer 23, the second re-wiring layer 28 is located on the dielectric layer 26 and electrically connected with the top ends of the conductive pillars 27, the metal bumps 211 are located on the second re-wiring layer 28 and electrically connected with the second re-wiring layer 28, the third re-wiring layer 214 is located on the second face of the substrate 21 and electrically connected with the bottom ends of the TSV metal pillars 22, the photo-chip 215, the 3D stack module 216 and the third re-wiring module 215 are horizontally stacked on the third re-wiring layer 215 and the third optical memory module 28, the 3D stacked chip 216 and the second electrical chip 25 are electrically connected through the third re-wiring layer 214 to constitute an optical integrated circuit, and the 3D stacked chip 216, the horizontal memory chip 217 and the first electrical chip 24 are connected through the third re-wiring layer 214 to constitute an electrical integrated circuit.

As an example, the first re-routing layer 23 may be a re-routing layer using a damascene process, the second re-routing layer 28 may be a re-routing layer using a damascene process, and the third re-routing layer 214 may be a re-routing layer using a damascene process.

As an example, the second electrical chip 25 may be an ASIC chip for converting the electrical signal of the 3D stacked chip 216 into an optical signal.

As an example, a filling layer 218 is provided in gaps among the optical chip module 215, the 3D stacked chip 216, and the horizontal memory chip 217 and the second re-wiring layer 28 to form a protective layer, improve bonding strength, and avoid the influence of moisture, gas, and the like.

As an example, a back plane power chip 219 may also be included, the back plane power chip 219 being bonded to the 3D stacked chip 216 and electrically connected to the 3D stacked chip 216.

As an example, the 3D stacked chip 216 includes a logic chip 2161 and a memory chip 2162, and the 3D stacked chip 216 extends the memory chip 2162 vertically over the logic chip 2161 using a 23D stack.

As an example, the upper surface of the first electronic chip 24 is further provided with a first heat dissipation layer 29, and/or the upper surface of the second electronic chip 25 is further provided with a second heat dissipation layer 210, so as to improve heat dissipation capability.

As an example, the number of the horizontal memory chips 217 is one or more, and the number of the first electrical chips 24 is one or more, and the specific number may be determined according to the specific situation, and is not limited herein.

In summary, according to the method for manufacturing the three-dimensional optoelectronic integrated package structure of the present invention, the optical chip module, the first electrical chip and the 3D stacked chip are connected through the TSV substrate and the rewiring layer to form the optical integrated circuit, and the 3D stacked chip, the second electrical chip and the horizontal memory chip are connected through the TSV substrate and the rewiring layer to form the electrical integrated circuit, so that the transmission distance between the optical integrated circuit and the electrical integrated circuit is shortened, the package area is reduced, the power consumption is reduced, and the high-density integrated package of the optoelectronic chip is realized. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A preparation method of a three-dimensional photoelectric integrated packaging structure is characterized by comprising the following steps:

2. The method for manufacturing the three-dimensional optoelectronic integrated package structure according to claim 1, wherein: after bonding the first electrical chip and the second electrical chip to the first rewiring layer, the method further comprises the step of thinning the first electrical chip and the second electrical chip.

3. The method of claim 1, further comprising removing the support substrate after bonding the optical chip module, the 3D stacked chip, and the horizontal memory chip to the third redistribution layer.

4. The method of manufacturing a three-dimensional optoelectronic integrated package of claim 1, wherein the first re-routing layer comprises a damascene process, the second re-routing layer comprises a damascene process, and the third re-routing layer comprises a damascene process.

5. The method of manufacturing a three-dimensional optoelectronic integrated package of claim 1, wherein the perpendicular projection of the optical chip module onto the third rewiring layer at least partially overlaps the perpendicular projection of the second electrical chip onto the third rewiring layer.

6. The method of claim 1, wherein the second electrical chip comprises an ASIC chip for converting electrical signals of the 3D stacked chip into optical signals.

7. The method of manufacturing a three-dimensional optoelectronic integrated package of claim 1, further comprising forming a filler layer in gaps between the optical chip module, the 3D stacked chip, and the horizontal memory chip and the third re-wiring layer.

8. The method of claim 1, further comprising bonding a back plane power chip to the 3D stacked chip after bonding the 3D stacked chip to the third redistribution layer, wherein the back plane power chip is electrically connected to the 3D stacked chip.

9. The method of claim 1, wherein the 3D stacked chip comprises a logic chip and a memory chip, and the memory chip is located on the logic chip and electrically connected with the logic chip.

10. The method of manufacturing a three-dimensional optoelectronic integrated package according to claim 1, further comprising the step of forming a first heat dissipation layer on an upper surface of the first electrical chip and/or forming a second heat dissipation layer on an upper surface of the second electrical chip before forming the second rewiring layer on the dielectric layer.

11. The method of manufacturing a three-dimensional optoelectronic integrated package of claim 1, wherein the number of horizontal memory chips is one or more and the number of first electrical chips is one or more.

12. A three-dimensional optoelectronic integrated package structure, comprising:

13. The three-dimensional optoelectronic integrated package of claim 12, wherein the perpendicular projection of said optical chip module onto said third rewiring layer at least partially overlaps the perpendicular projection of said second electrical chip onto said third rewiring layer.

14. The three-dimensional optoelectronic integrated package of claim 12, wherein said second electrical chip comprises an ASIC chip that converts electrical signals of said 3D stacked chip into optical signals.

15. The three-dimensional optoelectronic integrated package of claim 12, further comprising a filler layer positioned in a gap between said optical chip module, said 3D stacked chip, and said horizontal memory chip and said third rewiring layer.

16. The three-dimensional optoelectronic integrated package of claim 12, further comprising a back plane power chip bonded to said 3D stacked chip and electrically connected to said 3D stacked chip.

17. The three-dimensional optoelectronic integrated package of claim 12, wherein the 3D stacked die includes a logic die and a memory die, the memory die being located on and electrically connected to the logic die.

18. The three-dimensional optoelectronic integrated package of claim 12, further comprising a first heat spreader layer and/or a second heat spreader layer, wherein the first heat spreader layer is disposed on an upper surface of the first electrical chip and the second heat spreader layer is disposed on an upper surface of the second electrical chip.

19. The three-dimensional optoelectronic integrated package of claim 18, wherein said number of horizontal memory chips is one or more and said number of first electrical chips is one or more.