CN119581993A - Semiconductor photonic crystal light-emitting structure and preparation method thereof - Google Patents
Semiconductor photonic crystal light-emitting structure and preparation method thereof Download PDFInfo
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- CN119581993A CN119581993A CN202510134531.8A CN202510134531A CN119581993A CN 119581993 A CN119581993 A CN 119581993A CN 202510134531 A CN202510134531 A CN 202510134531A CN 119581993 A CN119581993 A CN 119581993A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
- H01S5/0282—Passivation layers or treatments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
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Abstract
The invention provides a semiconductor photon crystal luminous structure and a preparation method thereof, wherein the semiconductor photon crystal luminous structure comprises a semiconductor substrate layer; the semiconductor device comprises a semiconductor substrate layer, an active layer positioned on one side of the semiconductor substrate layer, a photonic crystal layer positioned on one side of the active layer, which is away from the semiconductor substrate layer, wherein the photonic crystal layer comprises a first semiconductor layer, a second semiconductor layer and a protective layer, the first semiconductor layer is provided with a groove, the groove extends into the first semiconductor layer from the surface of one side of the first semiconductor layer, which is away from the active layer, and the protective layer is positioned on the surface of the inner wall of the groove, and the second semiconductor layer is positioned between adjacent grooves, is away from the surface of one side of the active layer and does not extend into the groove. The light field mode regulation and control capability of the semiconductor photon crystal luminous structure is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor photonic crystal light-emitting structure and a preparation method thereof.
Background
Semiconductor lasers have wide application in the modern optoelectronic industry, and by introducing embedded periodic photonic crystals into semiconductor lasers, the semiconductor lasers are a general method for effectively regulating and controlling optical field modes and manufacturing various high-performance semiconductor lasers. The light extraction performance (mode, divergence angle, slope efficiency, etc.) of a semiconductor laser having a photonic crystal is often closely related to the processing quality of the photonic crystal. The production of the photonic crystal meeting the theoretical design requirements (morphology, size and roughness) is important in exerting the effect of the photonic crystal and realizing high-performance lasing.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is how to improve the light field mode regulation capability of the semiconductor photonic crystal light-emitting structure, so as to provide the semiconductor photonic crystal light-emitting structure and the preparation method thereof.
The application provides a semiconductor photonic crystal light-emitting structure which comprises a semiconductor substrate layer, an active layer and a photonic crystal layer, wherein the active layer is positioned on one side of the semiconductor substrate layer, the photonic crystal layer is positioned on one side of the active layer, which is away from the semiconductor substrate layer, and comprises a first semiconductor layer, a second semiconductor layer and a passivation protection layer, the first semiconductor layer is provided with a groove, the groove extends into the first semiconductor layer from one side surface of the first semiconductor layer, which is away from the active layer, the passivation protection layer is positioned on the inner wall of the groove, and the second semiconductor layer is positioned between adjacent grooves, is away from one side surface of the active layer and does not extend into the groove.
Optionally, the semiconductor device further comprises a semiconductor protection layer, wherein the passivation protection layer is located on one side of the semiconductor protection layer, which is away from the first semiconductor layer.
Optionally, the passivation protection layer is made of insulating oxide or insulating nitride.
Optionally, the semiconductor protection layer is a phosphide semiconductor material, a selenide semiconductor material or a sulfide semiconductor material.
Optionally, the passivation layer has a thickness of 1nm to 50nm.
Optionally, the thickness of the semiconductor protective layer is 1nm-50nm.
Optionally, the second semiconductor layer comprises a first part and a second part, wherein the first part is positioned on one side of the groove facing away from the semiconductor substrate layer, the second part is positioned on one side of the first semiconductor layer between adjacent grooves facing away from the semiconductor substrate layer, and the surface of the first part facing the groove is recessed into the first part relative to the surface of the second part facing the first semiconductor layer.
Optionally, the area of the recess surrounded by the surface of the passivation layer facing away from the first semiconductor layer is rectangular in cross-sectional shape perpendicular to the semiconductor substrate layer.
Optionally, the area of the recess surrounded by the surface of the passivation layer facing away from the first semiconductor layer has a first end facing away from the semiconductor substrate layer and a second end facing towards the semiconductor substrate layer, the first end having a smaller width parallel to the semiconductor substrate layer than the second end.
Optionally, the area of the recess surrounded by the surface of the passivation layer facing away from the first semiconductor layer has a positive trapezoid shape along a cross-sectional shape perpendicular to the semiconductor substrate layer.
Optionally, the area of the recess surrounded by the surface of the passivation layer facing away from the first semiconductor layer increases and then decreases in a direction parallel to the width of the semiconductor substrate layer from the semiconductor substrate layer to the active layer.
The semiconductor substrate comprises an active layer, a photon crystal layer, a Bragg reflector and a carrier transmission layer, wherein the Bragg reflector is positioned on one side of the photon crystal layer, which is away from the active layer, and the carrier transmission layer is positioned between the semiconductor substrate layer and the active layer, and the doping type of the carrier transmission layer is opposite to that of the Bragg reflector.
The application further provides a preparation method of the semiconductor photonic crystal light-emitting structure, which comprises the steps of forming an active layer on one side of a semiconductor substrate layer, forming a photonic crystal layer on one side of the active layer, which is away from the semiconductor substrate layer, wherein the step of forming the photonic crystal comprises the steps of forming a first semiconductor layer on one side of the active layer, which is away from the semiconductor substrate layer, forming a groove, which extends from one side surface of the first semiconductor layer, which is away from the active layer, into the first semiconductor layer, forming a passivation protection layer on the inner wall of the groove, and forming a second semiconductor layer on one side surface of the first semiconductor layer, which is away from the active layer, between adjacent grooves, wherein the second semiconductor layer does not extend into the groove.
Optionally, the step of forming the passivation layer on the inner wall of the groove comprises forming an initial passivation layer on the inner wall of the groove and on one side, facing away from the semiconductor substrate layer, of the first semiconductor layer between adjacent grooves, forming a mask layer in the groove, covering the initial passivation layer, exposing the initial passivation layer on one side, facing away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves, and removing the mask layer after etching the initial passivation layer on one side, facing away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves by taking the mask layer as a mask.
Optionally, before the initial passivation protection layer is formed, an initial semiconductor protection layer is formed on the inner wall surface of the groove and the surface of one side, facing away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves, after the mask layer is used as a mask for etching to remove the initial passivation protection layer on one side, facing away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves, the mask layer is used as a mask for etching to remove the initial semiconductor protection layer on one side, facing away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves, and the initial semiconductor protection layer on the inner wall of the groove forms the semiconductor protection layer.
The technical scheme of the invention has the following beneficial effects:
According to the semiconductor photonic crystal light-emitting structure provided by the technical scheme of the invention, the passivation protection layer is not a semiconductor material, the passivation protection layer is used for protecting the inner wall of the groove, and the material of the second semiconductor layer is prevented from growing in the groove, so that the space of the area, surrounded by the surface, of the groove, deviating from the first semiconductor layer, of the passivation protection layer is larger, and the light field mode regulation and control capability of the semiconductor photonic crystal light-emitting structure is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a semiconductor photonic crystal light emitting structure according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a semiconductor photonic crystal light emitting structure according to another embodiment of the present application;
FIG. 3 is a schematic diagram of a semiconductor photonic crystal light emitting structure according to another embodiment of the present application;
Fig. 4 to 13 are schematic structural views illustrating a process for fabricating a semiconductor photonic crystal light emitting structure according to an embodiment of the present application.
Detailed Description
The photonic crystal laser can simultaneously realize high output power and narrow beam divergence angle by utilizing the two-dimensional resonance of the two-dimensional photonic crystal singular point. The main principle is that a two-dimensional photonic crystal structure which is periodically arranged is formed on a photonic crystal layer through etching and secondary epitaxy, so that the limitation and regulation of an optical field mode are realized.
A preparation method of a photonic crystal laser comprises the steps of forming a carrier transmission layer on one side of a semiconductor substrate layer, forming an active layer on one side of the carrier transmission layer, which faces away from the semiconductor substrate layer, forming a photonic crystal layer on one side of the active layer, which faces away from the carrier transmission layer, and forming a Bragg reflector on one side of the photonic crystal layer, which faces away from the active layer. The method for forming the photonic crystal layer comprises the steps of forming a first semiconductor layer on one side of an active layer, which faces away from a semiconductor substrate layer, forming grooves which are arranged periodically, wherein the grooves extend into the first semiconductor layer from one side surface of the first semiconductor layer, which faces away from the active layer, and forming a second semiconductor layer on one side surface of the first semiconductor layer, which faces away from the active layer, in the grooves and between adjacent grooves.
However, since the second semiconductor layer is formed by adopting an epitaxial growth process, the second semiconductor layer is also formed in the groove in the process of forming the second semiconductor layer on the surface of one side of the first semiconductor layer, which is away from the active layer, between the adjacent grooves, so that the duty ratio of the gap inside the second semiconductor layer is small, and the adjustable optical field mode capability of the photonic crystal layer is limited, thereby greatly influencing the performance of the photonic crystal laser.
On the basis, the invention provides the semiconductor photonic crystal light-emitting structure and the preparation method thereof, and the light field mode regulation capability of the semiconductor photonic crystal light-emitting structure is improved.
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
An embodiment of the present invention provides a semiconductor photonic crystal light emitting structure, referring to fig. 1, 2 and 3, including:
A semiconductor substrate layer 100;
an active layer 120 located at one side of the semiconductor substrate layer 100;
A photonic crystal layer 130 located on a side of the active layer 120 facing away from the semiconductor substrate layer 100, the photonic crystal layer 130 including a first semiconductor layer 1300, a second semiconductor layer 1302, and a passivation layer 200a, the first semiconductor layer 1300 having a groove therein, the groove extending from a side surface of the first semiconductor layer 1300 facing away from the active layer 120 into the first semiconductor layer 1300, the passivation layer 200a being located on an inner wall of the groove, the second semiconductor layer 1302 being located between adjacent grooves, the first semiconductor layer 1300 facing away from a side surface of the active layer 120 and not extending into the groove.
In this embodiment, the passivation layer 200a is not a semiconductor material, the passivation layer 200a is used to protect the inner wall of the groove, and prevent the material of the second semiconductor layer 1302 from growing in the groove, so that the duty ratio of the area surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 is relatively large, and the light field mode adjusting capability of the semiconductor photonic crystal light emitting structure is improved.
For example, the semiconductor photonic crystal light emitting structure has more fundamental modes and fewer higher order modes.
In this embodiment, the semiconductor photonic crystal light emitting structure includes a surface emitting semiconductor laser.
In one embodiment, the photonic crystal layer 130 includes a first semiconductor layer 1300 and a second semiconductor layer 1302. The material of the first semiconductor layer 1300 includes a III-V compound semiconductor. The material of the first semiconductor layer 1300 includes, but is not limited to GaAs, gaSb, gaN, inP, silicon, or sapphire.
In one embodiment, the material of the first semiconductor layer 1300 comprises GaAs and the material of the second semiconductor layer 1302 comprises Al x1Ga1-x1 As.
In some embodiments, the refractive index of the second semiconductor layer 1302 is lower than the refractive index of the first semiconductor layer 1300. In other embodiments, the magnitude relationship between the refractive index of the second semiconductor layer 1302 and the refractive index of the first semiconductor layer 1300 is not limited.
In one embodiment, the first semiconductor layer 1300 and the second semiconductor layer 1302 are not doped with conductive ions.
In one embodiment, the area of the groove surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 is referred to as a void, where a plurality of voids are periodically arranged along a direction parallel to the surface of the semiconductor substrate layer 100, and the void is used for transmitting light with a specific wavelength, so that the wavelength of the light emitted by the semiconductor photonic crystal light emitting structure is more concentrated.
If the thickness of the passivation layer 200a is too large, the photonic crystal layer 130 has a reduced degree of improving the ability to modulate the light field. If the thickness of the passivation layer 200a is too small, the uniformity of the thickness of the passivation layer 200a is poor. Preferably, in one embodiment, the passivation layer 200a has a thickness of 1nm to 50nm, such as 1nm, 5nm, 10nm, 20nm, 30nm, 40nm, or 50nm.
In one embodiment, the passivation layer 200a is made of an insulating oxide or an insulating nitride, for example. An insulating oxide such as alumina or silica. An insulating nitride such as silicon nitride.
In one embodiment, the semiconductor photonic crystal light emitting structure further includes a semiconductor protection layer, the passivation protection layer 200a being located on a side of the semiconductor protection layer facing away from the first semiconductor layer 1300. The materials of the semiconductor protection layer and the passivation protection layer 200a are different. The lattice constant of the semiconductor protection layer is similar to that of the first semiconductor layer 1300, and the lattice of the semiconductor protection layer is matched with that of the first semiconductor layer 1300, so that defects of the first semiconductor layer 1300 facing the surface of the passivation protection layer can be reduced, and carrier recombination of the first semiconductor layer 1300 facing the surface of the passivation protection layer can be reduced. The passivation protection layer 200a prevents the material of the second semiconductor layer 1302 from growing in the grooves. Multiple protections are provided by combining semiconductor protective layers of different properties with passivation protective layer 200 a.
In one embodiment, the material of the semiconductor protective layer is, for example, a phosphide semiconductor material, such as gallium phosphide, a selenide semiconductor material, such as zinc selenide, or a sulfide semiconductor material, such as cadmium sulfide or zinc sulfide.
In one embodiment, the thickness of the semiconductor protective layer is 1nm-50nm, such as 1nm, 5nm, 10nm, 20nm, 30nm, 40nm, or 50nm.
In one embodiment, the second semiconductor layer 1302 includes a first portion on a side of the recess facing away from the semiconductor substrate layer 100 and a second portion on a side of the first semiconductor layer 1300 between adjacent recesses facing away from the semiconductor substrate layer 100, wherein a surface of the first portion facing the recess is recessed into the first portion relative to a surface of the second portion facing the first semiconductor layer 1300. This causes the second semiconductor layer 1302 to be farther away from the recess, and the second semiconductor layer 1302 does not extend into the recess. The position of the second semiconductor layer 1302 can be better controlled in the process.
In one embodiment, referring to fig. 1, the area of the recess surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 is rectangular in shape along a cross section perpendicular to the semiconductor substrate layer 100.
In one embodiment, referring to fig. 2, the region of the recess surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 has a first end facing away from the semiconductor substrate layer 100 and a second end facing toward the semiconductor substrate layer 100, the first end having a smaller width parallel to the semiconductor substrate layer than the second end. Such that the second semiconductor layer 1302 is less likely to enter the recess and the second semiconductor layer 1302 surrounding the recess is continuous on the side of the recess facing away from the semiconductor substrate layer. The position of the second semiconductor layer 1302 can be better controlled in the process.
In one embodiment, referring to fig. 2, the area of the recess surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 is in the shape of a positive trapezoid along a cross-sectional shape perpendicular to the semiconductor substrate layer 100.
In one embodiment, referring to fig. 3, the area of the recess surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 increases and then decreases in a direction parallel to the width of the semiconductor substrate layer from the semiconductor substrate layer 100 to the active layer 120. The region of the recess surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 has a first end facing away from the semiconductor substrate layer 100 and a second end facing towards the semiconductor substrate layer 100. The first end is smaller along a width parallel to the semiconductor substrate layer. Such that the second semiconductor layer 1302 is less likely to enter the recess and the second semiconductor layer 1302 surrounding the recess is continuous on the side of the recess facing away from the semiconductor substrate layer. The position of the second semiconductor layer 1302 can be better controlled in the process.
In one embodiment, the semiconductor photonic crystal light emitting structure further comprises a Bragg reflector 150 positioned on a side of the photonic crystal layer 130 facing away from the active layer 120, and a carrier transport layer 110 positioned between the semiconductor substrate layer 100 and the active layer 120, wherein the doping type of the carrier transport layer 110 is opposite to the doping type of the Bragg reflector 150. For example, the bragg mirror 150 is doped P-type and the carrier transport layer 110 is doped N-type.
In one embodiment, there is no Bragg mirror between the semiconductor substrate layer 100 and the active layer 120. The light emitted from the active layer 120 is transmitted to the bragg reflector 150 and reflected by the bragg reflector 150, and then exits from the semiconductor substrate layer 100 to the side of the semiconductor substrate layer 100 facing away from the active layer 120, and the photonic crystal layer 130 selects the wavelength of the light.
In one embodiment, the semiconductor photonic crystal light emitting structure further includes an underlying Bragg reflector between the semiconductor substrate layer and the active layer, the underlying Bragg reflector having a reflectivity greater than a reflectivity of the Bragg reflector.
The application further provides a preparation method of the semiconductor photonic crystal light-emitting structure, which comprises the steps of forming an active layer on one side of a semiconductor substrate layer, forming a photonic crystal layer on one side of the active layer, which is away from the semiconductor substrate layer, wherein the step of forming the photonic crystal comprises the steps of forming a first semiconductor layer on one side of the active layer, which is away from the semiconductor substrate layer, forming a groove, which extends from one side surface of the first semiconductor layer, which is away from the active layer, into the first semiconductor layer, forming a passivation protection layer on the inner wall of the groove, and forming a second semiconductor layer on one side surface of the first semiconductor layer, which is away from the active layer, between adjacent grooves, wherein the second semiconductor layer does not extend into the groove.
The method comprises the steps of forming an initial passivation protection layer on the inner wall of a groove and on one side, away from a semiconductor substrate layer, of a first semiconductor layer between adjacent grooves, forming a mask layer covering the initial passivation protection layer in the groove after the initial passivation protection layer is formed, exposing the initial passivation protection layer on one side, away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves, and removing the mask layer after the initial passivation protection layer on one side, away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves is etched by taking the mask layer as a mask.
The following describes a process of forming a semiconductor photonic crystal structure with reference to fig. 4 to 13.
Referring to fig. 4, a carrier transport layer 110 is formed on a side of the semiconductor substrate layer 100, and an active layer 120 is formed on a side of the carrier transport layer 110 facing away from the semiconductor substrate layer 100.
The embodiment further comprises a photonic crystal layer formed on one side, away from the semiconductor substrate layer, of the active layer, wherein the step of forming the photonic crystal comprises the steps of forming a first semiconductor layer on one side, away from the semiconductor substrate layer, of the active layer, forming a groove, extending into the first semiconductor layer from the surface, away from the active layer, of the first semiconductor layer, forming a passivation protection layer on the inner wall of the groove, and forming a second semiconductor layer, between adjacent grooves, on the surface, away from the active layer, of the first semiconductor layer, wherein the second semiconductor layer does not extend into the groove.
Referring to fig. 5, a first semiconductor layer 1300 is formed on a side of the active layer 120 facing away from the semiconductor substrate layer 100.
In one embodiment, the process of forming the first semiconductor layer 1300 is a deposition process, such as an organic metal chemical vapor deposition process. The material of the first semiconductor layer 1300 is described with reference to the foregoing embodiments.
Referring to fig. 6, a groove 1301 is formed, the groove 1301 extending from a side surface of the first semiconductor layer 1300 facing away from the active layer 120 into the first semiconductor layer 1300.
In one embodiment, the process of forming the recess 1301 is an etching process.
In this embodiment, the recess 1301 is rectangular in cross-sectional shape perpendicular to the semiconductor substrate layer 100.
In other embodiments, the recess has a first end facing away from the semiconductor substrate layer 100 and a second end facing towards the semiconductor substrate layer 100, the first end having a smaller width parallel to the semiconductor substrate layer than the second end. Illustratively, the recess has a positive trapezoid shape along a cross-sectional shape perpendicular to the semiconductor substrate layer 100.
In other embodiments, the grooves increase and then decrease in a direction parallel to the semiconductor substrate layer from the semiconductor substrate layer 100 to the active layer 120.
Referring to fig. 7, an initial passivation protection layer 200 is formed on the surface of the grooves 1301 and on a side of the first semiconductor layer 1300 between adjacent grooves 1301 facing away from the semiconductor substrate layer 100.
In one embodiment, the process of forming the initial passivation protection layer 200 is a deposition process including a combination of one or more of an atomic layer deposition process, a physical vapor deposition process, and a chemical vapor deposition process.
The thickness and material of the initial passivation layer 200 refer to those of the passivation layer of the previous embodiment.
In one embodiment, the initial passivation layer 200 is deposited at a temperature of 150 ℃ to 200 ℃, which may result in a better film uniformity and lower stress of the initial passivation layer 200.
Referring to fig. 8 to 11 in combination, a mask layer 210a is formed in the recess 1301 to cover the initial passivation layer 200, and the mask layer 210a exposes the initial passivation layer 200 on a side of the first semiconductor layer 1300 between adjacent recesses 1301 facing away from the semiconductor substrate layer 100.
Referring to fig. 8, an initial mask layer 210 covering the initial passivation protection layer 200 is formed in the grooves 1301 and on a side of the first semiconductor layer 1300 facing away from the semiconductor substrate layer 100 between adjacent grooves 1301.
The material of the initial mask layer 210 includes photoresist. The process of forming the initial mask layer 210 includes a spin-on process.
Referring to fig. 9, the initial mask layer 210 of the side of the first semiconductor layer 1300 facing away from the semiconductor substrate layer 100 between adjacent grooves 1301 is removed, and the initial mask layer 210 in the grooves 1301 forms a mask layer 210a.
Referring to fig. 10, the initial passivation layer 200 on the side of the first semiconductor layer 1300 facing away from the semiconductor substrate layer 100 between the adjacent grooves 1301 is etched using the mask layer 210a as a mask, where the passivation layer 200 on the side wall of the groove 1301 forms the passivation layer 200a.
The process of removing the initial passivation layer 200 on the side of the first semiconductor layer 1300 facing away from the semiconductor substrate layer 100 between the adjacent grooves 1301 by etching using the mask layer 210a as a mask includes an anisotropic dry etching process.
The description of the passivation protection layer 200a is referred to the description of the previous embodiment, and will not be described in detail.
The description of the region of the recess surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 refers to the foregoing embodiments.
Referring to fig. 11, after the first semiconductor layer 1300 between adjacent grooves 1301 is etched away from the initial passivation layer 200 on the side of the semiconductor substrate layer 100 with the mask layer 210a as a mask, the mask layer 210a is removed.
In one embodiment, the mask layer 210a is removed using acetone or N-methylpyrrolidone.
Referring to fig. 12, a second semiconductor layer 1302 is formed on a side surface of the first semiconductor layer 1300 facing away from the active layer 120 between adjacent grooves 1301, the second semiconductor layer 1302 not extending into the grooves 1301.
The material of the second semiconductor layer 1302 refers to the foregoing embodiments.
In one embodiment, the process of forming the second semiconductor layer 1302 includes an epitaxial growth process. In one embodiment, the process of forming the second semiconductor layer 1302 is, for example, an organometallic chemical vapor deposition process. The material of the second semiconductor layer 1302 is described with reference to the previous embodiments.
In this embodiment, in the process of forming the second semiconductor layer 1302, the first semiconductor layer 1300 is used as a substrate for epitaxially growing the second semiconductor layer 1302. Since the inside of the groove 1301 has the passivation layer 200a, the passivation layer 200a is not a semiconductor material, and thus the passivation layer 200a cannot serve as a substrate for epitaxial growth of the second semiconductor layer 1302, and thus the second semiconductor layer 1302 does not extend into the groove 1301. The area of the recess 1301 surrounded by the surface of the passivation layer 200a facing away from the first semiconductor layer 1300 has a large duty cycle.
Since the inside of the groove 1301 has the passivation protection layer 200a, the passivation protection layer 200a can protect the inner wall surface of the groove 1301 from damage.
Referring to fig. 13, a bragg mirror 150 is formed on a side of the photonic crystal layer 130 facing away from the active layer 120. Reference is made to the previous embodiments with respect to the materials of the bragg mirror 150.
The preparation method of the semiconductor photonic crystal light-emitting structure is different from the preparation method of the embodiment in that before the initial passivation protection layer is formed, the initial semiconductor protection layer is formed on the inner wall surface of the groove and the surface of one side, facing away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves, after the initial passivation protection layer on one side, facing away from the semiconductor substrate layer, of the first semiconductor layer between the adjacent grooves is etched and removed by taking the mask layer as a mask, the initial semiconductor protection layer on the inner wall of the groove is formed into the semiconductor protection layer, and then the mask layer is removed.
In one embodiment, the process of the initial semiconductor protective layer is a deposition process that includes a combination of one or more of an atomic layer deposition process, a physical vapor deposition process, and a chemical vapor deposition process.
The material and thickness descriptions of the semiconductor protective layer refer to the descriptions of the foregoing embodiments.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (15)
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| CN119905897A (en) * | 2025-04-02 | 2025-04-29 | 中国人民解放军国防科技大学 | Semiconductor light emitting structure and preparation method thereof |
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| CN119905897A (en) * | 2025-04-02 | 2025-04-29 | 中国人民解放军国防科技大学 | Semiconductor light emitting structure and preparation method thereof |
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