CN119626288B - Memory refresh circuit, refresh method and memory - Google Patents

Abstract

The embodiments of the present disclosure provide a memory refresh circuit, a refresh method and a memory. The refresh circuit includes an address generation module and an address decoding module, wherein the address generation module generates an address signal and determines a word line control signal according to a refresh command, and the address decoding module determines M address selection signals according to the address signal and the word line control signal, wherein each address selection signal includes a module address selection signal and a row address selection signal, the M module address selection signals correspond to M storage modules one-to-one, and the M row address selection signals correspond to M word lines one-to-one, so that the M address selection signals correspond to M different word lines of all storage modules, and different word lines of all storage modules can be opened at the same time, which can reduce the voltage drop on the word line and shorten the action time of the word line, thereby improving the success rate of memory refresh, and further improving the stability of the memory.

Description

Memory refresh circuit, refresh method and memory

Technical Field

Embodiments of the present disclosure relate to the field of memory technology, and in particular to a refresh circuit, a refresh method and a memory of the memory.

Background Art

The storage unit of Dynamic Random Access Memory (DRAM) is composed of a capacitor and a switch. The data of DRAM is stored in the capacitor. Since the capacitor will gradually lose its charge, the stored data may be destroyed if it is not refreshed regularly. Therefore, DRAM needs to be refreshed regularly to recharge to ensure the accuracy of the data. When DRAM is refreshed, the address signal is generated by the internal counter. Since the order of the address signal generated by the internal counter is certain, the word line opening order of all storage units is certain during the refresh operation.

In the prior art, the same word lines of all storage modules are opened simultaneously, resulting in a large voltage drop on the word lines. The word lines of storage modules farther from the power supply move more slowly, affecting the success rate of refresh and causing poor stability of the memory.

Summary of the invention

The present disclosure provides a memory refresh circuit, a refresh method and a memory, which can reduce the voltage drop on the word line and shorten the action time of the word line, thereby improving the success rate of memory refresh and further improving the stability of the memory.

In a first aspect, the present disclosure provides a refresh circuit of a memory, wherein the memory includes M memory modules arranged along a first direction, each of the memory modules includes m memory cells arranged along a second direction, the first direction and the second direction intersect, the M memory cells arranged along the first direction are connected to the same word line, M=2 ^N , N is an integer greater than zero, and m is an integer greater than or equal to M. The refresh circuit includes: an address generation module and an address decoding module.

The address generation module is configured to generate an address signal and determine a word line control signal according to a refresh command. The address decoding module is configured to determine M address selection signals according to the address signal and the word line control signal, wherein each of the address selection signals includes a module address selection signal and a row address selection signal, the M module address selection signals correspond one-to-one to the M storage modules, and the M row address selection signals correspond one-to-one to the M word lines.

In some embodiments of the present disclosure, the address decoding module includes a combinational logic unit and an address latch unit, the address input end of the combinational logic unit is connected to the address output end of the address generation module, the address output end of the combinational logic unit is connected to the address input end of the address latch unit, the control end of the address latch unit is connected to the word line control output end of the address generation module, the first level input end of the combinational logic unit is connected to a high level, and the second level input end of the combinational logic unit is connected to a low level.

The combinational logic unit is configured to determine the M module address selection signals according to the module address signal in the address signal, and to determine the M row address selection signals according to the row address signal in the address signal. The address latch unit is configured to output the M address selection signals when the word line control signal is at a high level.

In some embodiments of the present disclosure, the combinational logic unit includes M logic units, the module address signal includes N module address sub-signals, the N address input terminals of each of the logic units are connected one-to-one with the N module address sub-signals, the first level input terminal of the logic unit is connected to a high level or a low level, the second level input terminal of the logic unit is connected to a high level or a low level, and the output terminal of the logic unit is connected to the address input terminal of the address latch unit.

Each of the logic units is configured to force the N module address sub-signals to be output as a high level or a low level to obtain one module address selection signal.

In some embodiments of the present disclosure, the combinational logic unit includes a first logic unit, a second logic unit, a third logic unit, and a fourth logic unit, and the module address signal includes a first module address sub-signal and a second module address sub-signal.

The first level input terminal and the second level input terminal of the first logic unit are connected to a low level, the first address input terminal of the first logic unit is connected to the first module address sub-signal, the second address input terminal of the first logic unit is connected to the second module address sub-signal, and the output terminal of the first logic unit is connected to the first address input terminal of the address latch unit. The first level input terminal of the second logic unit is connected to a low level, the second level input terminal of the second logic unit is connected to a high level, the first address input terminal of the second logic unit is connected to the first module address sub-signal, the second address input terminal of the second logic unit is connected to the second module address sub-signal, and the output terminal of the second logic unit is connected to the second address input terminal of the address latch unit.

The first level input terminal of the third logic unit is connected to a high level, the second level input terminal of the third logic unit is connected to a low level, the first address input terminal of the third logic unit is connected to the first module address sub-signal, the second address input terminal of the third logic unit is connected to the second module address sub-signal, and the output terminal of the third logic unit is connected to the third address input terminal of the address latch unit. The first level input terminal and the second level input terminal of the fourth logic unit are connected to a high level, the first address input terminal of the fourth logic unit is connected to the first module address sub-signal, the second address input terminal of the fourth logic unit is connected to the second module address sub-signal, and the output terminal of the fourth logic unit is connected to the fourth address input terminal of the address latch unit.

The first logic unit is configured to force the first module address sub-signal and the second module address sub-signal to be output as a low level, so as to obtain a first module address selection signal. The second logic unit is configured to force the first module address sub-signal to be output as a high level, and the second module address sub-signal to be output as a low level, so as to obtain a second module address selection signal. The third logic unit is configured to force the first module address sub-signal to be output as a low level, and the second module address sub-signal to be output as a high level, so as to obtain a third module address selection signal. The fourth logic unit is configured to force the first module address sub-signal and the second module address sub-signal to be output as a high level, so as to obtain a fourth module address selection signal.

In some embodiments of the present disclosure, each of the logic units includes N XOR gates and 2N inverters. In each of the logic units, the two input ends of each of the XOR gates are connected one-to-one with the output ends of the two inverters, the input ends of the N inverters are connected one-to-one with the N module address sub-signals, and the input ends of the other N inverters are connected to a high level or a low level, and the output end of each of the XOR gates is connected to the address input end of the address latch unit.

In some embodiments of the present disclosure, each of the logic units includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first XOR gate and a second XOR gate, the input end of the first inverter is connected to the first module address sub-signal, the output end of the first inverter is connected to the first input end of the first XOR gate, the input end of the second inverter is connected to a low level or a high level, the output end of the second inverter is connected to the second input end of the first XOR gate, the input end of the third inverter is connected to the second module address sub-signal, the output end of the third inverter is connected to the first input end of the second XOR gate, the input end of the fourth inverter is connected to a low level or a high level, the output end of the fourth inverter is connected to the second input end of the second XOR gate, and the output end of the first XOR gate and the output end of the second XOR gate are connected to the address input end of the address latch unit.

In some embodiments of the present disclosure, the address latch unit includes M address latches, the address input ends of the M address latches are connected one-to-one with the output ends of the M logic units, and the control ends of the M address latches are all connected to the word line control output end of the address generation module.

In some embodiments of the present disclosure, the address generation module includes a command decoder, a word line control signal generator and an internal counter, the output of the command decoder is connected to the input of the word line control signal generator and the input of the internal counter, the output of the internal counter is connected to the address input of the address decoding module, and the output of the word line control signal generator is connected to the control end of the address decoding module.

The command decoder is configured to generate an internal refresh command in response to the received refresh command. The word line control signal generator is configured to pull up the word line control signal according to the internal refresh command. The internal counter is configured to generate the address signal according to the internal refresh command.

In a second aspect, the present disclosure provides a memory refresh method, which is applied to any refresh circuit provided in the first aspect, and the refresh method includes:

According to the refresh command, an address signal is generated and a word line control signal is determined; according to the address signal and the word line control signal, M address selection signals are determined.

Each of the address selection signals includes a module address selection signal and a row address selection signal, the M module address selection signals correspond one-to-one to the M storage modules, and the M row address selection signals correspond one-to-one to the M word lines.

In a third aspect, the present disclosure provides a memory comprising M storage modules arranged along a first direction and any refresh circuit provided in the first aspect.

Each of the storage modules includes m storage units arranged along a second direction, the first direction and the second direction intersect, the M storage units arranged along the first direction are connected to the same word line, M=2 ^N , N is an integer greater than zero, and m is an integer greater than or equal to M.

The technical solution disclosed in the present invention provides a refresh circuit, including an address generation module and an address decoding module. The address generation module generates an address signal and determines a word line control signal according to a refresh command. The address decoding module determines M address selection signals according to the address signal and the word line control signal, wherein each address selection signal includes a module address selection signal and a row address selection signal. The M module address selection signals correspond one-to-one to the M storage modules, and the M row address selection signals correspond one-to-one to the M word lines. In this way, the M address selection signals correspond to M different word lines of all storage modules, and different word lines of all storage modules can be opened at the same time, which can reduce the voltage drop on the word line and shorten the action time of the word line, thereby improving the success rate of memory refresh and further improving the stability of the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure, wherein:

FIG1 is a schematic diagram of the structure of a memory provided by the prior art;

FIG2 is a schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

FIG3 is a schematic diagram of the structure of a refresh circuit provided by an embodiment of the present disclosure;

FIG4 is a working timing diagram of a refresh circuit provided in an embodiment of the present disclosure;

FIG5 is a circuit diagram of an address decoding module provided in an embodiment of the present disclosure;

FIG6 is a flow chart of a refresh method provided in an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

The term "and/or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character "/" in this article generally indicates that the associated objects before and after are in an "or" relationship.

In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two). Similarly, "plurality groups" and "at least two groups" mean more than two groups (including two).

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

Figure 1 is a schematic diagram of the structure of a memory provided by the prior art. As shown in Figure 1, the memory includes a counter 30, multiple storage modules 10 and multiple word lines 20. Each storage module 10 includes multiple storage cells 11. Multiple storage cells 11 along the row direction are connected to the same word line 20. Each word line 20 is connected to a power supply. When the memory is refreshed, the counter 30 generates an address signal, and the word line 20 of the corresponding storage cell 11 can be selected and opened based on the address signal.

In practical applications, the order of address signals generated by the counter 30 is certain. Therefore, when the memory is refreshed, the order in which the word lines 20 of all storage cells 11 are opened is certain. As shown in FIG1 , when the memory is refreshed, the same word lines 20 of all storage modules 10 are opened at the same time. Therefore, the voltage drop on the word lines 20 is large, and the word lines 20 of the storage modules 10 that are far away from the power supply move slower, affecting the action duration of the word lines 20. When the action duration of the word lines 20 is longer, the success rate of memory refresh is lower, resulting in poor stability of the memory.

In view of this, the present disclosure provides a refresh circuit of a memory, including an address generation module and an address decoding module, wherein the address generation module generates an address signal and determines a word line control signal according to a refresh command, and the address decoding module determines M address selection signals according to the address signal and the word line control signal, wherein each address selection signal includes a module address selection signal and a row address selection signal, the M module address selection signals correspond one-to-one to the M storage modules, and the M row address selection signals correspond one-to-one to the M word lines, so that the M address selection signals correspond to M different word lines of all storage modules, and different word lines of all storage modules can be opened at the same time, which can reduce the voltage drop on the word line and shorten the action time of the word line, thereby improving the success rate of memory refresh, and further improving the stability of the memory.

The technical solution provided by the present disclosure is described in detail below with reference to several specific embodiments.

FIG2 is a schematic diagram of the structure of a memory provided by an embodiment of the present disclosure. As shown in FIG2 , the memory includes a refresh circuit 100 and M storage modules 10 arranged along a first direction, where M=2 ^N , and N is an integer greater than zero. Each storage module 10 includes m storage cells 11 arranged along a second direction, where m is an integer greater than or equal to M. The first direction and the second direction intersect, and the M storage cells 11 arranged along the first direction are connected to the same word line 20.

Exemplarily, as shown in FIG2 , the memory includes four storage modules 10, namely, a first storage module 10a, a second storage module 10b, a third storage module 10c, and a fourth storage module 10d, and the first storage module 10a, the second storage module 10b, the third storage module 10c, and the fourth storage module 10d are arranged in sequence along the first direction. Each storage module 10 includes four storage units 11, respectively denoted as storage unit 11a, storage unit 11b, storage unit 11c, and storage unit 11d, and the storage units 11a, storage unit 11b, storage unit 11c, and storage unit 11d in each storage module 10 are arranged in sequence along the second direction.

The memory includes four word lines 20, namely a first word line 21, a second word line 22, a third word line 23 and a fourth word line 24. The first word line 21 connects the memory cell 11a in the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d, the second word line 22 connects the memory cell 11b in the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d, the third word line 23 connects the memory cell 11c in the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d, and the fourth word line 24 connects the memory cell 11d in the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d.

It should be noted that FIG2 only takes N=2 as an example, and exemplarily shows that the memory includes 2 ² storage modules 10. In practical applications, the number of storage modules 10 may also be 2 ¹ , 2 ³ or 2 ^N , where N is any integer greater than 3, and the present disclosure does not make any specific limitation on this.

It should also be noted that FIG. 2 only takes m=M as an example, and exemplarily shows that the memory includes M word lines 20. In practical applications, the number of word lines 20 can also be any integer greater than M, and the present disclosure does not make any specific limitation on this.

Figure 3 is a structural schematic diagram of a refresh circuit provided in an embodiment of the present disclosure. As shown in Figure 3, the refresh circuit 100 includes an address generation module 110 and an address decoding module 120. The input end of the address generation module 110 receives a refresh command, the address output end of the address generation module 110 is connected to the address input end of the address decoding module 120, and the word line control output end of the address generation module 110 is connected to the control end of the address decoding module 120.

The address generation module 110 is configured to generate an address signal and determine a word line control signal according to a refresh command, and the address decoding module 120 is configured to determine M address selection signals according to the address signal and the word line control signal. Each address selection signal includes a module address selection signal and a row address selection signal, the M module address selection signals correspond to the M storage modules 10 one by one, and the M row address selection signals correspond to the M word lines 20 one by one.

Exemplarily, as shown in FIG3 , the address generation module 110 includes a command decoder 111, a word line control signal generator 112, and an internal counter 113. The output end of the command decoder 111 is connected to the input end of the word line control signal generator 112 and the input end 113 of the internal counter, the output end of the internal counter 113 is connected to the address input end of the address decoding module 120, and the output end of the word line control signal generator 112 is connected to the control end of the address decoding module 120.

When the memory needs to be refreshed, a refresh command is generated, and the command decoder 111 can receive the refresh command and respond to it, decoding to generate an internal refresh command, and the word line control signal generator 112 pulls up the word line control signal according to the internal refresh command. At the same time, the internal counter 113 generates an address signal according to the internal refresh command, as shown in Figure 4, which is a working timing diagram of a refresh circuit provided in an embodiment of the present disclosure.

For example, if the address signal is A<12:0>=0000000000000, then the address signal A<12:0> includes thirteen address sub-signals, namely, a first address sub-signal A<0>, a second address sub-signal A<1>, a third address sub-signal A<2>, a fourth address sub-signal A<3>, a fifth address sub-signal A<4>, a sixth address sub-signal A<5>, a seventh address sub-signal A<6>, an eighth address sub-signal A<7>, a ninth address sub-signal A<8>, a tenth address sub-signal A<9>, an eleventh address sub-signal A<10>, a twelfth address sub-signal A<11> and a thirteenth address sub-signal A<12>.

The internal counter 113 includes thirteen output terminals, namely a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, a sixth output terminal, a seventh output terminal, an eighth output terminal, a ninth output terminal, a tenth output terminal, an eleventh output terminal, a twelfth output terminal and a thirteenth output terminal, wherein the first output terminal outputs a first address sub-signal A<0>, the second output terminal outputs a second address sub-signal A<1>, the third output terminal outputs a third address sub-signal A<2>, the fourth output terminal outputs a fourth address sub-signal A<3>, The fifth output terminal outputs the fifth address sub-signal A<4>, the sixth output terminal outputs the sixth address sub-signal A<5>, the seventh output terminal outputs the seventh address sub-signal A<6>, the eighth output terminal outputs the eighth address sub-signal A<7>, the ninth output terminal outputs the ninth address sub-signal A<8>, the tenth output terminal outputs the tenth address sub-signal A<9>, the eleventh output terminal outputs the eleventh address sub-signal A<10>, the twelfth output terminal outputs the twelfth address sub-signal A<11>, and the thirteenth output terminal outputs the thirteenth address sub-signal A<12>.

The address signal includes a module address signal and a row address signal. The module address signal includes N module address sub-signals. The N module address sub-signals may be high-N-bit address sub-signals in the address signal. The row address signal may be the remaining address sub-signals in the address signal.

For example, based on the above embodiment, when N=2, the module address signal includes a first module address sub-signal and a second module address sub-signal, the thirteenth address sub-signal A<12> can be used as the second module address sub-signal, and the twelfth address sub-signal A<11> can be used as the first module address sub-signal, then the module address signal A<12,11>=00, and the row address signal A<10:0>=00000000000.

Continuing to refer to Figure 3, the address decoding module 120 includes a combinational logic unit 121 and an address latch unit 122. The address input end of the combinational logic unit 121 is connected to the address output end of the address generation module 110, the address output end of the combinational logic unit 121 is connected to the address input end of the address latch unit 122, the control end of the address latch unit 122 is connected to the word line control output end of the address generation module 110, the first level input end of the combinational logic unit 121 is connected to a high level, and the second level input end of the combinational logic unit 121 is connected to a low level.

Exemplarily, as shown in Figure 3, the combinational logic unit 121 includes M logic units 1211, the N address input terminals of each logic unit 1211 are connected one-to-one with the N module address sub-signals, the first level input terminal of the logic unit 1211 is connected to a high level or a low level, the second level input terminal of the logic unit 1211 is connected to a high level or a low level, and the output terminal of the logic unit 1211 is connected to the address input terminal of the address latch unit 122.

For example, as shown in FIG3 , the combinational logic unit 121 includes four logic units 1211, namely, a first logic unit 1211a, a second logic unit 1211b, a third logic unit 1211c, and a fourth logic unit 1211d. Among them, the first level input terminal and the second level input terminal of the first logic unit 1211a are connected to a low level, the first address input terminal of the first logic unit 1211a is connected to a first module address sub-signal, the second address input terminal of the first logic unit 1211a is connected to a second module address sub-signal, and the output terminal of the first logic unit 1211a is connected to the first address input terminal of the address latch unit 122.

The first level input terminal of the second logic unit 1211b is connected to a low level, the second level input terminal of the second logic unit 1211b is connected to a high level, the first address input terminal of the second logic unit 1211b is connected to the first module address sub-signal, the second address input terminal of the second logic unit 1211b is connected to the second module address sub-signal, and the output terminal of the second logic unit 1211b is connected to the second address input terminal of the address latch unit 122.

The first level input terminal of the third logic unit 1211c is connected to a high level, the second level input terminal of the third logic unit 1211c is connected to a low level, the first address input terminal of the third logic unit 1211c is connected to the first module address sub-signal, the second address input terminal of the third logic unit 1211c is connected to the second module address sub-signal, and the output terminal of the third logic unit 1211c is connected to the third address input terminal of the address latch unit 122.

The first level input terminal and the second level input terminal of the fourth logic unit 1211d are connected to a high level, the first address input terminal of the fourth logic unit 1211d is connected to the first module address sub-signal, the second address input terminal of the fourth logic unit 1211d is connected to the second module address sub-signal, and the output terminal of the fourth logic unit 1211d is connected to the fourth address input terminal of the address latch unit 122.

Based on the above embodiment, the first logic unit 1211a can perform a logic operation on the first module address sub-signal A<11> and the low level to obtain a low level, so as to force the first module address sub-signal A<11> to be output as a low level, and perform a logic operation on the second module address sub-signal A<12> and the low level to obtain a low level, so as to force the second module address sub-signal A<12> to be output as a low level, and the obtained first module address selection signal AS1<12,11>=00.

The first logic unit 1211a may also determine the first row address selection signal AS1<10:0> according to the row address signal A<10:0>. For example, the first logic unit 1211a determines the row address signal A<10:0> as the first row address selection signal AS1<10:0> to obtain the first address selection signal AS1<12:0>.

The second logic unit 1211b can perform a logic operation on the first module address sub-signal A<11> and a high level to obtain a high level, so as to force the first module address sub-signal A<11> to be output as a high level, and perform a logic operation on the second module address sub-signal A<12> and a low level to obtain a low level, so as to force the second module address sub-signal A<12> to be output as a low level, and the obtained second module address selection signal AS2<12,11>=01.

The second logic unit 1211b can also determine a second row address selection signal AS2<10:0> based on the row address signal A<10:0>. The second row address selection signal AS2<10:0> is different from the first row address selection signal AS1<10:0>. For example, the second logic unit 1211b adds 1 to the row address signal A<10:0> and determines it as the second row address selection signal AS2<10:0> to obtain the second address selection signal AS2<12:0>.

The third logic unit 1211c can perform a logic operation on the first module address sub-signal A<11> and a low level to obtain a low level, so as to force the first module address sub-signal A<11> to be output as a low level, and perform a logic operation on the second module address sub-signal A<12> and a high level to obtain a high level, so as to force the second module address sub-signal A<12> to be output as a high level, and the obtained third module address selection signal AS3<12,11>=10.

The third logic unit 1211c can also determine the third row address selection signal AS3<10:0> based on the row address signal A<10:0>. The third row address selection signal AS3<10:0> is different from the second row address selection signal AS2<10:0> and the first row address selection signal AS1<10:0>. For example, the third logic unit 1211c adds 2 to the row address signal A<10:0> and determines it as the third row address selection signal AS3<10:0> to obtain the third address selection signal AS3<12:0>.

The fourth logic unit 1211d can perform a logic operation on the first module address sub-signal A<11> and the high level to obtain a high level, so as to force the first module address sub-signal A<11> to be output as a high level, and perform a logic operation on the second module address sub-signal A<12> and the high level to obtain a high level, so as to force the second module address sub-signal A<12> to be output as a high level, and the obtained fourth module address selection signal AS4<12,11>=11.

The fourth logic unit 1211d can also determine the fourth row address selection signal AS4<10:0> based on the row address signal A<10:0>. The fourth row address selection signal AS4<10:0> is different from the third row address selection signal AS3<10:0>, the second row address selection signal AS2<10:0> and the first row address selection signal AS1<10:0>. For example, the fourth logic unit 1211d adds 3 to the row address signal A<10:0> and determines it as the fourth row address selection signal AS4<10:0> to obtain the fourth address selection signal AS4<12:0>.

It should be noted that FIG3 only takes N=2 as an example, and exemplarily shows that the combinational logic unit 121 includes 2 ² logic units 1211. In practical applications, the number of logic units 1211 may also be 2 ¹ , 2 ³ or 2 ^N , where N is any integer greater than 3, and the present disclosure does not make any specific limitation on this.

In this way, each logic unit 1211 can force the N module address sub-signals to be output as high level or low level respectively to obtain a module address selection signal, and the combinational logic unit 121 can determine M module address selection signals according to the module address signal in the address signal.

Each logic unit 1211 may also determine a row address selection signal according to the row address signal, and the combinational logic unit 121 may determine M row address selection signals according to the row address signal in the address signal.

3 , the address latch unit 122 includes M address latches 1221 , the address input ends of the M address latches 1221 are connected one-to-one with the output ends of the M logic units 1211 , and the control ends of the M address latches 1221 are connected to the word line control output end of the address generation module 110 .

For example, as shown in Figure 3, the address latch unit 122 includes four address latches 1221, namely a first address latch 1221a, a second address latch 1221b, a third address latch 1221c and a fourth address latch 1221d, and the control end of the first address latch 1221a, the control end of the second address latch 1221b, the control end of the third address latch 1221c and the control end of the fourth address latch 1221d receive word line control signals.

The address input end of the first address latch 1221a is connected to the output end of the first logic unit 1211a, the address input end of the second address latch 1221b is connected to the output end of the second logic unit 1211b, the address input end of the third address latch 1221c is connected to the output end of the third logic unit 1211c, and the address input end of the fourth address latch 1221d is connected to the output end of the fourth logic unit 1211d.

During the refresh operation, the word line control signal received by the first address latch 1221a, the second address latch 1221b, the third address latch 1221c and the fourth address latch 1221d is a high level. Under the effect of the high level, the first address latch 1221a outputs the first address selection signal AS1<12:0>, the second address latch 1221b outputs the second address selection signal AS2<12:0>, the third address latch 1221c outputs the third address selection signal AS3<12:0>, and the fourth address latch 1221d outputs the fourth address selection signal AS4<12:0>.

It should be noted that FIG3 only takes N=2 as an example, and exemplarily shows that the address latch unit 122 includes 2 ² address latches 1221. In practical applications, the number of address latches 1221 may also be 2 ¹ , 2 ³ or 2 ^N , where N is any integer greater than 3, and the present disclosure does not make any specific limitation on this.

In this way, each address latch 1221 can output an address selection signal when the word line control signal is at a high level, and the address latch unit 122 can output M address selection signals when the word line control signal is at a high level.

To summarize, the module address selection signal in each address selection signal corresponds to a different storage module 10, M address selection signals correspond to M storage modules 10, the row address selection signal in each address selection signal corresponds to a different word line 20, and the M address selection signals also correspond to M word lines 20. Then, the M address selection signals correspond to M different word lines 20 of all storage modules 10, and the different word lines 20 of all storage modules 10 can be opened at the same time, which can reduce the voltage drop on the word line 20 and shorten the action time of the word line 20, thereby improving the success rate of memory refresh and further improving the stability of the memory.

In some embodiments, the combinational logic unit 121 is configured to determine M module address selection signals according to the module address signal in the address signal. The address latch unit 122 is configured to determine M row address selection signals according to the row address signal; when the word line control signal is at a high level, the M address selection signals are output.

Exemplarily, as shown in FIG3 , the first logic unit 1211a may update the module address signal in the address signal to the first module address selection signal AS1<12,11>, and transmit the updated address signal to the first address register 1221a. The first address register 1221a may determine the first row address selection signal AS1<10:0> according to the row address signal A<10:0>, for example, the first address register 1221a determines the row address signal A<10:0> as the first row address selection signal AS1<10:0> to obtain the first address selection signal AS1<12:0>, and outputs the first address selection signal AS1<12:0> under the action of a high level.

The second logic unit 1211b can update the module address signal in the address signal to the second module address selection signal AS2<12,11>, and transmit the updated address signal to the second address register 1221b. The second address register 1221b can determine the second row address selection signal AS2<10:0> according to the row address signal A<10:0>, and the second row address selection signal AS2<10:0> is different from the first row address selection signal AS1<10:0>. For example, the second logic unit 1211b adds 1 to the row address signal A<10:0> to determine it as the second row address selection signal AS2<10:0> to obtain the second address selection signal AS2<12:0>, and outputs the second address selection signal AS2<12:0> under the action of a high level.

The third logic unit 1211c can update the module address signal in the address signal to the third module address selection signal AS3<12,11>, and transmit the updated address signal to the third address register 1221c. The third address register 1221c can determine the third row address selection signal AS3<10:0> according to the row address signal A<10:0>, and the third row address selection signal AS3<10:0> is different from the second row address selection signal AS2<10:0> and the first row address selection signal AS1<10:0>. For example, the third logic unit 1211c adds 2 to the row address signal A<10:0> to determine it as the third row address selection signal AS3<10:0>, so as to obtain the third address selection signal AS3<12:0>, and outputs the third address selection signal AS3<12:0> under the action of a high level.

The fourth logic unit 1211d may update the module address signal in the address signal to the fourth module address selection signal AS4<12,11>, and transmit the updated address signal to the fourth address register 1221d. The fourth address register 1221d may determine the fourth row address selection signal AS4<10:0> according to the row address signal A<10:0>, and the fourth row address selection signal AS4<10:0> is different from the third row address selection signal AS3<10:0>, the second row address selection signal AS2<10:0>, and the first row address selection signal AS1<10:0>. For example, the fourth logic unit 1211d adds 3 to the row address signal A<10:0> to determine the fourth row address selection signal AS4<10:0> to obtain the fourth address selection signal AS4<12:0>, and outputs the fourth address selection signal AS4<12:0> under the action of a high level.

In some embodiments, Figure 5 is a circuit diagram of an address decoding module provided by an embodiment of the present disclosure. As shown in Figure 5, each logic unit 1211 includes N XOR gates XOR and 2N inverters INV. In each logic unit 1211, the two input ends of each XOR gate XOR are connected one-to-one with the output ends of two inverters INV, the input ends of the N inverters INV are connected one-to-one with the N module address sub-signals, and the input ends of the N inverters INV are connected to a high level or a low level, and the output end of the XOR gate XOR is connected to the address input end of the address latch unit 122.

Exemplarily, as shown in FIG5 , each logic unit 1211 includes two XOR gates XOR and four inverters INV, the two XOR gates XOR are respectively a first XOR gate XOR1 and a second XOR gate XOR2, and the four inverters INV are respectively a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV4.

The input end of the first inverter INV1 is connected to the first module address sub-signal A<11>, the output end of the first inverter INV1 is connected to the first input end of the first XOR gate XOR1, the input end of the second inverter INV2 is connected to a low level or a high level, and the output end of the second inverter INV2 is connected to the second input end of the first XOR gate XOR1. The input end of the third inverter INV3 is connected to the second module address sub-signal A<12>, the output end of the third inverter INV3 is connected to the first input end of the second XOR gate XOR2, the input end of the fourth inverter INV4 is connected to a low level or a high level, the output end of the fourth inverter INV4 is connected to the second input end of the second XOR gate XOR2, and the output end of the first XOR gate XOR1 and the output end of the second XOR gate XOR2 are connected to the address input end of the address latch unit 122.

Each first inverter INV1 can invert the first module address sub-signal A<11> to obtain an inverted signal of the first module address sub-signal A<11>, and each third inverter INV3 can invert the second module address sub-signal A<12> to obtain an inverted signal of the second module address sub-signal A<12>. Based on the above embodiment, if the first module address sub-signal A<11>=0 and the second module address sub-signal A<12>=0, the inverted signal of the first module address sub-signal A<11> is at a high level, and the inverted signal of the second module address sub-signal A<12> is at a high level.

For example, as shown in Figure 5, in the first logic unit 1211a, the input end of the second inverter INV2 and the input end of the fourth inverter INV4 are connected to a low level, the second inverter INV2 and the fourth inverter INV4 can both invert the low level to a high level, the first XOR gate XOR1 can XOR the high level and the inverted signal of the first module address sub-signal A<11> to obtain a low level, the second XOR gate XOR2 can XOR the high level and the inverted signal of the second module address sub-signal A<12> to obtain a low level, that is, the first module address selection signal AS1<12,11>=00.

In the second logic unit 1211b, the input end of the second inverter INV2 is connected to a high level, and the second inverter INV2 can invert the high level to a low level. The input end of the fourth inverter INV4 is connected to a low level, and the fourth inverter INV4 can invert the low level to a high level. The first XOR gate XOR1 can XOR the low level and the inverted signal of the first module address sub-signal A<11> to obtain a high level. The second XOR gate XOR2 can XOR the high level and the inverted signal of the second module address sub-signal A<12> to obtain a low level, that is, the second module address selection signal AS2<12,11>=01.

In the third logic unit 1211c, the input end of the second inverter INV2 is connected to a low level, and the second inverter INV2 can invert the low level to a high level. The input end of the fourth inverter INV4 is connected to a high level, and the fourth inverter INV4 can invert the high level to a low level. The first XOR gate XOR1 can XOR the high level and the inverted signal of the first module address sub-signal A<11> to obtain a low level. The second XOR gate XOR2 can XOR the low level and the inverted signal of the second module address sub-signal A<12> to obtain a high level, that is, the third module address selection signal AS3<12,11>=10.

In the fourth logic unit 1211d, the input end of the second inverter INV2 and the input end of the fourth inverter INV4 are connected to a high level, the second inverter INV2 and the fourth inverter INV4 can both invert the high level to a low level, the first XOR gate XOR1 can XOR the low level and the inverted signal of the first module address sub-signal A<11> to obtain a high level, the second XOR gate XOR2 can XOR the low level and the inverted signal of the second module address sub-signal A<12> to obtain a high level, that is, the fourth module address selection signal AS4<12,11>=11.

It should be noted that FIG. 5 only takes N=2 as an example, and exemplarily shows that each logic unit 1211 includes two XOR gates and 2 2 inverters INV. In practical applications, the number of XOR gates XOR in each logic unit 1211 can also be 1, 3 or any integer greater than 3, and the corresponding number of inverters INV is twice the number of XOR gates XOR. The present disclosure does not make any specific restrictions on this.

The present disclosure also provides a refresh method, which is applied to the refresh circuit 100 provided in any of the above embodiments.

FIG6 is a flow chart of a refresh method provided by an embodiment of the present disclosure. As shown in FIG6 , the specific steps of the refresh method include:

S101, generating an address signal and determining a word line control signal according to a refresh command.

Exemplarily, when the memory needs to be refreshed, a refresh command is generated, the command decoder responds to the refresh command, decodes and generates an internal refresh command, the word line control signal generator pulls up the word line control signal according to the internal refresh command, and the internal counter generates an address signal according to the internal refresh command.

Wherein, the address signal includes a module address signal and a row address signal, the module address signal includes N module address sub-signals, the N module address sub-signals may be high-N address sub-signals in the address signal, and the row address signal may be the remaining address sub-signals in the address signal. For example, the address signal A<12:0>=0000000000000, when N=2, the module address signal includes a first module address sub-signal and a second module address sub-signal, the thirteenth address sub-signal A<12> may be used as the second module address sub-signal, and the twelfth address sub-signal A<11> may be used as the first module address sub-signal, then the module address signal A<12,11>=00, and the row address signal A<10:0>=00000000000.

S102, determining M address selection signals according to the address signal and the word line control signal.

Each address selection signal includes a module address selection signal and a row address selection signal, the M module address selection signals correspond one-to-one to the M storage modules, and the M row address selection signals correspond one-to-one to the M word lines.

Exemplarily, the combinational logic unit can determine M module address selection signals based on the module address signal in the address signal, and determine M row address selection signals based on the row address signal in the address signal. The address latch unit outputs M address selection signals when the word line control signal is at a high level.

For example, the combinational logic unit can force N module address sub-signals to be output as high level and low level respectively to obtain M module address selection signals, and can add M different values to the row address signal to obtain M row address selection signals to obtain M address selection signals. The address latch unit outputs M address selection signals under the action of high level.

In other embodiments, the combinational logic unit can determine M module address selection signals based on the module address signal in the address signal, and the address latch unit can determine M row address selection signals based on the row address signal, and output M address selection signals when the word line control signal is at a high level.

For example, the combinational logic unit may update the module address signal in the address signal M times to update the module address signal in the address signal to M different module address selection signals respectively. The address latch unit receives the M updated address signals, and determines M different row address selection signals according to the row address signal in the M updated address signals to obtain M address selection signals, and outputs the M address selection signals under the action of a high level.

In the disclosed embodiment, an address signal is generated and a word line control signal is determined according to a refresh command, and M address selection signals are determined according to the address signal and the word line control signal, wherein each address selection signal includes a module address selection signal and a row address selection signal, the M module address selection signals correspond one-to-one to the M storage modules, and the M row address selection signals correspond one-to-one to the M word lines. In this way, the M address selection signals correspond to M different word lines of all storage modules, and the different word lines of all storage modules can be opened at the same time, which can reduce the voltage drop on the word line and shorten the action time of the word line, thereby improving the success rate of memory refresh and further improving the stability of the memory.

Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural form and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims (9)

1. A refresh circuit of a memory, wherein the memory comprises M memory modules arranged along a first direction, each memory module comprises M memory cells arranged along a second direction, the first direction and the second direction intersect, the M memory cells arranged along the first direction are connected to a same word line, m=2 ^N, N is an integer greater than zero;

the refreshing circuit comprises an address generating module and an address decoding module;

the address generation module is configured to generate an address signal and determine a word line control signal according to a refresh command;

The address decoding module is configured to determine M address selection signals according to the address signals and the word line control signals, wherein each address selection signal comprises a module address selection signal and a row address selection signal, the M module address selection signals are in one-to-one correspondence with the M memory modules, and the M row address selection signals are in one-to-one correspondence with the M word lines;

The address decoding module comprises a combinational logic unit and an address latch unit;

The address input end of the combinational logic unit is connected with the address output end of the address generation module, the address output end of the combinational logic unit is connected with the address input end of the address latch unit, the control end of the address latch unit is connected with the word line control output end of the address generation module, the first level input end of the combinational logic unit is connected with a high level, and the second level input end of the combinational logic unit is connected with a low level;

The combination logic unit is configured to determine M module address selection signals according to module address signals in the address signals, and determine M row address selection signals according to row address signals in the address signals;

The address latch unit is configured to output M address selection signals when the word line control signal is at a high level.

2. The refresh circuit of claim 1, wherein the combinational logic cell comprises M logic cells, the module address signal comprises N module address sub-signals;

The N address input ends of each logic unit are connected with N module address sub-signals in a one-to-one correspondence manner, the first level input end of each logic unit is connected with a high level or a low level, the second level input end of each logic unit is connected with a high level or a low level, and the output end of each logic unit is connected with the address input end of each address latch unit;

Each logic unit is configured to force the N module address sub-signals to be high or low, so as to obtain one module address selection signal.

3. The refresh circuit of claim 2, wherein the combinational logic cell comprises a first logic cell, a second logic cell, a third logic cell, and a fourth logic cell, the module address signal comprising a first module address sub-signal and a second module address sub-signal;

The first level input end and the second level input end of the first logic unit are connected with low level, the first address input end of the first logic unit is connected with the first module address sub-signal, the second address input end of the first logic unit is connected with the second module address sub-signal, and the output end of the first logic unit is connected with the first address input end of the address latch unit;

the first level input end of the second logic unit is connected with a low level, the second level input end of the second logic unit is connected with a high level, the first address input end of the second logic unit is connected with the first module address sub-signal, the second address input end of the second logic unit is connected with the second module address sub-signal, and the output end of the second logic unit is connected with the second address input end of the address latch unit;

the first level input end of the third logic unit is connected with a high level, the second level input end of the third logic unit is connected with a low level, the first address input end of the third logic unit is connected with the first module address sub-signal, the second address input end of the third logic unit is connected with the second module address sub-signal, and the output end of the third logic unit is connected with the third address input end of the address latch unit;

the first level input end and the second level input end of the fourth logic unit are connected with high level, the first address input end of the fourth logic unit is connected with the first module address sub-signal, the second address input end of the fourth logic unit is connected with the second module address sub-signal, and the output end of the fourth logic unit is connected with the fourth address input end of the address latch unit;

The first logic unit is configured to forcedly output the first module address sub-signal and the second module address sub-signal to be low level to obtain a first module address selection signal;

The second logic unit is configured to forcedly output the first module address sub-signal to be high level, forcedly output the second module address sub-signal to be low level, and obtain a second module address selection signal;

the third logic unit is configured to forcedly output the first module address sub-signal to be low level, forcedly output the second module address sub-signal to be high level, and obtain a third module address selection signal;

The fourth logic unit is configured to forcedly output the first module address sub-signal and the second module address sub-signal to a high level to obtain a fourth module address selection signal.

4. The refresh circuit of claim 2, wherein each of the logic cells comprises N exclusive-or gates and 2N inverters;

In each logic unit, two input ends of each exclusive-OR gate are connected with output ends of two inverters in a one-to-one correspondence manner, the input ends of N inverters are connected with N module address sub-signals in a one-to-one correspondence manner, the input ends of N inverters are connected with high level or low level, and the output end of each exclusive-OR gate is connected with the address input end of the address latch unit.

5. The refresh circuit of claim 4, wherein each of the logic cells comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first exclusive-or gate, and a second exclusive-or gate;

the input end of the first inverter is connected with a first module address sub-signal, the output end of the first inverter is connected with the first input end of the first exclusive-OR gate, the input end of the second inverter is connected with a low level or a high level, the output end of the second inverter is connected with the second input end of the first exclusive-OR gate, the input end of the third inverter is connected with a second module address sub-signal, the output end of the third inverter is connected with the first input end of the second exclusive-OR gate, the input end of the fourth inverter is connected with a low level or a high level, the output end of the fourth inverter is connected with the second input end of the second exclusive-OR gate, and the output ends of the first and second exclusive-OR gates are connected with the address input end of the address latch unit.

6. The refresh circuit of claim 2, wherein the address latch unit comprises M address latches;

The address input ends of the M address latches are connected with the output ends of the M logic units in a one-to-one correspondence mode, and the control ends of the M address latches are connected with the word line control output ends of the address generation module.

7. The refresh circuit of any one of claims 1-6, wherein the address generation module comprises a command decoder, a word line control signal generator, and an internal counter;

The output end of the command decoder is connected with the input end of the word line control signal generator and the input end of the internal counter, the output end of the internal counter is connected with the address input end of the address decoding module, and the output end of the word line control signal generator is connected with the control end of the address decoding module;

The command decoder is configured to generate an internal refresh command in response to the received refresh command;

The word line control signal generator is configured to pull up the word line control signal according to the internal refresh command;

The internal counter is configured to generate the address signal according to the internal refresh command.

8. A memory refresh method applied to the refresh circuit of any one of claims 1-7, comprising:

Generating address signals and determining word line control signals according to the refresh command;

Determining M address selection signals according to the address signals and the word line control signals, wherein each address selection signal comprises a module address selection signal and a row address selection signal, the M module address selection signals are in one-to-one correspondence with the M memory modules, and the M row address selection signals are in one-to-one correspondence with the M word lines;

the determining M address selection signals according to the address signals and the word line control signals includes:

determining M module address selection signals according to module address signals in the address signals;

Determining M row address selection signals according to row address signals in the address signals;

M address selection signals are output when the word line control signal is at a high level.

9. A memory comprising M memory modules arranged in a first direction and the refresh circuit of any one of claims 1-7;

Each memory module comprises M memory cells arranged along a second direction, the first direction and the second direction are intersected, the M memory cells arranged along the first direction are connected with the same word line, M=2 ^N, and N is an integer larger than zero.