CN119621626A - Clock phase adjustment method, Ethernet data transmission method and related equipment - Google Patents
Clock phase adjustment method, Ethernet data transmission method and related equipment Download PDFInfo
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- CN119621626A CN119621626A CN202411418051.6A CN202411418051A CN119621626A CN 119621626 A CN119621626 A CN 119621626A CN 202411418051 A CN202411418051 A CN 202411418051A CN 119621626 A CN119621626 A CN 119621626A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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Abstract
The invention relates to the technical field of chip signals and discloses a clock phase adjusting method, an Ethernet data transmission method and related equipment. The clock phase adjusting method comprises the steps of setting an initial value and a counting turnover condition of a counter by acquiring a link state and a working transmission rate of an opposite end chip (PHY chip or MAC chip), and generating a first clock signal and a second clock signal with phase deviation when the value of the counter reaches the counting turnover condition for outputting a data signal and a clock signal of the PHY chip or the MAC chip. The invention enables the RGMII interface to adapt to the interconnection scenes of various MAC chips and PHY chips, improves the compatibility of network card chips and solves the problem of error sampling of RGMII interface data.
Description
Technical Field
The present invention relates to the field of chip signal technologies, and in particular, to a clock phase adjustment method, an ethernet data transmission method, and related devices.
Background
The RGMII (Reduced Gigabit compact MEDIA INDEPENDENT INTERFACE) interface is a simplified version of the Gigabit media independent interface, and is mainly used for communication between ethernet MAC (MEDIA ACCESS Control) and PHY (PHYSICAL LAYER ). The RGMII interface adopts a 4-bit data interface, supports three communication rates of 10/100/1000Mbps, and meets the requirements under different network environments. At a transmission rate of 1000Mbps, the clock frequency is 125MHz, 25MHz at 100Mbps, and 2.5MHz at 10 Mbps. In the 1000Mbps mode, the RGMII interface transmits data at the same time on the rising edge and the falling edge of the clock, so that high-speed data transmission is realized.
As shown in fig. 1, the RGMII interface mainly includes the following signal lines:
TXCLK (transmit clock) is provided by MAC to PHY;
Tx_ctrl (transmit control) transmit control signal;
TXDATA [3:0] (transmit data) 4-bit parallel transmit data signals;
RXCLK (receive clock) is extracted from the received data by the PHY independent of the transmit clock.
RX_CTRL (receive control) receive control signal.
RXDATA [3:0] (received data) 4-bit parallel received data signals.
In an actual application scenario, the MAC transmit data and the PHY receive data all need to be interconnected through PCB routing. For example, in a data transmission scenario, a data signal TXDATA and a clock signal TXCLK transmitted by a MAC are interconnected with a PHY chip through PCB routing, and due to inconsistent delay between the data and clock routing caused by PCB layout, PHY chip specification and manufacturing errors generated, etc., the data and clock bias is large, so that the PHY chip cannot sample correct data by using TXCLK. Similar problems exist for data transmission scenarios as well for data reception scenarios. In order to solve the above problem of interconnection between the MAC and the PHY, the conventional method is generally to adjust the fixed phase deviation by 90 °, but in the fixed phase adjustment mode, one fixed phase mode cannot adapt to compatible scenarios of PHY chips and PCB designs of different manufacturers, for example, if the data routing delay is greater than 90 ° phase, if the clock fixed phase adjustment is 90 °, data sampling errors will be caused.
Disclosure of Invention
The invention mainly aims to provide a clock phase adjusting method, an Ethernet data transmission method and related equipment, and aims to solve the technical problem that data sampling errors are caused by low compatibility of the existing RGMII interface to PHY chips and PCB designs of different factories.
The first aspect of the present invention provides a clock phase adjustment method, which is applied to an RGMII interface, and the clock phase adjustment method includes:
Acquiring a link state and a working transmission rate of an opposite chip;
If the link state is that the link is successfully established, determining the working clock frequency of the RGMII interface based on the working transmission rate;
setting an initial value of a counter and a counting overturning condition based on the chip clock frequency provided by a system chip and the working clock frequency of the RGMII interface;
Self-decrementing from the counter initial value;
when the value of the counter reaches the count-flip condition, a first clock signal and a second clock signal with phase deviation are generated.
Optionally, in a first implementation manner of the first aspect of the present invention, the clock phase adjustment method further includes:
When the value of the counter is reduced to 0, acquiring the latest work transmission rate of the opposite end chip again, and determining the latest work clock frequency of the RGMII based on the latest work transmission rate of the opposite end chip;
if the current latest work transmission rate changes, resetting a new initial value of a counter and a new counting turnover condition based on the chip clock frequency provided by the system chip and the latest work clock frequency of the RGMII interface;
starting self-decrementing from a new counter initial value;
when the new counter value reaches the new count-flip condition, a third clock signal and a fourth clock signal with phase deviations are generated.
Optionally, in a second implementation manner of the first aspect of the present invention, the clock phase adjustment method further includes:
If the current latest working transmission rate is not changed, continuing to self-count from the initial value of the counter set last time;
and when the value of the counter reaches the counting flip condition set last time, generating the first clock signal and the second clock signal with phase deviation.
Optionally, in a third implementation manner of the first aspect of the present invention, the first clock signal is in phase with the clock frequency of the chip and is used for driving to send a data signal or receiving a data signal, and the second clock signal is in phase with the first clock signal and is used for data sampling of the peer chip.
Optionally, in a fourth implementation manner of the first aspect of the present invention, a calculation formula of the initial value of the counter is as follows:
C0＝(F1/F2)-1;
Wherein, C 0 represents the initial value of the counter, F 1 represents the chip clock frequency provided by the system chip, and F 2 represents the operating clock frequency of the RGMII interface.
Optionally, in a fifth implementation manner of the first aspect of the present invention, the count flip condition is a whole division of a value of the counter to a flip threshold, and a calculation formula of the flip threshold is as follows:
N=(C0+1)/2;
Where N represents the flip threshold and C 0 represents the counter initial value.
The second aspect of the present invention provides an ethernet data transmission method, applied to an RGMII interface, where the ethernet data transmission method includes:
Generating a first clock signal and a second clock signal with phase deviation by adopting any one of the clock phase adjustment methods;
And based on the first clock signal and the second clock signal, performing Ethernet data transmission through the RGMII interface.
A third aspect of the present invention provides a clock phase adjustment device applied to an RGMII interface, the clock phase adjustment device including:
the acquisition module is used for acquiring the link state and the work transmission rate of the opposite end chip;
the determining module is used for determining the working clock frequency of the RGMII interface based on the working transmission rate if the link state is that the link is successfully established;
the counting module is used for setting a counter initial value and a counting turnover condition based on the chip clock frequency provided by the system chip and the working clock frequency of the RGMII interface, and starting self-decreasing counting from the counter initial value;
And the generation module is used for generating a first clock signal and a second clock signal with phase deviation when the value of the counter reaches the count flip condition.
Optionally, in a first implementation manner of the third aspect of the present invention, the obtaining module is further configured to re-obtain a latest working transmission rate of the peer chip when the value of the counter is reduced to 0;
The determining module is also used for determining the latest work clock frequency of the RGMII interface based on the latest work transmission rate of the opposite end chip;
the counting module is further used for resetting a new initial value of the counter and a new counting turnover condition based on the chip clock frequency provided by the system chip and the latest working clock frequency of the RGMII interface if the current latest working transmission rate changes, and starting self-decrementing from the new initial value of the counter;
the generation module is further configured to generate a third clock signal and a fourth clock signal having a phase deviation when the new counter value reaches a new count-flip condition.
Optionally, in a second implementation manner of the third aspect of the present invention, the counting module is further configured to continue to self-count from an initial value of the counter set last time if the current latest working transmission rate does not change;
the generation module is further used for generating the first clock signal and the second clock signal with phase deviation when the value of the counter reaches the count-up condition set last time.
Optionally, in a third implementation manner of the third aspect of the present invention, the first clock signal is in phase with the clock frequency of the chip and is used for driving to send a data signal or receiving a data signal, and the second clock signal is in phase with the first clock signal and is used for performing data sampling on the peer chip.
Optionally, in a fourth implementation manner of the third aspect of the present invention, a calculation formula of the initial value of the counter is as follows:
C0＝(F1/F2)-1;
Wherein, C 0 represents the initial value of the counter, F 1 represents the chip clock frequency provided by the system chip, and F 2 represents the operating clock frequency of the RGMII interface.
Optionally, in a fifth implementation manner of the third aspect of the present invention, the count flip condition is a whole division of a value of the counter to a flip threshold, and a calculation formula of the flip threshold is as follows:
N=(C0+1)/2;
Where N represents the flip threshold and C 0 represents the counter initial value.
In a fourth aspect, the present invention provides a computer device, including a memory and at least one processor, where the memory stores instructions, and the at least one processor invokes the instructions in the memory to cause the computer device to perform the clock phase adjustment method and/or the ethernet data transmission method described above.
A fourth aspect of the present invention provides a computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the above-described clock phase adjustment method, and/or ethernet data transmission method.
The invention provides a method for supporting flexible adjustment of clock phase, which is characterized in that the link state and the working transmission rate of an opposite end chip (PHY chip or MAC chip) are obtained, the initial value and the counting flip condition of a counter are further set, when the value of the counter reaches the counting flip condition, a first clock signal and a second clock signal with phase deviation are generated, and the first clock signal and the second clock signal are used for outputting data signals and clock signals of the PHY chip or the MAC chip, so that the timing problem of an RGMII interface is solved. According to the invention, the initial value and the counting overturning condition of the counter are customized, so that the self definition of the phase deviation of the data signal and the clock signal is realized, the RGMII interface can adapt to the interconnection scenes of various MAC chips and PHY chips, the compatibility of the network card chip is improved, and the problem of error sampling of the RGMII interface data is solved.
Drawings
FIG. 1 is a schematic diagram of an embodiment of an RGMII interface interconnect according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an embodiment of a method for adjusting clock phase according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another embodiment of a method for adjusting clock phase according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an embodiment of an Ethernet data transmission method according to the present invention;
FIG. 5 is a schematic diagram of an embodiment of a clock phase adjustment device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of one embodiment of a computer device in an embodiment of the invention.
Detailed Description
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating an embodiment of an RGMII interface interconnect. The RGMII interface is a physical layer interface standard for gigabit Ethernet, and is used for connecting an on-chip MAC end and a PHY end, so that the transmission of gigabit Ethernet data is realized. The RGMII interface transmits data and control signals between the MAC chip and the physical layer chip (i.e., PHY chip) through specific pins and signal lines. These signals include clock signals (TXC/RXC), data signals (TXD [3:0]/RXD [3:0 ]), and control signals (e.g., TX_EN/RX_DV). In practical applications, the RGMII interface may be implemented depending on the connection between the external PHY chip and the MAC controller, or may be implemented inside the SoC (system-on-a-chip) through the connection between the integrated MAC chip and PHY chip. The invention is described in particular with reference to the examples of the latter case.
The MAC chip (MEDIA ACCESS Control, medium access Control chip) is a component of the data link layer (DATA LINK LAYER) and is mainly responsible for functions such as encapsulation and decapsulation of data frames, error detection, and medium access Control. The MAC chip can determine whether data can be transmitted, and if the condition is satisfied, control information (e.g., source address, destination address, frame type, etc.) is added to the data and transmitted to a physical layer (PHY layer) in a prescribed format. When receiving data, the MAC chip firstly judges whether the input information has transmission errors, and if the input information has no transmission errors, the control information is removed, and the data is sent to a higher layer for processing.
The PHY chip (PHYSICAL LAYER CHIP ) is a component of the physical layer (PHYSICAL LAYER) and is mainly responsible for the functions of conversion between digital signals and analog signals, modulation and demodulation of signals, clock synchronization and the like. When the PHY chip transmits data, the digital signal transmitted by the MAC chip is converted into an analog signal and is transmitted through a transmission medium (such as a network cable). When receiving data, the PHY chip converts the received analog signals into digital signals and transmits the digital signals to the MAC chip for processing.
The network card chip is one of core components in the local area network of the computer, integrates a MAC chip and a PHY chip (or one of the MAC chip and the PHY chip) and related interface circuits, and is responsible for connecting the computer to a network to realize data transmission and network communication. The network card chip converts the digital signal of the computer into an analog signal suitable for network transmission through the integrated MAC chip and PHY chip, and sends the analog signal to the network through transmission media such as network cables.
For easy understanding, a specific flow of an embodiment of the present invention is described below, referring to fig. 2, and in an embodiment of the present invention, a clock phase adjustment method is applied to an RGMII interface, where the clock phase adjustment method includes:
201. Acquiring a link state and a working transmission rate of an opposite chip;
The peer chip of the present embodiment may be either a physical layer chip (for transmitting data) or a medium access control chip (for receiving data). The medium access control chip (i.e., MAC chip) or the physical layer chip (i.e., PHY chip) is typically connected to an upper layer device (e.g., link layer chip or processor) through interfaces (e.g., MDIO, MDC, etc.), so that a query command may be sent through these interfaces to directly read a status register or status bit of the physical layer chip or the medium access control chip, thereby obtaining link state information. Such status information may include whether the link is established, is in an active state, whether an error has occurred, and so on.
In a network environment such as ethernet, a physical layer chip or a medium access control chip generally supports an auto-negotiation function, so that a transmission rate and a duplex mode of a peer device can be automatically detected and matched. The current working transmission rate can be obtained by querying the result of the auto-negotiation. The physical layer chip or the medium access control chip typically has configuration registers for setting and storing configuration information of the device, including the operational transmission rate. By reading these configuration registers, the currently set working transmission rate can be acquired. Similar to obtaining the link state, the inquiry command may also be sent through interfaces such as MDIO and MDC, to directly read the register or the status bit related to the transmission rate in the physical layer chip or the medium access control chip, thereby obtaining the current working transmission rate.
202. If the link state is that the link is successfully established, determining the working clock frequency of the RGMII interface based on the working transmission rate;
In ethernet communication, when the link state of the physical layer chip or the medium access control chip is that the link is successfully created, the working clock frequency of the RGMII interface needs to be determined according to the working transmission rate of the physical layer chip or the medium access control chip. The operating clock frequency of the RGMII interface may be different for different operating transmission rates of the physical layer chip or the medium access control chip, but in practice in standard RGMII implementations, the clock frequency is typically fixed (e.g., 125 MHz) while data is transmitted on the rising or falling edge (or both) of the clock to achieve higher data transmission rates.
In this embodiment, when the link creation is successful and the working transmission rate is determined, the RGMII interface will use a fixed clock frequency (e.g. 125 MHz) and adapt to different transmission rates by adjusting the data coding and transmission scheme.
For example, when the working transmission rate of the physical layer chip or the medium access control chip is 1000Mbps, the RGMII interface adopts a working clock frequency of 125MHz, when the working transmission rate of the physical layer chip or the medium access control chip is 100Mbps, the RGMII interface adopts a working clock frequency of 25MHz, and when the working transmission rate of the physical layer chip or the medium access control chip is 10Mbps, the RGMII interface adopts a working clock frequency of 2.5 MHz.
203. Setting an initial value of a counter and a counting overturning condition based on the chip clock frequency provided by a system chip and the working clock frequency of the RGMII interface;
204. self-decrementing from the counter initial value;
The counter is set based on a chip clock frequency provided by a system on a chip (SoC) and an operating clock frequency of the RGMII interface, and the main purpose of the counter is to generate a clock signal required by the RGMII interface. Since the RGMII interface generally operates at a fixed clock frequency (e.g., 125MHz for gigabit ethernet), and the chip clock frequency of the SoC is much higher than the operating clock frequency of the RGMII interface, a counter is required to divide the high-frequency clock signal.
Frequency division refers to reducing the frequency of an input signal to a lower frequency. In digital circuits, a frequency divider is used to generate a plurality of low frequency clock signals from a high frequency reference clock signal to meet the requirements of different circuit modules. The implementation principle of the frequency divider depends on specific circuit design and application requirements. The basic principle of the digital frequency divider is that the digital circuit elements such as a counter and a register count and logically process an input signal, so as to obtain an output signal with reduced frequency.
In the case of self-countdown, the counter may be counting from an initial value greater than, less than, or equal to the frequency division ratio. For example, assuming that the clock frequency of the SoC is 500MHz and the RGMII interface requires a 125MHz clock for operation, the frequency division ratio between the clock frequency of the SoC chip and the RGMII interface operation clock frequency is 4 (500 MHz/125 mhz=4), the counter initial value may be counted from 3 or 4 or 5.
Since the present embodiment divides the frequency based on the chip clock frequency provided by the system chip, the counter self-decrements every SoC clock cycle. The count-flip condition refers to when the counter should be flipped (i.e., reset to an initial value or some new value) to generate the required clock signal.
In an embodiment, the calculation formula of the initial value of the counter is as follows:
c 0＝(F1/F2) -1 (equation 1)
Wherein, C 0 represents the initial value of the counter, F 1 represents the chip clock frequency provided by the system chip, and F 2 represents the operating clock frequency of the RGMII interface.
For example, assuming that the SoC chip provides a chip clock frequency of 500M, if the PHY chip or the MAC chip negotiates that the working transmission rate is 1000Mbps, the working clock frequency of the RGMII interface may be determined to be 125MHz based on the transmission protocol, and then the initial value of the counter may be calculated to be 3 through the above formula 1, that is, the counter starts to count down from 3 each time.
In an embodiment, the count-flip condition is a whole division of a value of a counter to a flip threshold, and a calculation formula of the flip threshold is as follows:
n= (C 0 +1)/2 (formula 2)
Where N represents the flip threshold and C 0 represents the counter initial value.
Continuing with the above example, if the initial value of the counter calculated by equation 1 is 3, then the flip threshold calculated by equation 2 is 2, i.e., when the value of the counter divides 2 by one, the generation of the clock signal will be triggered.
As can be seen from the above, the initial value of the counter is not only related to the chip clock frequency of the system chip and the working clock frequency of the RGMII interface, but also related to the working transmission rate adopted by the PHY chip or the MAC chip in negotiation, that is, the embodiment can dynamically adjust the initial value of the counter based on the negotiation rate of the PHY chip or the MAC chip, and further adjust the counting flip condition, thereby realizing the phase deviation control of the output clock signal, and further solving the problem of data sampling errors caused by the phase deviation of clock data of the RGMII interface.
205. When the value of the counter reaches the count-flip condition, a first clock signal and a second clock signal with phase deviation are generated.
The clock signal (e.g., TXCLK, RXCLK) of the RGMII interface is not directly provided by the RGMII interface itself, but by a PHY chip or MAC chip connected to the RGMII interface. These clock signals are used to synchronize the transmission and reception of data. The PHY chip or MAC chip typically contains clock generation circuitry within it that can generate the required clock signal based on an external reference clock (e.g., crystal oscillator). According to actual needs, the clock generation circuit can perform frequency division or frequency multiplication operation on the external reference clock so as to generate a clock signal meeting the RGMII interface requirement. In some cases, the clock signal may also need to be phase adjusted in order to stay synchronized with the data signal or to meet specific timing requirements, in particular by adjusting the delay or phase offset of the clock signal.
In this embodiment, when the value of the counter does not reach the set flip condition, the current clock signal state is not generated or maintained. And when the value of the counter reaches the set flip condition, the clock signal generation logic is triggered. For example, assuming that the initial value of the counter is 3, the count flip is adjusted to be the integer division of the value of the counter by 2, when the value of the counter is 2, the flip condition is reached at this time, and the generation of the first clock signal and the second clock signal with phase deviation is triggered.
The clock source used to generate the clock signal in this embodiment preferably uses the clock frequency of the SoC.
In one embodiment, the first clock signal is generated in phase with the chip clock frequency for driving the transmit data signals (e.g., TXDATA and TX_CTRL as shown in FIG. 1) or the receive data signals (e.g., RXDATA and RX_CTRL as shown in FIG. 1), the second clock signal is generated in phase with the first clock signal for data sampling by the peer chip (i.e., the second clock signal is the TXCLK input of the PHY chip, the PHY chip samples TXDATA and TX_CTRL with the second clock signal, or the second clock signal is the RXCLK input of the MAC chip, and the MAC chip samples RXDATA and RX_CTRL with the second clock signal).
In this embodiment, the delay processing is performed on the first clock signal, so as to implement an adjustable phase deviation between the first clock signal and the second clock signal. The amount of delay determines the phase offset between the two clock signals. The delay may be implemented in a variety of ways, such as using Digital Delay Lines (DDL), FIFO buffers, D flip-flop chains, and the like. The required delay time may be calculated in particular from the required phase deviation and the frequency of the clock signal. For example, if the clock frequency is 125MHz (period is 8 ns), and a phase deviation of 1ns is required, the amount of delay required is 1ns.
The embodiment realizes a method for supporting flexible adjustment of clock phase, by acquiring the link state and the working transmission rate of an opposite end chip (PHY chip or MAC chip), further setting the initial value and the counting flip condition of a counter, and generating a first clock signal and a second clock signal with phase deviation when the value of the counter reaches the counting flip condition for outputting data signals and clock signals of the PHY chip or the MAC chip, thereby solving the timing problem of an RGMII interface. According to the embodiment, the initial value and the counting overturning condition of the counter are customized, so that the self definition of the phase deviation of the data signal and the clock signal is further realized, the RGMII interface can adapt to the interconnection scenes of various MAC chips and PHY chips, the compatibility of network card chips is improved, and the problem of error in data sampling of the RGMII interface is solved.
Referring to fig. 3, fig. 3 is a schematic diagram of another embodiment of a clock phase adjustment method according to the present invention. In this embodiment, the clock phase adjustment method includes:
301. Acquiring a link state and a working transmission rate of an opposite chip;
302. if the link state is that the link is successfully established, determining the working clock frequency of the RGMII interface based on the working transmission rate;
303. Setting an initial value of a counter and a counting overturning condition based on the chip clock frequency provided by a system chip and the working clock frequency of the RGMII interface;
304. self-decrementing from the counter initial value;
305. When the value of the counter reaches the counting flip condition, generating a first clock signal and a second clock signal with phase deviation;
In this embodiment, the steps 301-305 are the same as the steps 201-205 in the previous embodiment, and thus will not be repeated.
306. When the value of the counter is reduced to 0, acquiring the latest work transmission rate of the opposite end chip again, and determining the latest work clock frequency of the RGMII based on the latest work transmission rate of the opposite end chip;
In this embodiment, since the clock signal is generated based on the counter, when the value of the counter is self-reduced to 0, a new counter initial value and a new count-up condition need to be reset, which is usually directly used for the counter initial value and the count-up condition that were used last time. In this embodiment, the possible change of the working transmission rate of the opposite chip is considered, so that the subsequent RGMII interface timing sequence is affected, and therefore, the latest working transmission rate of the opposite chip needs to be obtained again, and the latest working clock frequency of the RGMII interface is determined.
307. If the current latest work transmission rate changes, resetting a new initial value of a counter and a new counting turnover condition based on the chip clock frequency provided by the system chip and the latest work clock frequency of the RGMII interface;
308. Starting self-decrementing from a new counter initial value;
309. when the new counter value reaches the new count-flip condition, a third clock signal and a fourth clock signal with phase deviations are generated.
In this embodiment, if the working transmission rate of the current physical layer chip or the mac chip changes, a new counter initial value and a new count-up condition are reset, and a self-down count is started from the new counter initial value, and when the new counter value reaches the new count-up condition, a third clock signal and a fourth clock signal with phase deviation are generated.
For example, in steps 301 and 302, the working transmission rate of the physical layer chip or the medium access control chip is 1000mbps, and the working clock frequency of the rgmii interface is 125MHz, then the counter initial value required to be set in step 303 is 3, the count flip condition is that 2 is divided, and the count is self-reduced from the counter initial value 3. In step 305, when the counter reaches the count-down condition (e.g., the counter value is 2), a first clock signal and a second clock signal with a phase deviation are generated.
In step 306, when the self-subtracted value of the counter becomes 0, the latest working transmission rate of the peer physical layer chip or the medium access control chip is re-acquired, if the working transmission rate is changed, the new counter initial value is reset to 19 in step 307, the new count-up condition is that 10 is divided, and the self-subtraction count is started from the new counter initial value 19. When the new counter reaches a new count-flip condition (e.g., a counter value of 10) from the decremented value, a third clock signal and a fourth clock signal are generated having a phase offset.
In an embodiment, if the latest working transmission rate of the current physical layer chip or the media access control chip is not changed, the self-decreasing count is continuously started from the initial value of the counter set last time, and when the value of the counter reaches the count inversion condition set last time, the first clock signal and the second clock signal with phase deviation are generated.
In this embodiment, when the value of the counter is reduced from 0, if the latest working transmission rate of the current physical layer chip or the mac chip is unchanged, the counter initial value and the count-up condition set last time are continuously adopted, and when the value of the counter reaches the count-up condition set, the first clock signal and the second clock signal with phase deviation are generated.
According to the embodiment, the initial value of the counter and the counting turnover condition are correspondingly adjusted according to the change of the working transmission rate of the physical layer chip or the media access control chip, and the self definition of the phase deviation of the data signal and the clock signal is further realized by self defining the initial value of the counter and the counting turnover condition, so that the RGMII interface can adapt to the interconnection scenes of various MAC chips and PHY chips, the compatibility of the network card chip is improved, and the problem of error sampling of the RGMII interface data is solved.
Referring to fig. 4, fig. 4 is a schematic diagram of another embodiment of an ethernet data transmission method according to the present invention. The embodiment is applied to an RGMII interface, and the Ethernet data transmission comprises the following steps:
401. generating a first clock signal and a second clock signal with phase deviation by adopting a clock phase adjustment method;
402. And based on the first clock signal and the second clock signal, performing Ethernet data transmission through the RGMII interface.
The data signal TXDATA and the clock signal TXCLK sent by the MAC chip are interconnected with the PHY chip through the PCB wiring, and the data signal RXDATA and the clock signal RXCLK sent by the PHY chip are interconnected with the MAC chip through the PCB wiring. Because of inconsistent data and clock routing delays caused by the PCB layout, the PHY chip specification, the production errors and the like can cause great data and clock deviation, so that the PHY chip or the MAC chip cannot sample correct data by using TXCLK or RXCLK.
In this embodiment, in order to solve the problem that the compatibility of the existing RGMII interface to PHY chips and PCB boards of different manufacturers is not high, so that data sampling errors are caused, the clock phase adjustment method described in the above embodiment is adopted to generate the first clock signal and the second clock signal with phase deviation, and the RGMII interface can normally perform ethernet data transmission based on the generated first clock signal and the generated second clock signal with phase deviation, so as to ensure accuracy of data transmission.
The clock phase adjusting method and the ethernet data transmission method in the embodiments of the present invention are described above, and the clock phase adjusting device in the embodiments of the present invention is described below, referring to fig. 5, where an embodiment of the clock phase adjusting device in the embodiments of the present invention includes:
An obtaining module 501, configured to obtain a link state and a working transmission rate of an opposite chip;
A determining module 502, configured to determine, based on the working transmission rate, a working clock frequency of the RGMII interface if the link state is that the link creation is successful;
A counting module 503, configured to set a counter initial value and a count flip condition based on a chip clock frequency provided by a system chip and a working clock frequency of the RGMII interface, and start self-decrementing from the counter initial value;
a generating module 504, configured to generate a first clock signal and a second clock signal with a phase deviation when the value of the counter reaches the count-flip condition.
Optionally, in an embodiment, the obtaining module 501 is further configured to re-obtain the latest working transmission rate of the peer chip when the value of the counter is reduced to 0;
the determining module 502 is further configured to determine a latest working clock frequency of the RGMII interface based on a latest working transmission rate of the peer chip;
The counting module 503 is further configured to reset a new counter initial value and a new count-up condition based on a chip clock frequency provided by a system chip and a latest working clock frequency of the RGMII interface if a current latest working transmission rate changes, and start self-decrementing from the new counter initial value;
the generating module 504 is further configured to generate a third clock signal and a fourth clock signal having a phase deviation when the new counter value reaches a new count-flip condition.
Optionally, in an embodiment, the counting module 503 is further configured to continue to count down from the initial value of the counter set last time if the current latest working transmission rate has not changed;
the generating module 504 is further configured to generate the first clock signal and the second clock signal with a phase deviation when the value of the counter reaches a count-flip condition set last time.
Optionally, in an embodiment, the first clock signal is in phase with the clock frequency of the chip and is used for driving a sending data signal or receiving a data signal, and the second clock signal is in phase with the first clock signal and is used for data sampling of the opposite chip.
Optionally, in a fourth implementation manner of the third aspect of the present invention, a calculation formula of the initial value of the counter is as follows:
C0＝(F1/F2)-1;
Wherein, C 0 represents the initial value of the counter, F 1 represents the chip clock frequency provided by the system chip, and F 2 represents the operating clock frequency of the RGMII interface.
Optionally, in an embodiment, the count-flip condition is a whole division of a value of the counter to a flip threshold, and a calculation formula of the flip threshold is as follows:
N=(C0+1)/2;
Where N represents the flip threshold and C 0 represents the counter initial value.
Since the embodiments of the device portion correspond to the embodiments of the method described above, the description of the clock phase adjusting device provided by the present invention refers to the embodiments of the method described above, and the present invention is not repeated herein, and has the same beneficial effects as the clock phase adjusting method described above.
The clock phase adjusting device in the embodiment of the present invention is described in detail above in fig. 5 from the point of view of the modularized functional entity, and the computer device in the embodiment of the present invention is described in detail below from the point of view of hardware processing.
Fig. 6 is a schematic diagram of a computer device according to an embodiment of the present invention, where the computer device 600 may have a relatively large difference due to configuration or performance, and may include one or more processors (central processing units, CPU) 610 (e.g., one or more processors) and a memory 620, and one or more storage mediums 630 (e.g., one or more mass storage devices) storing applications 633 or data 632. Wherein the memory 620 and the storage medium 630 may be transitory or persistent storage. The program stored on the storage medium 630 may include one or more modules (not shown), each of which may include a series of instruction operations in the computer device 600. Still further, the processor 610 may be configured to communicate with a storage medium 630 and execute a series of instruction operations in the storage medium 630 on the computer device 600.
The computer device 600 may also include one or more power supplies 640, one or more wired or wireless network interfaces 650, one or more input/output interfaces 660, and/or one or more operating systems 631, such as Windows Serve, mac OS X, unix, linux, freeBSD, and the like. It will be appreciated by those skilled in the art that the computer device structure shown in FIG. 6 is not limiting of the computer device and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
The present invention also provides a computer device, where the computer device includes a memory and a processor, where the memory stores computer readable instructions that, when executed by the processor, cause the processor to perform the clock phase adjustment method and/or the ethernet data transmission method steps in the foregoing embodiments.
The present invention also provides a computer readable storage medium, which may be a non-volatile computer readable storage medium, or a volatile computer readable storage medium, having stored therein instructions that, when executed on a computer, cause the computer to perform the steps of the clock phase adjustment method, and/or the ethernet data transmission method.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
While the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that the foregoing embodiments may be modified or equivalents may be substituted for some of the features thereof, and that the modifications or substitutions do not depart from the spirit and scope of the embodiments of the invention.
Claims (10)
1. The clock phase adjusting method is applied to an RGMII interface, and is characterized by comprising the following steps of:
Acquiring a link state and a working transmission rate of an opposite chip;
If the link state is that the link is successfully established, determining the working clock frequency of the RGMII interface based on the working transmission rate;
setting an initial value of a counter and a counting overturning condition based on the chip clock frequency provided by a system chip and the working clock frequency of the RGMII interface;
Self-decrementing from the counter initial value;
when the value of the counter reaches the count-flip condition, a first clock signal and a second clock signal with phase deviation are generated.
2. The clock phase adjustment method according to claim 1, characterized in that the clock phase adjustment method further comprises:
When the value of the counter is reduced to 0, acquiring the latest work transmission rate of the opposite end chip again, and determining the latest work clock frequency of the RGMII based on the latest work transmission rate of the opposite end chip;
if the current latest work transmission rate changes, resetting a new initial value of a counter and a new counting turnover condition based on the chip clock frequency provided by the system chip and the latest work clock frequency of the RGMII interface;
starting self-decrementing from a new counter initial value;
when the new counter value reaches the new count-flip condition, a third clock signal and a fourth clock signal with phase deviations are generated.
3. The clock phase adjustment method according to claim 2, characterized in that the clock phase adjustment method further comprises:
If the current latest working transmission rate is not changed, continuing to self-count from the initial value of the counter set last time;
and when the value of the counter reaches the counting flip condition set last time, generating the first clock signal and the second clock signal with phase deviation.
4. The method of claim 1, wherein the first clock signal is in phase with the chip clock frequency for driving a transmit data signal or a receive data signal, and the second clock signal is in phase with the first clock signal for data sampling by the peer chip.
5. A clock phase adjustment method according to any one of claims 1-3, characterized in that the counter initial value is calculated as follows:
C0＝(F1/F2)-1;
Wherein, C 0 represents the initial value of the counter, F 1 represents the chip clock frequency provided by the system chip, and F 2 represents the operating clock frequency of the RGMII interface.
6. The method of claim 5, wherein the count flip condition is a whole division of a value of a counter by a flip threshold, and a calculation formula of the flip threshold is as follows:
N=(C0+1)/2;
Where N represents the flip threshold and C 0 represents the counter initial value.
7. The Ethernet data transmission method is applied to an RGMII interface and is characterized by comprising the following steps:
generating a first clock signal and a second clock signal with a phase deviation using the clock phase adjustment method of any one of claims 1-6;
And based on the first clock signal and the second clock signal, performing Ethernet data transmission through the RGMII interface.
8. A clock phase adjustment device applied to an RGMII interface, the clock phase adjustment device comprising:
the acquisition module is used for acquiring the link state and the work transmission rate of the opposite end chip;
the determining module is used for determining the working clock frequency of the RGMII interface based on the working transmission rate if the link state is that the link is successfully established;
the counting module is used for setting a counter initial value and a counting turnover condition based on the chip clock frequency provided by the system chip and the working clock frequency of the RGMII interface, and starting self-decreasing counting from the counter initial value;
And the generation module is used for generating a first clock signal and a second clock signal with phase deviation when the value of the counter reaches the count flip condition.
9. A computer device comprising a memory and at least one processor, the memory having instructions stored therein;
The at least one processor invoking the instructions in the memory to cause the computer device to perform the clock phase adjustment method of any of claims 1-6, and/or the ethernet data transmission method of claim 7.
10. A computer readable storage medium having instructions stored thereon, which when executed by a processor, implement the clock phase adjustment method of any one of claims 1-6, and/or the ethernet data transmission method of claim 7.
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| CN202411418051.6A CN119621626A (en) | 2024-10-11 | 2024-10-11 | Clock phase adjustment method, Ethernet data transmission method and related equipment |
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| CN202411418051.6A CN119621626A (en) | 2024-10-11 | 2024-10-11 | Clock phase adjustment method, Ethernet data transmission method and related equipment |
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| JPH1188309A (en) * | 1997-07-15 | 1999-03-30 | Nec Corp | Phase adjustment circuit for data and clock |
| CN104199341A (en) * | 2014-08-11 | 2014-12-10 | 福州瑞芯微电子有限公司 | Electric circuit signal phase adaptive system, device and method |
| CN106788566A (en) * | 2016-12-30 | 2017-05-31 | 合肥国为电子有限公司 | Transceiver and transmission method based on ethernet physical layer chip rate continuous variable |
| CN110188052A (en) * | 2019-05-15 | 2019-08-30 | 晶晨半导体(上海)股份有限公司 | It is a kind of for improving the method and device of RGMII interface stability |
| CN116931658A (en) * | 2023-07-31 | 2023-10-24 | 成都中微达信科技有限公司 | Multi-board synchronous clock architecture and method based on digital-to-analog converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH1188309A (en) * | 1997-07-15 | 1999-03-30 | Nec Corp | Phase adjustment circuit for data and clock |
| CN104199341A (en) * | 2014-08-11 | 2014-12-10 | 福州瑞芯微电子有限公司 | Electric circuit signal phase adaptive system, device and method |
| CN106788566A (en) * | 2016-12-30 | 2017-05-31 | 合肥国为电子有限公司 | Transceiver and transmission method based on ethernet physical layer chip rate continuous variable |
| CN110188052A (en) * | 2019-05-15 | 2019-08-30 | 晶晨半导体(上海)股份有限公司 | It is a kind of for improving the method and device of RGMII interface stability |
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