CN119630045A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device and a method of fabricating the same, the semiconductor device including a semiconductor layer having opposite first and second surfaces, the semiconductor layer being located in a trench of the first surface of the semiconductor layer, the semiconductor layer including a first buried layer located at a bottom of the trench gate and connected to the trench gate, a body region connected to a sidewall of the trench gate, a source region connected to the sidewall of the trench gate, the source region extending from the first surface toward the body region and connected to the body region, and a drift region at least a portion of the drift region being located between the body region and the second surface and connected to the first buried layer and the body region, wherein a width of the trench gate is not less than a depth of the trench gate and a width of the trench gate is greater than a width of the first buried layer. By widening the width of the trench gate and arranging a narrower buried layer at the bottom of the trench gate, the obstruction of the buried layer to carrier flow is reduced, and the overall voltage endurance capacity of the device is improved.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor device technology, and more particularly, to a semiconductor device having a trench gate structure and a method of manufacturing the same.

Background

In a vertical transistor with a trench gate, the drain of the transistor needs to be able to withstand high voltages. Because PN junction exists between the drain electrode and the source electrode, the high-voltage-resistant power supply has better bearing capacity with high voltage.

However, between the drain and the trench gate, high voltage is not easily sustained due to the gate dielectric layer. Particularly, the high voltage resistance is poor at the bottom and corners of the trench gate, and the overall voltage resistance of the device is reduced. Accordingly, improvements in devices are needed to ameliorate the above problems.

Disclosure of Invention

In view of the foregoing, an object of the present disclosure is to provide a semiconductor device and a method of manufacturing the same, which reduces the obstruction of carrier flow by a buried layer by widening the width of a trench gate and providing a narrower buried layer at the bottom thereof, and improves the overall withstand voltage capability of the device.

According to an aspect of an embodiment of the present disclosure, there is provided a semiconductor device including a semiconductor layer having opposite first and second surfaces, and a trench gate in a trench of the first surface of the semiconductor layer,

The semiconductor layer includes:

the first buried layer is positioned at the bottom of the trench gate and is connected with the trench gate;

The body region is connected with the side wall of the trench gate;

A source region connected to the sidewall of the trench gate and extending from the first surface toward the body region and connected to the body region, and

A drift region, at least part of which is located between the body region and the second surface and is connected with the first buried layer and the body region,

The width of the groove gate is not smaller than the depth of the groove gate, and the width of the groove gate is larger than the width of the first buried layer.

Optionally, the source region and the drift region are of a first conductivity type, the first buried layer and the body region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

Optionally, the semiconductor layer further includes a second buried layer, which is separated from the trench gate and the first buried layer, respectively, the second buried layer and the first buried layer being of the same conductivity type,

The body region is located between the second buried layer and the first surface and connected with the second buried layer, and the drift region is connected with the second buried layer.

Optionally, the first buried layer is flush with the bottom of the second buried layer.

Optionally, the first buried layer and the second buried layer both extend along a length direction of the trench gate.

Optionally, along the width direction of the trench gate, the body region, the source region and the second buried layer are all located at two sides of the trench gate.

Optionally, the semiconductor layer further includes a third buried layer located between the first buried layer and the second buried layer and connected to the first buried layer, the second buried layer and the body region, and the third buried layer has a conductivity type identical to that of the first buried layer.

Optionally, a plurality of third buried layers are arranged at intervals along the length direction of the trench gate.

Optionally, the spacing distance between adjacent third buried layers is greater than the length of the third buried layers along the length direction of the trench gate.

Optionally, the third buried layer is flush with the bottom of the first buried layer.

Optionally, a plurality of the trench gates are arranged at intervals along the length direction of the trench gate,

And along the length direction of the trench gate, the body region and the source region are also positioned between adjacent trench gates.

Optionally, along the length direction of the trench gate, a spacing region between adjacent trench gates corresponds to a part of the third buried layer.

Optionally, the trench gate extends continuously along a length direction of the trench gate.

According to another aspect of the embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, including:

forming a first buried layer in a semiconductor layer, the semiconductor layer having opposite first and second surfaces, the first buried layer having a preset distance to the first surface;

forming a well region in the semiconductor layer, wherein the well region extends from the first surface towards the first buried layer and is connected with the first buried layer;

Forming a doped region in the well region, the doped region extending from the first surface into the well region, and

Forming a trench extending from the first surface to the first buried layer, and forming a trench gate in the trench,

The width of the groove gate is not smaller than the depth of the groove gate, and the width of the groove gate is larger than the width of the first buried layer.

Optionally, forming a second buried layer in the semiconductor layer,

The second buried layer is separated from the trench gate and the first buried layer respectively, and the well region is located between the second buried layer and the first surface and connected with the second buried layer.

Optionally, forming a third buried layer in the semiconductor layer,

The third buried layer is located between the first buried layer and the second buried layer and is connected with the first buried layer, the second buried layer and the well region.

Optionally, the first buried layer, the second buried layer and the third buried layer are formed simultaneously by adopting an ion implantation process.

One of the above technical solutions has the following beneficial effects:

Through setting up first buried layer in the bottom of trench gate, increase the withstand voltage ability of the bottom of trench gate to set the width of trench gate to be not less than the degree of depth of trench gate, compare in the narrow slot scheme that trench gate width is less than the degree of depth, this scheme has widened the width of trench gate, thereby can realize that first buried layer only contacts with trench gate bottom, and can not wrap up the corner of trench gate, greatly reduced the hindrance of first buried layer to carrier flow, thereby reduced the on-resistance of device.

In some embodiments, the body region and the source region are disposed on two sides of the trench gate and connected to the sidewalls of the trench gate, so that two sides of the trench gate can be used as a conductive channel (channel), thereby reducing the resistance of the device in the on state.

In some embodiments, the second buried layers are arranged on two sides of the trench gate, so that the problem of electric field concentration at the corners of the trench gate is solved, and the voltage withstanding capability at the corners of the trench gate is improved.

In some embodiments, the third buried layer is arranged to realize the electric connection between the first buried layer and the source region, so that the first buried layer is not in a floating state any more, and the electric field shielding function of the first buried layer to the bottom of the trench gate is more stable.

In some embodiments, third buried layers are arranged at intervals along the length direction of the trench gate, so that the electric field shielding function of the first buried layer on the bottom of the trench gate can be stabilized, and the current distribution between the source and the drain can be laid out by utilizing an interval region between adjacent third buried layers.

In some embodiments, the first buried layer, the second buried layer and the third buried layer are formed in the semiconductor layer simultaneously by adopting an ion implantation process, so that the number of mask plates is reduced, patterns of the first buried layer to the third buried layer are not required to be additionally aligned, the process difficulty is reduced, and the cost is saved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will make it apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

Fig. 1 shows a schematic top view of a semiconductor device according to a first embodiment of the present disclosure.

Fig. 2 shows a schematic cross-sectional view taken along line AA in fig. 1.

Fig. 3 shows a schematic cross-sectional structure taken along the line BB in fig. 1.

Fig. 4 shows a schematic top view of a semiconductor device according to a second embodiment of the present disclosure.

Fig. 5 to 9 are schematic perspective views showing a part of stages in the manufacturing method of the semiconductor device of the first embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.

It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.

If, for the purposes of describing a situation directly on top of another layer, another area, expressions such as "directly on top of" or "on top of and adjacent to" will be used herein.

Power devices typically include an active element region, an edge termination region, and a crack-stop (or shield) region. The active element region includes an active element array. The present disclosure relates to active element structures. The dimensions of the active elements may vary depending on the product requirements and there may be body regions between the active elements in the active element region.

Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

In a vertical transistor, such as a SiC MOSFET, it is necessary to be able to withstand a high voltage applied to the drain. Because PN junction exists between the drain electrode and the source electrode, the high-voltage-resistant power supply has better bearing capacity with high voltage. However, between the drain and the trench gate, high voltage is not easily sustained due to the gate dielectric layer. Particularly, the high voltage resistance of the gate dielectric layer is poor at the bottom and corners of the trench gate, and a shielding structure is required to be designed separately. In order to improve the above problems, an object of the present disclosure is to provide a semiconductor device, by widening the width of a trench gate and disposing a narrower buried layer at the bottom thereof, not only the overall withstand voltage capability of the device is improved, but also the obstruction of the buried layer to carrier flow is reduced.

Fig. 1 shows a schematic top view of a semiconductor device according to a first embodiment of the present disclosure, fig. 2 shows a schematic cross-sectional structure taken along line AA in fig. 1, fig. 3 shows a schematic cross-sectional structure taken along line BB in fig. 1, wherein fig. 1 shows only buried layers and trench gates, and other structures are omitted to more clearly express the positional relationship between the respective structures.

As shown in fig. 1 to 3, the semiconductor device of the first embodiment of the present disclosure includes a semiconductor layer, a plurality of trench gates 150, an interlayer dielectric layer 160, a first conductive layer 171, and a second conductive layer 172. The semiconductor layer has opposing first and second surfaces 101, 102 and a plurality of trenches extending into the semiconductor layer from the first surface 101 toward the second surface 102. A plurality of trench gates 150 are located in the corresponding trenches. The semiconductor layer is, for example, siC, gaN, ga ₂O₃、Al₂O₃ substrate or a stacked structure of substrate and epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may perform other settings on the material of the semiconductor layer, the number of layers, such as other wide bandgap semiconductor materials, etc., as required.

The semiconductor layer includes a drift region 110, a first buried layer 121, a second buried layer 122, a third buried layer 123, a body region 131, a source region 141, and a body contact region 142. Wherein the source region 141 and the drift region 110 are of the first conductivity type, and the first buried layer 121, the second buried layer 122, the third buried layer 123, the body region 131 and the body contact region 142 are of the second conductivity type, and the doping concentration of the body contact region 142 is greater than the doping concentration of the body region 131. The first conductivity type is opposite to the second conductivity type. The first conductivity type is one of P-type and N-type, and the second conductivity type is the other of P-type and N-type.

The semiconductor device of the present embodiment may be used as a Metal-Oxide-semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example, a drain contact region is provided on the second surface 102 of the semiconductor layer, and the conductivity type of the drain contact region is set to be the first conductivity type or the second conductivity type, respectively. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other settings of the conductivity type of each region in the semiconductor layer as needed to make the semiconductor device a MOSFET or an IGBT.

Trench gate 150 includes a gate dielectric layer 151 and a gate conductor 152. A gate dielectric layer 151 covers the inner surface of the trench in which the gate conductor 152 is located. A gate dielectric layer 151 is located between the semiconductor layer and the gate conductor 152 for separating the semiconductor layer from the gate conductor 152. The width direction of the trench gate 150 is the X-axis direction, the depth direction is the Z-axis direction, and the length direction is the Y-axis direction, and optionally, the X-axis, Y-axis, and Z-axis directions are perpendicular to each other.

The first buried layer 121 is located at the bottom of the trench gate 150. The second buried layer 122, the body region 131, the source region 141, and the body contact region 142 are located at both sides of the trench gate 150 in the X-axis direction.

The first buried layer 121 is connected to the trench gate 150, where the trench gate 150 is a wide trench structure, and the width of the trench gate 150 is not smaller than the depth of the trench gate 150, so that in an actual manufacturing process, the width of the first buried layer 121 can be smaller than the width of the trench gate 150, and further, the first buried layer 121 is only located at the bottom of the trench gate 150 and does not wrap around corners of the trench gate 150. In some specific embodiments, the depth of trench gate 150 is less than the width of trench gate 150, and the depth of first buried layer 121 is greater than the depth of trench gate 150.

The first buried layer 121 and the second buried layer 122 each extend in the Y-axis direction and are separated from each other. The second buried layer 122 is not connected to the trench gate 150. The third buried layer 123 is located between the first buried layer 121 and the second buried layer 122 in the X-axis direction, and connects the first buried layer 121 and the second buried layer 122, respectively. The plurality of third buried layers 123 are disposed at intervals along the Y-axis direction. Alternatively, the spacing distance Sp of adjacent third buried layers 123 is greater than the length Wp of the third buried layers 123. Alternatively, the bottoms of the first buried layer 121, the second buried layer 122, and the third buried layer 123 are flush. Alternatively, in the XY plane, the third buried layer 123 may extend along the X axis or may extend at a predetermined angle with respect to the X axis.

The body region 131 is connected to both sidewalls of the trench gate 150 and the second buried layer 122, respectively, along the X-axis direction. The source region 141 extends from the first surface 101 of the semiconductor layer toward the body region 131 and is connected to the body region 131. The body contact region 142 extends from the first surface 101 of the semiconductor layer in the direction of the body region 131 and is connected to the body region 131. Alternatively, the source region 141 and the body contact region 142 may be connected or may be separated by the body region 131. At least a portion of the drift region 110 is located between the body region 131 and the second surface 102 of the semiconductor layer and is connected to the first buried layer 121, the second buried layer 122, the third buried layer 123 and the body region 131.

An interlayer dielectric layer 160 is located on the first surface 101 of the semiconductor layer and covers the trench gate 150. The first conductive layer 171 serves as a source electrode and covers the first surface 101 of the semiconductor layer and the interlayer dielectric layer 160. The second conductive layer 172 serves as a drain electrode covering the second surface 102 of the semiconductor layer.

In the present embodiment, the plurality of trench gates 150 are spaced apart in the Y-axis direction, and the body region 131 and the source region 141 are further located between adjacent trench gates 150 in the Y-axis direction. Alternatively, in the Y-axis direction, the spacing region between adjacent trench gates 150 corresponds to a portion of the third buried layer 123.

In this embodiment, when the device is turned on, the portion of the body region 131 adjacent to the sidewall of the trench gate 150 is inverted to form a channel, and carriers flow from the source (the first conductive layer 171) and then flow to the drift region 110 via the source region 141 and the channel, and finally flow out from the drain (the second conductive layer 172), see a carrier flow path shown by a dotted line in fig. 1.

By arranging the first buried layer 121 at the bottom of the trench gate 150, the first buried layer 121 and the drift region 110 form a PN junction, so that the voltage withstand capability of the bottom of the trench gate 150 is increased, and the trench gate 150 is arranged to be a wide trench structure with a width not smaller than the depth.

Further, by disposing the body region 131 and the source region 141 on both sides of the trench gate 150 and connecting the body region and the walls of the trench gate 150, both sides of the trench gate 150 can be used as conductive channels (channels), so that the resistance of the device in the on state is reduced.

Further, by providing the second buried layer 122 at both sides of the trench gate 150, the problem of electric field concentration at the corners of the trench gate 150 is improved, and the withstand voltage capability at the corners of the trench gate 150 is increased.

Further, by providing the third buried layer 123, the first buried layer 121 is electrically connected with the source region 141, so that the first buried layer 141 is not in a floating state any more, and the electric field shielding function of the first buried layer 121 to the bottom of the trench gate 150 is more stable.

Further, the third buried layers 123 are arranged at intervals along the Y-axis direction, so that not only can the electric field shielding function of the first buried layer 121 on the bottom of the trench gate 150 be stabilized, but also the current distribution between the source and the drain can be laid out by utilizing the interval area between the adjacent third buried layers 123. Referring to fig. 1 and 2, carriers flowing out of the conductive channels on both sides of the trench gate 150 are uniformly diffused throughout the drift region 110 through the individual regions surrounded by the first, second and third buried layers 121, 122 and 123, thereby exhibiting low on-resistance.

Fig. 4 shows a schematic top view of a semiconductor device according to a second embodiment of the present disclosure.

As shown in fig. 4, the semiconductor device of the second embodiment of the present disclosure is the same as that of the first embodiment and will not be described again here, and reference is made to the description about fig. 1 to 3. Except that in this embodiment, the trench gate 150 extends continuously in the Y-axis direction.

Fig. 5 to 9 are schematic perspective views showing a part of stages in the manufacturing method of the semiconductor device of the first embodiment of the present disclosure.

Referring to fig. 5, an epitaxial layer 104 is formed on a substrate 103 using an epitaxial process, wherein the epitaxial layer 104 and the substrate 103 constitute a semiconductor layer 100.

Further, a high-energy ion implantation process is used to form the first buried layer 121, the second buried layer 122, and the third buried layer 123 simultaneously in the epitaxial layer 104, as shown in fig. 6. Wherein the first, second and third buried layers 121, 122 and 123 have a preset distance to the first surface of the semiconductor layer 100.

By forming the first buried layer 121, the second buried layer 122 and the third buried layer 123 in the semiconductor layer 100 simultaneously by using the ion implantation process, the number of mask plates is reduced, patterns of the first to third buried layers are not required to be additionally aligned, and the process difficulty is reduced and the cost is saved.

Further, a well region 130 is formed in the semiconductor layer 100, and the well region 130 extends from the first surface of the semiconductor layer 100 toward the first buried layer 121 and is connected to the tops of the first buried layer 121, the second buried layer 122, and the third buried layer 123, respectively, as shown in fig. 7.

Further, a doped region 140 and a body contact region 142 are formed in the well region 130, the doped region 140 and the body contact region 142 extending from the first surface of the semiconductor layer 100 into the well region 130, as shown in fig. 8.

Further, a trench extending from the first surface of the semiconductor layer 100 to the first buried layer 121 is formed, and a trench gate 150 is formed in the trench, as shown in fig. 9. The depth of the trench is smaller than that of the first buried layer 121, the doped region 140 is used as the source region 141, the undoped well region 130 is used as the body region 131, and the undoped epitaxial layer 104 and the substrate 103 are used as the drift region 110.

In this step, a plurality of trenches are formed at intervals in the Y-axis direction so that the plurality of trench gates 150 are arranged at intervals.

Further, an interlayer dielectric layer 160 and a first conductive layer 171 are formed on the first surface of the semiconductor layer 100, and a second conductive layer 172 is formed on the second surface of the semiconductor layer 100, thereby forming the semiconductor device shown in fig. 1 to 3.

The semiconductor device of the second embodiment of the present disclosure is substantially similar to the method of manufacturing the semiconductor device of the first embodiment, and can be referred to in the description related to the first embodiment, except that in forming the trench, it is necessary to form a trench that extends continuously in the Y-axis direction so that the trench gate 150 extends continuously.

The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (17)

1. A semiconductor device includes a semiconductor layer having opposing first and second surfaces and a trench gate in a trench in the first surface of the semiconductor layer,

The semiconductor layer includes:

the first buried layer is positioned at the bottom of the trench gate and is connected with the trench gate;

The body region is connected with the side wall of the trench gate;

A source region connected to the sidewall of the trench gate and extending from the first surface toward the body region and connected to the body region, and

A drift region, at least part of which is located between the body region and the second surface and is connected with the first buried layer and the body region,

The width of the groove gate is not smaller than the depth of the groove gate, and the width of the groove gate is larger than the width of the first buried layer.

2. The semiconductor device of claim 1, wherein the source region and the drift region are of a first conductivity type, the first buried layer and the body region are of a second conductivity type, the first conductivity type being opposite the second conductivity type.

3. The semiconductor device of claim 1 wherein the semiconductor layer further comprises a second buried layer separated from the trench gate and the first buried layer, respectively, the second buried layer being of the same conductivity type as the first buried layer,

The body region is located between the second buried layer and the first surface and connected with the second buried layer, and the drift region is connected with the second buried layer.

4. The semiconductor device of claim 3, wherein the first buried layer is flush with a bottom of the second buried layer.

5. The semiconductor device of claim 3, wherein the first buried layer and the second buried layer each extend along a length direction of the trench gate.

6. The semiconductor device of claim 3, wherein the body region, the source region, and the second buried layer are located on both sides of the trench gate in a width direction of the trench gate.

7. The semiconductor device according to any one of claims 3 to 6, wherein the semiconductor layer further comprises a third buried layer which is located between the first buried layer and the second buried layer and is connected to the first buried layer, the second buried layer, and the body region, and has a conductivity type identical to that of the first buried layer.

8. The semiconductor device of claim 7, wherein a plurality of the third buried layers are spaced apart along a length direction of the trench gate.

9. The semiconductor device of claim 8, wherein a spacing distance between adjacent third buried layers is greater than a length of the third buried layers along a length direction of the trench gate.

10. The semiconductor device of claim 7, wherein the third buried layer is level with a bottom of the first buried layer.

11. The semiconductor device of claim 7, wherein a plurality of the trench gates are arranged at intervals along a length direction of the trench gate,

And along the length direction of the trench gate, the body region and the source region are also positioned between adjacent trench gates.

12. The semiconductor device of claim 11, wherein a spacing region between adjacent trench gates corresponds to a portion of the third buried layer along a length direction of the trench gates.

13. The semiconductor device of claim 7, wherein the trench gate extends continuously along a length of the trench gate.

14. A method of manufacturing a semiconductor device, comprising:

forming a first buried layer in a semiconductor layer, the semiconductor layer having opposite first and second surfaces, the first buried layer having a preset distance to the first surface;

forming a well region in the semiconductor layer, wherein the well region extends from the first surface towards the first buried layer and is connected with the first buried layer;

Forming a doped region in the well region, the doped region extending from the first surface into the well region, and

Forming a trench extending from the first surface to the first buried layer, and forming a trench gate in the trench,

The width of the groove gate is not smaller than the depth of the groove gate, and the width of the groove gate is larger than the width of the first buried layer.

15. The method of manufacturing according to claim 14, further comprising forming a second buried layer in the semiconductor layer,

The second buried layer is separated from the trench gate and the first buried layer respectively, and the well region is located between the second buried layer and the first surface and connected with the second buried layer.

16. The manufacturing method according to claim 15, further comprising forming a third buried layer in the semiconductor layer,

The third buried layer is located between the first buried layer and the second buried layer and is connected with the first buried layer, the second buried layer and the well region.

17. The method of manufacturing of claim 16, wherein the first, second, and third buried layers are formed simultaneously using an ion implantation process.