CN119694254A - Display control method, circuit, electronic device and computer readable storage medium - Google Patents
Display control method, circuit, electronic device and computer readable storage medium Download PDFInfo
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Abstract
本申请提供一种显示控制方法、电路、电子设备及计算机可读介质，涉及数字图像处理技术领域。方法包括：将待转化数据存入第一存储单元，并在第一存储单元内将待转化数据转化为第一分组数据和第二分组数据；存储信号控制分组数据存入第二存储单元；传输信号控制分组数据传输至一级电路；存储信号包括第一存储子信号和第二存储子信号；传输信号包括第一传输子信号和第二传输子信号；第二存储子信号在第一存储子信号结束时，延迟预设时段触发；第一存储子信号和第一传输子信号的触发时间点一致；第二存储子信号和第二传输子信号的触发时间点一致。通过优化控制信号的时序配置，减少数据翻动和等待时间，可以有效降低无效工作时间，降低芯片功耗。
The present application provides a display control method, circuit, electronic device and computer-readable medium, which relate to the field of digital image processing technology. The method includes: storing the data to be converted into a first storage unit, and converting the data to be converted into first grouped data and second grouped data in the first storage unit; storing the grouped data in the second storage unit under the control of a storage signal; transmitting the grouped data to the primary circuit under the control of a transmission signal; the storage signal includes a first storage sub-signal and a second storage sub-signal; the transmission signal includes a first transmission sub-signal and a second transmission sub-signal; the second storage sub-signal is triggered by delaying a preset period of time at the end of the first storage sub-signal; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent. By optimizing the timing configuration of the control signal and reducing the data flipping and waiting time, the invalid working time can be effectively reduced and the chip power consumption can be reduced.
Description
Technical Field
The present application relates to the field of digital image processing technology, and in particular, to a display control method, a circuit, an electronic device, and a computer readable storage medium.
Background
With the continuous development of display technology, AMOLED display screens are widely used in electronic devices such as smart phones and tablet computers due to the advantages of high contrast, wide color gamut, low power consumption and the like. In order to improve the resolution of AMOLED displays, penTile technology is typically used. The PenTile technology realizes higher pixel density through a special sub-pixel arrangement mode, thereby improving the display effect.
In the AMOLED display screen, the driving chip is required to process a large amount of picture data. In general, the image data sent by the host is real image data, and the driving chip processes the real image data into the subpixel data arranged in Pentile through a subpixel rendering technology (subpixel rendering, abbreviated as SPR). This approach, while increasing the display resolution, also increases the complexity of the data processing.
However, this design has certain problems in the data transmission process. The driving chip is required to transmit the data of the sub-pixel 1 or the data of the sub-pixel 2 to the gray scale voltage converting circuit in a row of display time in a time period. It is a common practice to select the subpixel data to be transferred in the current period by a control signal which transfers the subpixel 1 data when high and the subpixel 2 data when low. When the data of the sub-pixel 1 and the data of the sub-pixel 2 are switched, invalid data flip exists in a period of time, so that the gray scale voltage conversion circuit is invalid in a period of time, and the driving chip is increased in power consumption in a period of time.
Disclosure of Invention
Accordingly, an object of an embodiment of the present application is to provide a display control method, which reduces data flip and waiting time by optimizing timing configuration of control signals, so as to effectively reduce invalid working time and reduce chip power consumption. So as to solve the problems of multiple invalid working time and large power consumption of chips in the prior art.
The display control method comprises the steps of storing data to be converted into first packet data and second packet data in a first storage unit, controlling the first packet data and the second packet data to be stored in the second storage unit through storage signals, controlling the first packet data and the second packet data to be transmitted to a primary circuit through transmission signals, wherein the transmission signals comprise a first transmission sub-signal and a second transmission sub-signal, delaying triggering of the second storage sub-signal by a preset time period when the first storage sub-signal is finished, enabling triggering time points of the first storage sub-signal and the first transmission sub-signal to be consistent, and enabling triggering time points of the second storage sub-signal and the second transmission sub-signal to be consistent.
In the above implementation, the preliminary storage and grouping operations are first completed in the first storage unit. And after the first storage unit completely receives the data to be converted in the first storage unit and converts the data to be converted into first packet data and second packet data, the first packet data and the second packet data are controlled to be respectively stored in the second storage unit, and then the first packet data and the second packet data are controlled to be transmitted to the primary circuit through a transmission signal, wherein the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal. And the triggering of the second storage sub-signal is delayed for a preset period after the first storage sub-signal is finished, the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent, and the triggering time points of the second storage sub-signal and the second transmission sub-signal are also consistent, so that the ordered storage and transmission of data are realized, the stability and the reliability of the overall display control method are improved, the time sequence of each signal can be further allocated, the invalid working time of a circuit is reduced, and the power consumption of a chip is reduced.
Optionally, the display control method further comprises the step that the transmission signal controls the first packet data and the second packet data to pass through the primary circuit and then transmits the first packet data and the second packet data to the secondary circuit, and the secondary circuit converts the first packet data and the second packet data and then outputs display voltage.
In the above implementation process, the first packet data and the second packet data processed by the primary circuit are transmitted to the secondary circuit. In the secondary circuit, the two parts of data are further converted and finally output a voltage signal for display. The complete conversion flow from the original state to the voltage signal which can be directly used for display is realized, the flexibility and the adaptability of the display control method are improved, the diversified requirements on data processing and display effects in different display scenes can be better met, and the performance and the stability of the whole display system are enhanced.
Optionally, the first packet data comprises first class data and second class data, the second packet data comprises third class data and fourth class data, the first packet data and the second packet data are controlled to be transmitted to a primary circuit through a transmission signal, the first class data and/or the third class data are transmitted to the secondary circuit when the transmission signal is in a high level, and the second class data and/or the fourth class data are transmitted to the secondary circuit when the transmission signal is in a low level.
In the implementation process, the flexibility and the refinement degree of data processing are further enhanced by subdividing the first packet data into the first class data and the second class data and subdividing the second packet data into the third class data and the fourth class data. The first type data and/or the third type data are transmitted to the secondary circuit when the transmission signal is at a high level, and the second type data and/or the fourth type data are transmitted to the secondary circuit when the transmission signal is at a low level. The time-sharing transmission of different types of data is realized by utilizing the high-low level characteristics of the transmission signals, the conflict and interference in the data transmission process are reduced, the stability and the reliability of the data transmission are improved, the processing efficiency of the secondary circuit on the data is optimized, and the invalid working time of the circuit is reduced and the power consumption of a chip is reduced by adjusting the time sequence of each signal. The performance of the whole display control method is further improved, and the high requirements on data processing and display effects in complex display scenes are better met.
Optionally, the controlling the first packet data and the second packet data to be stored in the second storage unit through the storage signal includes controlling the first packet data to be stored in the second storage unit from the first storage unit through the first storage sub-signal, and controlling the second packet data to be stored in the second storage unit from the first storage unit through the second storage sub-signal.
In the implementation process, the storage signal is subdivided into the first storage sub-signal and the second storage sub-signal, so that the first packet data and the second packet data are respectively controlled. The method comprises the steps of receiving a first storage sub-signal, receiving a second storage sub-signal, and controlling the storage operation of the first packet data from a first storage unit to a second storage unit by utilizing the first storage sub-signal, so that the first packet data is accurately stored, and simultaneously, controlling the storage process of the second packet data from the first storage unit to the second storage unit by utilizing the second storage sub-signal, thereby ensuring the reliable storage of the second packet data. The mode of respectively controlling different packet data storage through different storage sub-signals not only improves the flexibility and controllability of data storage, but also reduces the conflict and confusion of data in the storage process, and the time sequence of each signal is allocated, so that the invalid working time of a circuit is reduced, and the power consumption of a chip is reduced.
Optionally, the controlling the transmission of the first packet data and the second packet data to the primary circuit through the transmission signal includes controlling the transmission of the first packet data from the second storage unit to the primary circuit through the first transmission sub-signal, and controlling the transmission of the second packet data from the second storage unit to the primary circuit through the second transmission sub-signal.
In the implementation process, the transmission signal is subdivided into the first transmission sub-signal and the second transmission sub-signal, so that the control transmission of the first packet data and the second packet data is realized respectively. The method comprises the steps of receiving a first transmission sub-signal, receiving a first packet data, and transmitting the first packet data to a first-stage circuit through a first storage unit, wherein the first storage unit is used for storing the first packet data, and the first transmission sub-signal is used for precisely controlling the transmission process of the first packet data from the second storage unit to the first-stage circuit by utilizing the first transmission sub-signal so that the first packet data is accurately transmitted, and meanwhile, the transmission operation of the second packet data from the second storage unit to the first-stage circuit is controlled by means of the second transmission sub-signal so as to ensure the reliable transmission of the second packet data. The mode of respectively controlling different packet data transmission through different transmission sub-signals not only improves the flexibility and controllability of data transmission, but also effectively reduces the conflict and interference of data in the transmission process, and by allocating the time sequence of each signal, the invalid working time of the circuit is reduced, and the power consumption of a chip is reduced.
Optionally, the data to be converted is stored in a first storage unit, and the data to be converted is converted into first packet data and second packet data in the first storage unit, wherein the method comprises the steps of preprocessing original data to obtain the data to be converted, temporarily storing the data to be converted into the first storage unit, and dividing the data to be converted into the first packet data and the second packet data through the first storage unit under the condition that all the data to be converted are received by the first storage unit.
In the implementation process, the original data is preprocessed first, so that the data to be converted meets the requirement of subsequent processing. Temporarily storing the data to be converted obtained by pretreatment to a first storage unit, and dividing the data to be converted into first packet data and second packet data by utilizing the storage and processing capacity of the first storage unit after the first storage unit finishes receiving all the data to be converted. The grouping is helpful to the subsequent separate processing and transmission of different types of data, so that the efficiency and the accuracy of the whole display control method are improved, and the data can keep the order in the storage and transmission processes.
The embodiment of the application also provides a display control circuit which comprises a first storage unit, a second storage unit and a primary circuit, wherein the first storage unit is configured to store data to be converted and receive a storage signal to execute corresponding operation, the storage signal comprises a first storage sub-signal and a second storage sub-signal, the first storage unit receives the first storage sub-signal to divide the data to be converted into first packet data and second packet data, the second storage unit is configured to transmit the first packet data and the second packet data into the primary circuit after receiving a transmission signal, the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal, the second storage sub-signal is delayed for triggering in a preset period when the first storage sub-signal is ended, the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent, and the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.
In the implementation process, the display control circuit realizes effective storage, grouping and transmission of data through the cooperative work of the first storage unit, the second storage unit and the primary circuit. The first storage unit divides data to be converted into first packet data and second packet data after receiving the first storage sub-signal. Then, the second storage unit sequentially transfers the two parts of packet data into the primary circuit after receiving the transmission signal. The first transmission sub-signal and the second transmission sub-signal in the transmission signal respectively control the transmission process of the first packet data and the second packet data, so that the data transmission is kept orderly and accurate. In addition, the second storage sub-signal is triggered by delaying a preset period after the first storage sub-signal is finished, so that the time sequence relation of data storage and transmission is further optimized, conflicts and confusion in the data processing process are reduced, invalid working time of a circuit is reduced by adjusting the time sequence of each signal, and chip power consumption is reduced. Not only improves the flexibility and controllability of data storage and transmission, but also enhances the stability and reliability of the whole display control circuit, and provides powerful support for realizing high-efficiency display control functions.
Optionally, the display control circuit further comprises a secondary circuit, wherein the secondary circuit is configured to receive and convert the first packet data and the second packet data and then output a display voltage.
In the implementation process, after the primary processing of the first packet data and the second packet data is completed by the primary circuit, the secondary circuit receives the processed data, performs further conversion processing on the processed data, and finally outputs a voltage signal for display. The complete conversion flow from the original state to the voltage signal which can be directly used for display is realized, the time sequence relation of data storage and transmission is optimized by matching with the grouping processing and transmission of the data by the prior circuit module, the conflict and confusion in the data processing process are reduced, and the invalid working time of the circuit is reduced and the power consumption of a chip is reduced by allocating the time sequence of each signal.
The embodiment of the application also provides electronic equipment, which comprises a memory and a processor, wherein the memory stores program instructions, and the processor executes the steps in any implementation mode when reading and running the program instructions.
In the implementation process, the electronic equipment realizes effective execution of the display control method through the internal memory and the processor. The program instructions stored in the memory comprise the steps of the display control method, and when the processor reads and executes the program instructions, the electronic device can complete the storage, grouping, transmission and final display control operation of the data according to a preset flow.
Embodiments of the present application also provide a computer readable storage medium having stored therein computer program instructions which, when read and executed by a processor, perform the steps of any of the above implementations.
In the above implementation, the computer readable storage medium is used as a key storage component, and stores computer program instructions related to the display control method. When read and executed by a processor, the program instructions are capable of performing the steps of any of the implementations described above, thereby enabling efficient deployment and execution of display control methods.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a simplified schematic diagram of a display control method according to an embodiment of the present application;
FIG. 2 is a detailed schematic diagram of a display control method according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating data transmission to a secondary circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a display control circuit according to an embodiment of the present application;
Fig. 5 is a schematic block diagram of an electronic device according to an embodiment of the present application;
FIG. 6 is a schematic diagram of data transmission in one embodiment provided by the present application;
FIG. 7 is a timing diagram of data transmission in one embodiment provided by the present application;
fig. 8 is a timing chart of a conventional method according to an embodiment of the present application.
The icons are 001-preprocessing module, 010-first storage unit, 020-second storage unit, 030-primary circuit, 040-secondary circuit, 100-electronic equipment, 111-memory, 112-memory controller, 113-processor, 114-peripheral interface, 115-input-output unit and 116-display unit.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on embodiments of the present application without making any inventive effort, are intended to fall within the scope of the embodiments of the present application.
The embodiment of the application provides a display control method which is applied to data display control of a driving chip, and data to be displayed is transmitted to an output circuit (a secondary circuit 040) according to a configuration time sequence by generating the same kind of signals but different kinds of signals, so that invalid flip-flop during data switching is reduced, and the working power consumption of the circuit is reduced.
Optionally, referring to fig. 1, fig. 1 is a simplified schematic diagram of a display control method according to an embodiment of the application.
The display control method comprises the steps of storing data to be converted into first packet data and second packet data in a first storage unit 010, controlling the first packet data and the second packet data to be stored in a second storage unit 020 through storage signals, controlling the first packet data and the second packet data to be transmitted to a primary circuit 030 through transmission signals, wherein the transmission signals comprise a first transmission sub-signal and a second transmission sub-signal, the second storage sub-signal is triggered by delaying a preset time period when the first storage sub-signal is finished, triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent, and triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.
In the implementation process, the display control method realizes the preliminary processing and grouping of the data by storing the data to be converted into the first storage unit 010 and converting the data to be converted into the first grouping data and the second grouping data in the first storage unit 010. Subsequently, the first packet data and the second packet data are controlled to be stored in the second storage unit 020 by a storage signal, wherein the storage signal comprises a first storage sub-signal and a second storage sub-signal. Further, the first packet data and the second packet data are controlled to be transmitted to the stage circuit 030 by a transmission signal including a first transmission sub-signal and a second transmission sub-signal. The trigger time point of the transmission signal is consistent with the trigger time point of the storage signal, and the order and the accuracy of data transmission are maintained. In addition, the second storage sub-signal is triggered by delaying a preset period under the condition that the first storage sub-signal is ended, so that the time sequence relation of data storage and transmission is further optimized, conflicts and confusion in the data processing process are avoided, invalid working time of a circuit is shortened, and chip power consumption is reduced.
Optionally, please refer to fig. 2 in conjunction with fig. 1, fig. 2 is a detailed schematic diagram of a display control method according to an embodiment of the present application.
The method comprises the steps of preprocessing original data to obtain data to be converted, temporarily storing the data to be converted into a first storage unit 010, and dividing the data to be converted into first grouping data and second grouping data through the first storage unit 010 under the condition that the first storage unit 010 receives all the data to be converted, wherein the first grouping data comprises first category data and second category data, and the second grouping data comprises third category data and fourth category data.
In the implementation process, the original data is preprocessed to obtain the data to be converted, wherein the preprocessing may include operations such as data cleaning and format conversion, so that the data meets the requirements of subsequent processing. Then, the data to be converted is temporarily stored in the first storage unit 010 to wait for further processing. When the first storage unit 010 receives all the data to be converted, the data to be converted is divided into the first packet data and the second packet data by the first storage unit 010. Wherein the first packet data includes first category data and second category data, and the second packet data includes third category data and fourth category data.
Optionally, the grouping data can be expanded to more groups or categories, the finer the grouping is, the better the data transmission effect is, the more time is needed, the more complicated the circuit is, and the output efficiency is ensured on the premise of ensuring the reduction of the power consumption of the chip by selecting the proper grouping. Also, each class has its own control signal, and the timing between each class of control signals is configurable.
Referring to fig. 3 in combination with fig. 2, fig. 3 is a schematic diagram illustrating data transmission to the secondary circuit 040 according to an embodiment of the present application.
The first packet data and the second packet data are controlled to be stored in the second storage unit 020 by the storage signal. The first packet data and the second packet data are controlled by the transmission signal to pass through the primary circuit 030 and then transmitted to the secondary circuit 040, and the first type data and/or the third type data are transmitted to the secondary circuit 040 when the transmission signal is at a high level, and the second type data and/or the fourth type data are transmitted to the secondary circuit 040 when the transmission signal is at a low level. The second circuit 040 converts the first packet data and the second packet data and outputs a display voltage.
In the above implementation, the first packet data and the second packet data are controlled to be stored in the second storage unit 020 by the storage signal. The storage signal includes a first storage sub-signal and a second storage sub-signal for controlling a storage operation of the first packet data and the second packet data, respectively. Next, the first packet data and the second packet data are controlled by the transmission signal, and transmitted to the secondary circuit 040 through the primary circuit 030. The transmission signal includes a first transmission sub-signal and a second transmission sub-signal, and transmits the first type of data and/or the third type of data to the secondary circuit 040 when the transmission signal is at a high level, and transmits the second type of data and/or the fourth type of data to the secondary circuit 040 when the transmission signal is at a low level. The second-stage circuit 040 converts the first packet data and the second packet data, and then outputs a voltage signal for display. The grouping and time sequence configuration is utilized, so that the flexibility and the efficiency of data processing are improved, the time for turning invalid data is effectively reduced, the power consumption of a driving chip is reduced, and the performance and the stability of the whole display control method are improved.
In one embodiment of the application, the method is applied in the field of digital image processing. The original data is processed into subpixel data arranged by a subpixel rendering technique (subpixel rendering, SPR for short). If the original data is 1080 resolution, i.e. 1080 columns of pixels are arranged, 2160 sub-pixel data, i.e. two sub-pixels for each pixel, is obtained after SPR processing. In the case where all the pixel data are stored in the first storage unit 010, the pixel data are divided into first packet data and second packet data, and the first packet data includes first class data and second class data, and the second packet data includes third class data and fourth class data. The grouped pixel data is stored in the second storage unit 020 by a storage signal, wherein the storage signal includes a first storage sub-signal and a second storage sub-signal for controlling storage operations of the first packet data and the second packet data, respectively. The first packet data and the second packet data are controlled to be transmitted to the primary circuit 030 by a transmission signal, wherein the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal, the first type pixel data and/or the third type pixel data are transmitted to the secondary circuit 040 when the transmission signal is at a high level, and the second type pixel data and/or the fourth type pixel data are transmitted to the secondary circuit 040 when the transmission signal is at a low level, and the corresponding transmission signal is changed from the low level to the high level when the storage signal is at a high level. When the transmission signals change from high level to low level, the transmission signals also need to change sequentially. The second circuit 040 converts the first packet data and the second packet data and outputs a display voltage. By means of grouping and time sequence configuration, not only are the flexibility and the efficiency of data processing improved, but also the time for turning invalid data is effectively reduced, the power consumption of a driving chip is reduced, and the performance and the stability of the whole display control method are improved.
Referring to fig. 4, fig. 4 is a schematic diagram of a display control circuit according to an embodiment of the application.
The display control circuit comprises a preprocessing module 001, a first storage unit 010, a second storage unit 020, a primary circuit 030 and a secondary circuit 040, wherein the first storage unit 010 is configured to store data to be converted and receive a storage signal to perform corresponding operation, the storage signal comprises a first storage sub-signal and a second storage sub-signal, the first storage unit 010 receives the first storage sub-signal to divide the data to be converted into first packet data and second packet data, the second storage unit 020 is configured to receive a transmission signal and then transmit the first packet data and the second packet data into the primary circuit 030, and the secondary circuit 040 is configured to receive and convert the first packet data and the second packet data and then output a display voltage. The transmission signals comprise a first transmission sub-signal and a second transmission sub-signal, wherein the second storage sub-signal is triggered by delaying a preset period when the first storage sub-signal is ended, the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent, and the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.
In one embodiment of the present application, the preprocessing module 001 may be a data format conversion module, a data cleansing module, a data compression module, a data enhancement module, a color correction module, a data sorting module, or the like. The first memory unit 010 and the second memory unit 020 may be a data buffer, and a memory unit for storing the original pixel data or the preprocessed data to be converted, or the first packet data and the second packet data. The primary circuit 030 may be a MUX2:1 circuit, a data selector, a multiplexer, and a circuit for selecting and transmitting packet data to the secondary circuit 040. The secondary circuit 040 may be a gray-scale conversion circuit, a display driving circuit, a display signal conversion circuit, for converting packet data into a display voltage.
In one embodiment of the application, the raw pixel data is typically from a host or other external device, and its input speed and format may not be fully suitable for direct subsequent data processing. The preprocessing module 001 converts raw pixel data from one format to another to accommodate the requirements of subsequent processing. For example, data in RGB format is converted into data in Pentile format. The first memory unit 010 serves as a first memory unit 010, which serves as a buffer, can receive single data sent from an input terminal, and temporarily stores original pixel data after receiving, ensuring that the data is complete and continuous before processing. The second storage unit 020 is for storing the first packet data and the second packet data updated by the storage signal from the first storage unit 010, ensuring that the data is complete and ordered in the form of packets before being transferred to the primary circuit 030. The MUX2:1 circuit, which is the primary circuit 030, is responsible for selecting and transmitting sub-pixel data to the secondary circuit 040. By controlling the transmission signals, the MUX2:1 circuit can select the first type of pixel data and/or the third type of pixel data or the second type of pixel data and/or the fourth type of pixel data according to the requirements, so that the flexibility and the controllability of data transmission are ensured. Meanwhile, by optimizing the time sequence configuration of the control signals, the invalid flipping time in the data transmission process is reduced, and the data transmission efficiency is improved. The secondary circuit 040 converts the received sub-pixel data into display voltage and outputs the display voltage to the AMOLED display screen. The main function of the display device is to convert the sub-pixel data in a digital form into a display voltage in an analog form, so that the display device can display images correctly. In addition, the gray-scale conversion circuit can reduce invalid working time and power consumption of the driving chip by optimizing data transmission and conversion processes, thereby realizing high-quality display effect and excellent performance.
Fig. 5 is a block schematic diagram of an electronic device according to an embodiment of the present application. The electronic device 100 may include a memory 111, a memory controller 112, a processor 113, a peripheral interface 114, an input output unit 115, and a display unit 116. It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 5 is merely illustrative and is not limiting of the configuration of the electronic device 100. For example, the electronic device 100 may also include more or fewer components than shown in fig. 5, or have a different configuration than shown in fig. 5.
The above-mentioned memory 111, memory controller 112, processor 113, peripheral interface 114, input/output unit 115 and display unit 116 are electrically connected directly or indirectly to each other to realize data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The processor 113 is used to execute executable modules stored in the memory.
The Memory 111 may be, but is not limited to, a random access Memory (Random Access Memory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc. The memory 111 is configured to store a program, and the processor 113 executes the program after receiving an execution instruction, and a method executed by the electronic device 100 defined by the process disclosed in any embodiment of the present application may be applied to the processor 113 or implemented by the processor 113.
The processor 113 may be an integrated circuit chip having signal processing capabilities. The processor 113 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a digital signal processor (DIGITAL SIGNAL processor, DSP), an Application-specific integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a discrete gate or transistor logic device, or a discrete hardware component. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. The general purpose processor may be a microprocessor, but in the alternative, it may be any conventional processor or the like.
The peripheral interface 114 couples various input/output devices to the processor 113 and the memory 111. In some embodiments, the peripheral interface 114, the processor 113, and the memory controller 112 may be implemented in a single chip. In other examples, they may be implemented by separate chips.
The input-output unit 115 described above is used to provide input data to a user. The input/output unit 115 may be, but is not limited to, a mouse, a keyboard, and the like.
The display unit 116 described above provides an interactive interface (e.g., a user-operated interface) between the electronic device 100 and a user or is used to display image data to a user reference. In this embodiment, the display unit may be a liquid crystal display or a touch display. In the case of a touch display, the touch display may be a capacitive touch screen or a resistive touch screen, etc. supporting single-point and multi-point touch operations. Supporting single-point and multi-point touch operations means that the touch display can sense touch operations simultaneously generated from one or more positions on the touch display, and the sensed touch operations are passed to the processor for calculation and processing.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating data transmission in an embodiment of the present application.
In one embodiment of the present application, taking 1080 source PADs of the driving chip as an example, 1080 gray-scale conversion paths, that is, S1-S1080, are divided into two groups of high and low, where S1-S540 are low packets and S541-S1080 are high packets. Each packet contains 4 types of data, namely odd 1, even 1, odd 2 and even 2. In this way, 1080 grayscale conversion paths, i.e., 2160 data, are classified into 8 types, specifically, low packet odd 1, low packet even 1, low packet odd 2, low packet even 2, high packet odd 1, high packet even 1, high packet odd 2, high packet even 2. When packet data is updated from LA1 (first storage unit) to LA2 (second storage unit), the data update is controlled by the UPD signal (storage signal). Since the data is divided into 8 classes, each class of data has its own control signal, namely UPD _ o1_ L, upd_e1_l, upd_o2_l, upd_e2_l, upd_o1_h, UPD _ e2_ L, UPD _ O1_ H. When the subpixel data is transferred from LA2 to the gray-scale conversion circuit through the MUX2:1 circuit, the subpixel 1 data or the subpixel 2 data is controlled by the SEL signal (transfer signal). Wherein, the data of the high level selection sub-pixel 1 is transmitted to the gray level conversion circuit, and the data of the low level selection sub-pixel 2 is transmitted to the gray level conversion circuit. Since LA2 and the gray-scale conversion circuit are divided into 8 classes, each class of data has its own control signal, i.e., sel_o1_l, sel_e1_l, sel_o2_l, sel_e2_l, sel_o1_h, sel_e1_h, sel_o2_h, sel_e2_h. Fig. 6 shows control signals and data transmission diagrams of high packet odd 1, high packet even 1, high packet odd 2, high packet even 2. The low packet is processed in the same manner as above, and when the subpixel data is updated from LA1 to LA2, the control signals are upd_o1_l, upd_e1_l, upd_o2_l, and upd_e2_l. When the sub-pixel data passes from LA2 to the gradation conversion circuit through the MUX2:1 circuit, the control signals are sel_o1_l, sel_e1_l, sel_o2_l, sel_e2_l. The timing of the validation of each of the same type of signals is different and configurable by a register.
Referring to fig. 7 and 8, fig. 7 is a timing chart of data transmission in an embodiment of the present application, and fig. 8 is a timing chart of a conventional method in an embodiment of the present application.
First, in fig. 7, T0 represents a line display time, and T1 represents a time interval between each type of control signals, which interval can be configured by a register to realize different timings. T2 represents the invalid flip time of the sub-pixel data output from the MUX2:1 circuit to the gray scale conversion circuit before stabilization. With 8 UPD signals, 2160 sub-pixel data can be updated from LA1 to LA2 in 8 different time points. And then, through the matching of corresponding SEL control signal time sequences, the invalid time T2 is shortened and the number of data is reduced when the sub-pixel data output to the gray scale conversion circuit by the MUX2:1 circuit is switched from the sub-pixel 2 of the previous row to the sub-pixel 1 of the current row. Similarly, the number of invalid data is also reduced in the T3 time. The T1 time is equal to the UPD signal high time times 7, plus the spacing between UPD signals times 7. The spacing between the UPD signals is shown and may be configured by registers to achieve different timings. When the UPD signal is at a high level, the corresponding SEL signal changes from a low level to a high level. The SEL signals also change sequentially when they change from high to low. T2 represents the invalid data time before the data of the sub-pixel 2 of the previous line is output to the data of the sub-pixel 1 of the current line by the MUX2:1 circuit, because the sub-pixel data is multi-bit, and the delay time of each bit circuit is different. T3 represents the invalid data time before the MUX2:1 circuit outputs the current row sub-pixel 1 data to switch to the current row sub-pixel 2 data. Class 8 data has T2, T3 times for each class, except for the point in time at which the T2, T3 time periods occur for each class. For example, the point in time when T2 of the low packet odd 1 occurs precedes T2 of the high packet odd 1.
In contrast to fig. 8, in the conventional scheme, the gray-scale conversion circuits are generally classified into two categories, i.e., low-order groups and high-order groups. Taking 1080 resolution of the original picture as an example, when the MUX2:1 circuit outputs the sub-pixel data 1 to switch to the sub-pixel data 2, 1080 sub-pixel data are shared for switching in the time of T3, and the number of invalid data is 8 times that of the scheme. Similarly, when the sub-pixel data 2 of the previous line is switched to the sub-pixel data 1 of the current line, the number of invalid data is 8 times as large as that of the scheme in the time T2. In addition, since the control signal UPD and the control signal SEL corresponding thereto have the same timing switching point in this scheme, the present scheme greatly reduces the T2 time, so that the data invalid flip time is reduced.
In summary, the present application provides a display control method, a circuit, an electronic device, and a computer readable medium, which ensure the integrity and the order of data by temporarily storing the original pixel data in the first storage unit 010, preprocessing and grouping the original pixel data, and then storing the preprocessed and grouped original pixel data in the second storage unit 020. The second memory unit 020 temporarily stores the grouped data, and provides a stable basis for subsequent data selection and transmission. The primary circuit 030 selects and transmits packet data by a transmission signal, ensuring flexibility and controllability of data transmission. The secondary circuit 040 converts the sub-pixel data into display voltage output, and achieves a high-quality display effect. In the whole process, invalid data flipping time is reduced, power consumption of a driving chip is reduced, and performance and stability of a display control method are improved by optimizing time sequence configuration of data storage, transmission and conversion.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of devices according to various embodiments of the present application. In this regard, each block in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams, and combinations of blocks in the block diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of additional identical elements in a process, method, article, or apparatus that comprises the element.
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