CN119694893A - Semiconductor packaging structure and method for forming the same - Google Patents
Semiconductor packaging structure and method for forming the same Download PDFInfo
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Abstract
一种半导体封装结构及其形成方法，形成方法包括：提供玻璃基板，玻璃基板中具有若干分立的玻璃通孔互连结构，玻璃基板的中还具有位于上表面的凹槽；提供未内部布线的半导体芯片，包括半导体衬底和位于半导体衬底上表面的器件层，器件层中具有半导体器件；将未内部布线的半导体芯片贴装进凹槽中；在玻璃基板的上表面形成无机介质层和位于无机介质层中的第一互连结构和第二互连结构，第一互连结构与玻璃通孔互连结构的上端表面电连接，第二互连结构与半导体器件电连接，未内部布线的半导体芯片、第二互连结构和部分无机介质层构成第一半导体芯片；在玻璃基板下表面形成有机钝化层和位于有机钝化层中的第三互连结构。提高了封装结构的性能。
A semiconductor packaging structure and a forming method thereof, the forming method comprising: providing a glass substrate, the glass substrate having a plurality of discrete glass through hole interconnection structures, the glass substrate also having a groove located on the upper surface; providing a semiconductor chip without internal wiring, comprising a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, the device layer having a semiconductor device; mounting the semiconductor chip without internal wiring into the groove; forming an inorganic dielectric layer and a first interconnection structure and a second interconnection structure located in the inorganic dielectric layer on the upper surface of the glass substrate, the first interconnection structure being electrically connected to the upper end surface of the glass through hole interconnection structure, the second interconnection structure being electrically connected to the semiconductor device, the semiconductor chip without internal wiring, the second interconnection structure and part of the inorganic dielectric layer constituting the first semiconductor chip; forming an organic passivation layer and a third interconnection structure located in the organic passivation layer on the lower surface of the glass substrate. The performance of the packaging structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor packaging, and more particularly, to a semiconductor packaging structure and a method for forming the same.
Background
The most common of the existing packaging substrates is an organic material substrate, the processing difficulty of the organic material substrate is low, and the organic material substrate can also transmit signals at high speed and is always regarded as a army in the field of chips. However, the organic material substrate has some drawbacks, such as an excessively large difference in thermal expansion coefficient between the organic material substrate and the chip, easy disconnection of the connection point between the chip and the organic material substrate at high temperature, easy burning of the chip, and a very limited size of the organic substrate, which does not accommodate too many chips in a limited size.
In this context, glass substrates have been developed. The glass substrate has ultra-low flatness (extremely flat), better thermal stability and mechanical stability. Since the glass material is very flat, the depth of focus of lithography can be improved, and the number of openings is much larger than that on the organic material substrate in the same area, so that the interval between the formed glass through holes (Through Glass Via) can be smaller than 100 micrometers, which directly improves the interconnection density between chips by 10 times. In addition, the thermal expansion coefficient of the glass substrate is closer to that of the chip, the deformation can be reduced by 50% due to higher temperature tolerance, the risk of fracture of the connecting point can be reduced, and the reliability of the chip is improved. In addition, compared with the traditional organic material substrate, the glass substrate has lower power consumption and higher signal transmission speed, and the thickness of the glass substrate can be reduced by about half. These advantages make glass substrates an ideal choice for next generation high density packaging, enabling the construction of higher performance multi-chip package structures.
However, the performance of the existing packaging structure based on the glass substrate still needs to be improved.
Disclosure of Invention
The application aims to provide a semiconductor packaging structure and a forming method thereof, so as to improve the performance of the packaging structure based on a glass substrate.
To this end, the present application first provides a method for forming a semiconductor package structure, including:
Providing a glass substrate, wherein the glass substrate is provided with a plurality of discrete glass through hole interconnection structures, the upper surface and the lower surface of the glass substrate are respectively exposed out of the upper end surface and the lower end surface of the glass through hole interconnection structures, the glass substrate is also provided with a groove, and the groove is positioned on the upper surface of the glass substrate;
providing a semiconductor chip without internal wiring, wherein the semiconductor chip without internal wiring comprises a semiconductor substrate and a device layer positioned on the upper surface of the semiconductor substrate, and the device layer is provided with a semiconductor device;
Mounting the semiconductor chip without internal wiring into the groove, wherein the upper surface of a device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate;
Forming an inorganic dielectric layer and a first interconnection structure and a second interconnection structure in the inorganic dielectric layer on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring, wherein the first interconnection structure is electrically connected with the upper end surface of the glass through hole interconnection structure, the second interconnection structure is electrically connected with the semiconductor device in the semiconductor chip without internal wiring, part of the second interconnection structure is also electrically connected with part of the first interconnection structure, and the semiconductor chip without internal wiring, the second interconnection structure and part of the inorganic dielectric layer form a first semiconductor chip;
Forming an organic passivation layer and a third interconnection structure in the organic passivation layer on the lower surface of the glass substrate, wherein the third interconnection structure is electrically connected with the lower end surface of the glass through hole interconnection structure;
and at least one second semiconductor chip is mounted on the upper surface of the inorganic medium layer, and the second semiconductor chip is electrically connected with the first interconnection structure.
In an alternative embodiment, the forming method further includes forming a plurality of discrete first solder bumps on a lower surface of the inorganic passivation layer, the first solder bumps being electrically connected to the third interconnect structure.
In an alternative embodiment, the inorganic dielectric layer, the first interconnection structure and the second interconnection structure are manufactured by BEOL process in front-end of line (front-end of line) process of the semiconductor, the organic passivation layer and the third interconnection structure are manufactured by RDL process in back-end of line process of the semiconductor, the density of the first interconnection structure is greater than that of the third interconnection structure, the feature size of the first interconnection structure is smaller than that of the third interconnection structure, and the density of the second interconnection structure is greater than or equal to that of the first interconnection structure.
In an alternative embodiment, the first interconnect structure and the second interconnect structure have a feature size of 0.2-0.8 microns and the third interconnect structure has a feature size of 1.5-2.5 microns.
In an alternative embodiment, the first interconnection structure and the second interconnection structure comprise one or a combination of a plurality of metal wires, metal plugs, damascene structures or dual damascene structures, and the third interconnection structure is a rewiring layer.
In an alternative embodiment, the inorganic dielectric layer is a multi-layered stacked structure, and the first interconnect structure and the second interconnect structure are multi-layered stacked structures.
In an alternative embodiment, the material of the inorganic dielectric layer is one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnection structure, the second interconnection structure and the third interconnection structure is one or a combination of several of Cu, al, W, ag, au, pt, ni, ti, ta, tiN, taN, taC, WN.
In an alternative embodiment, the device layer further includes an underlying inorganic dielectric layer on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covering the semiconductor device, and the device layer further includes a conductive connection structure in the underlying inorganic dielectric layer electrically connected to the active region of the semiconductor device, the conductive connection structure being electrically connected to the second interconnect structure.
In an alternative embodiment, the semiconductor device includes one or a combination of several of a bipolar transistor, a field effect transistor and an insulated gate bipolar transistor.
In an alternative embodiment, the semiconductor device further includes one or a combination of several of a diode, a resistor, a capacitor, and an inductor.
In an alternative embodiment, the forming method further comprises providing a passive device, mounting the passive device on the lower surface of the glass substrate or embedding the passive device in the glass substrate from the direction of the lower surface of the glass substrate, and electrically connecting the passive device with the third interconnection structure.
The application also provides a semiconductor packaging structure, which comprises:
The glass substrate is provided with a plurality of discrete glass through hole interconnection structures, the upper surface and the lower surface of the glass substrate are respectively exposed out of the upper end surface and the lower end surface of the glass through hole interconnection structures, a groove is further formed in the glass substrate, and the groove is positioned on the upper surface of the glass substrate;
A semiconductor chip without internal wiring in the groove, the semiconductor chip without internal wiring comprising a semiconductor substrate and a device layer on an upper surface of the semiconductor substrate, the device layer having a semiconductor device therein, the upper surface of the device layer of the semiconductor chip without internal wiring being flush with the upper surface of the glass substrate;
An inorganic dielectric layer located on an upper surface of the glass substrate and an upper surface of a device layer of the semiconductor chip without internal wiring, and a first interconnect structure and a second interconnect structure located in the inorganic dielectric layer, the first interconnect structure being electrically connected to an upper end surface of the glass via interconnect structure, the second interconnect structure being electrically connected to a semiconductor device in the semiconductor chip without internal wiring, and a part of the second interconnect structure being further electrically connected to a part of the first interconnect structure, the semiconductor chip without internal wiring, the second interconnect structure, and a part of the inorganic dielectric layer constituting a first semiconductor chip;
An organic passivation layer positioned on the lower surface of the glass substrate and a third interconnection structure positioned in the organic passivation layer, wherein the third interconnection structure is electrically connected with the lower end surface of the glass through hole interconnection structure;
and at least one second semiconductor chip is mounted on the upper surface of the inorganic medium layer, and the second semiconductor chip is electrically connected with the first interconnection structure.
In an alternative embodiment, the package structure further includes a plurality of discrete first solder bumps on a lower surface of the inorganic passivation layer, the first solder bumps being electrically connected to the third interconnect structure.
In an alternative embodiment, the inorganic dielectric layer, the first interconnection structure and the second interconnection structure are formed by BEOL (back end of line) process in front end of line process of the semiconductor, the organic passivation layer and the third interconnection structure are formed by RDL (RDL) process in back end of line process of the semiconductor, the density of the first interconnection structure is greater than that of the third interconnection structure, the feature size of the first interconnection structure is smaller than that of the third interconnection structure, and the density of the second interconnection structure is greater than or equal to that of the first interconnection structure.
In an alternative embodiment, the first interconnect structure and the second interconnect structure have a feature size of 0.2-0.8 microns and the third interconnect structure has a feature size of 1.5-2.5 microns.
In an alternative embodiment, the first interconnection structure and the second interconnection structure comprise one or a combination of a plurality of metal wires, metal plugs, damascene structures or dual damascene structures, and the third interconnection structure is a rewiring layer.
In an alternative embodiment, the inorganic medium layer is a multi-layer stacked structure, the first interconnection structure and the second interconnection structure are multi-layer stacked structures, the material of the inorganic medium layer is one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnection structure, the second interconnection structure and the third interconnection structure is one or a combination of several of Cu, al, W, ag, au, pt, ni, ti, ta, tiN, taN, taC, WN.
In an alternative embodiment, the device layer further includes an underlying inorganic dielectric layer on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covering the semiconductor device, and the device layer further includes a conductive connection structure in the underlying inorganic dielectric layer electrically connected to the active region of the semiconductor device, the conductive connection structure being electrically connected to the second interconnect structure.
In an alternative embodiment, the semiconductor device includes one or a combination of several of a bipolar transistor, a field effect transistor and an insulated gate bipolar transistor.
In an alternative embodiment, the semiconductor device further includes one or a combination of several of a diode, a resistor, a capacitor, and an inductor.
In an alternative embodiment, the packaging structure further comprises a passive device, wherein the passive device is mounted on the lower surface of the glass substrate or embedded in the glass substrate from the direction of the lower surface of the glass substrate, and the passive device is electrically connected with the third interconnection structure.
Compared with the prior art, the technical scheme of the application has the advantages that:
In the present application, when the semiconductor chip without internal wiring is fabricated, only a front End Of Line (FEOL, front End Of Line) Of the semiconductor front End Of Line is performed to form a semiconductor device, and a Back End Of Line (BEOL) Of the semiconductor front End Of Line is not performed, that is, internal wiring for interconnecting the semiconductor device is not formed, after the semiconductor chip without internal wiring is mounted or embedded in a groove Of a glass substrate, an inorganic dielectric layer and a first interconnect structure and a second interconnect structure located in the inorganic dielectric layer are formed on an upper surface Of the glass substrate and an upper surface Of a device layer Of the semiconductor chip without internal wiring through the Back End Of Line (BEOL, back End Of Line) Of the semiconductor front End Of Line, and the semiconductor chip without internal wiring, the second interconnect structure and a portion Of the inorganic dielectric layer form a first semiconductor chip, so that the first semiconductor chip has corresponding functions (such as logic control and/or data storage) and the like, and the package performance Of the semiconductor chip can be increased by forming the first semiconductor chip through the specific steps. In addition, the semiconductor chip without internal wiring is only manufactured to the device layer, so that the manufacturing process of the semiconductor chip without internal wiring can be greatly simplified, and meanwhile, the thickness of the semiconductor chip without internal wiring can be made thinner, so that the depth of the groove in the glass substrate can be made shallower, the glass substrate can be kept thinner, and the semiconductor chip without internal wiring is buried in the glass substrate, and the thickness of the packaging structure can not be increased. And, the second interconnection structure (or internal wiring) for interconnecting the semiconductor devices on the semiconductor chip without internal wiring is synchronized with the step of forming the first interconnection structure on the upper surface of the glass substrate, so that the formation process of the internal wiring of the semiconductor chip without internal wiring is compatible with the formation process of the first interconnection structure on the glass substrate while the structure and function of the first semiconductor chip can be completely realized. In addition, the semiconductor device (thin film transistor package) may not be fabricated on the upper surface of the glass substrate later, and the semiconductor device is fabricated integrally on the semiconductor chip without internal wiring, which simplifies the process, reduces the thermal effect, and optimizes and simplifies the layout of the wiring layer on the upper surface of the glass substrate.
Drawings
FIGS. 1-7 are schematic diagrams illustrating a process for forming a semiconductor package according to an embodiment of the application;
FIG. 8 is a schematic diagram illustrating a process of forming a semiconductor package according to another embodiment of the present application;
fig. 9 is a schematic diagram illustrating a process of forming a semiconductor package according to another embodiment of the present application.
Detailed Description
The following describes the embodiments of the present application in detail with reference to the drawings. In describing embodiments of the present application in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
An embodiment of the present application first provides a method for forming a semiconductor package, and a specific process of the method is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a glass substrate 100 is provided, wherein the glass substrate 100 has a plurality of discrete glass via interconnection structures 103, the upper surface and the lower surface of the glass substrate 100 expose the upper end surface and the lower end surface of the glass via interconnection structures 103, respectively, and the glass substrate 100 further has a groove 110 therein, and the groove 110 is located on the upper surface of the glass substrate 100.
The glass substrate 100 serves as a support carrier and a wiring carrier for the package structure. The glass substrate 100 has ultra-low flatness (extremely flat), better thermal stability and mechanical stability than organic material substrates. In an embodiment, the material of the glass substrate 100 is glass, crystal and the like, and the thermal expansion coefficient of the glass substrate 100 is less than or equal to 9ppm/°c, specifically, 3 ppm/°c-4 ppm/°c,6 ppm/°c-9 ppm/°c.
The glass substrate 100 may have a thinner thickness and a larger size. In one embodiment, the thickness of the glass substrate 100 is less than 800 microns. In a specific embodiment, the glass substrate 100 may have a thickness of 300 microns to 500 microns. In another specific embodiment, the glass substrate 100 may have a thickness of 30 micrometers to 200 micrometers. In an embodiment, the glass substrate 100 is rectangular, and the size of the glass substrate 100 is greater than 100mmX100mm, and the size of the glass substrate 100 may be 110mmX110mm, 300mmX300mm, 515mmX510mm, 600mmX600mm, 620mmX750mm.
The glass substrate 100 has formed therein a number of discrete through glass via (TGV, through Glass Via) interconnect structures 103. In an embodiment, the material of the glass via interconnection structure 103 is one material or a combination of two or more materials selected from copper, tungsten, aluminum, nickel, gold, gallium, silver, and titanium. In one embodiment, the forming process of the glass via interconnection structure 103 includes forming a glass via (TGV, through Glass Via) in the glass substrate 103, where the glass via may be formed by a photosensitive glass method, a focusing power generation method, a plasma etching method, a laser ablation method, an electrochemical discharge machining method, or a laser induced etching method, filling a metal conductive material in the glass via and planarizing the metal conductive material to form the glass via interconnection structure 103, filling the metal conductive material may be formed by electroplating or physical vapor deposition (such as sputtering), and planarizing the metal conductive material may be performed by a chemical mechanical polishing process.
The shape of the groove 110 is the same as the shape of the semiconductor chip without internal wiring which is mounted subsequently in the groove 110, the depth of the groove 110 is equal to or slightly larger than the thickness of the semiconductor chip without internal wiring, and the size of the groove 110 is equal to or slightly larger than the size of the semiconductor chip without internal wiring. In one embodiment, the recess 110 is formed after the glass via interconnect structure 103 is formed. The grooves 110 may be formed by a photosensitive glass method, a focusing power generation method, a plasma etching method, a laser ablation method, an electrochemical discharge machining method, or a laser induced etching method.
Referring to fig. 2, a semiconductor chip 300 without internal wiring is provided, the semiconductor chip 300 without internal wiring including a semiconductor substrate 302 and a device layer having a semiconductor device 304 therein on an upper surface of the semiconductor substrate 302.
The semiconductor chip 300 without internal wiring is fabricated by performing a front End Of Line (FEOL, front End Of Line) process Of the semiconductor front End Of Line only to form the semiconductor device 304, and performing a Back End Of Line (BEOL) process Of the semiconductor front End Of Line, i.e., forming no internal wiring for interconnecting the semiconductor device 304. After the semiconductor chip 300 without internal wiring is mounted or buried in the recess 110 (refer to fig. 3) of the glass substrate, an inorganic dielectric layer 104 and a first interconnect structure 101 and a second interconnect structure 305 (refer to fig. 4) located in the inorganic dielectric layer 104 are formed on the upper surface of the glass substrate 100 and the upper surface of the device layer of the semiconductor chip 300 without internal wiring, the first interconnect structure 101 is electrically connected to the upper end surface of the glass via interconnect structure 103, the second interconnect structure 305 is electrically connected to the semiconductor device 304 in the semiconductor chip 300 without internal wiring, and a part of the second interconnect structure 305 is also electrically connected to a part of the first interconnect structure 101, the semiconductor chip 300 without internal wiring, The second interconnection structure 305 and a portion of the inorganic dielectric layer 104 form a first semiconductor chip (refer to fig. 4), the first semiconductor chip 301 may have corresponding functions (such as logic control and/or data storage, etc.), and the first semiconductor chip 301 may be interconnected with a second semiconductor chip 201 (refer to fig. 6) subsequently mounted on the upper surface of the inorganic dielectric layer 104 through a portion of the first interconnection structure 101, that is, the first semiconductor chip 301 formed through the foregoing specific steps may increase the functions of the package structure and improve the performance of the package structure. In addition, since the semiconductor chip 300 without internal wiring is only fabricated on the device layer without internal wiring, the fabrication process of the semiconductor chip 300 without internal wiring can be greatly simplified, and the thickness of the semiconductor chip 300 without internal wiring can be made thinner, so that the depth of the groove 110 in the glass substrate 100 can be made shallower, the thickness of the glass substrate 100 can be kept thinner, and the semiconductor chip 300 without internal wiring is buried in the glass substrate 100 without increasing the thickness of the package structure. Also, the second interconnection structure 305 (or internal wiring) for interconnecting the semiconductor devices on the semiconductor chip 300 without internal wiring is synchronized with the step of forming the first interconnection structure 101 on the upper surface of the glass substrate 100, so that the formation process of the internal wiring of the semiconductor chip 300 without internal wiring is compatible with the formation process of the first interconnection structure 101 on the glass substrate 100 while the structure and function of the first semiconductor chip 301 can be completely realized. in addition, a semiconductor device (thin film transistor package) may not be formed on the upper surface of the glass substrate 101 later, and the semiconductor device may be integrally formed on the semiconductor chip 300 without internal wiring, which simplifies the process, reduces the thermal effect, and optimizes and simplifies the layout of the wiring layer on the upper surface of the glass substrate 100.
In an embodiment, the device layer further includes an underlying inorganic dielectric layer 303 disposed on the upper surface of the semiconductor substrate 302, the underlying inorganic dielectric layer 303 covers the semiconductor device 304, the device layer further includes a conductive connection structure 307 disposed in the underlying inorganic dielectric layer 303 and electrically connected to the active region of the semiconductor device 304, the conductive connection structure 307 is electrically connected to the second interconnection structure 305, the underlying inorganic dielectric layer 303 directly exposes a part or all of the active region of the semiconductor device 302, and the underlying inorganic dielectric layer 303 exposes an upper end surface of the conductive connection structure 307. In one embodiment, the semiconductor substrate 302 may be a wafer. In one embodiment, the semiconductor substrate 302 is made of silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), silicon On Insulator (SOI), germanium On Insulator (GOI), or other materials, such as III-V compounds like gallium arsenide. The semiconductor substrate 300 may also be implanted with certain dopant ions to change electrical parameters according to design requirements. In an embodiment, a shallow trench isolation structure 306 is further formed in the semiconductor substrate 300, and the shallow trench isolation structure is used to isolate different semiconductor devices 304, so as to prevent electrical connection between the different semiconductor devices 304. The material of the bottom inorganic dielectric layer 303 and the shallow trench isolation structure 306 may be one or more of silicon oxide, silicon nitride, and silicon oxynitride.
In one embodiment, the semiconductor device 304 includes one or a combination of bipolar transistors, field effect transistors, and insulated gate bipolar transistors. In another embodiment, the semiconductor device 304 further includes one or a combination of several of a diode, a resistor, a capacitor, and an inductor. It should be noted that the semiconductor device 304 in fig. 2 is illustrated by taking two field effect transistors as an example, and in other embodiments, the semiconductor device 304 may be other semiconductor devices, other numbers, and other layout structures.
The bipolar transistor (fully called bipolar junction transistor (bipolar junction transistor, BJT)), commonly called triode, is an electronic device with three terminals, and is made of three semiconductors with different doping levels in a semiconductor substrate, and comprises an emitter (Emitter), a Base (Base) and a Collector (Collector), wherein the doping types of the Base (Base) and the emitter (Emitter) and the Collector (Collector) are different, for example, for an NPN triode, the doping type of the Base (Base) is P-type, and the doping type of the emitter (Emitter) and the Collector (Collector) is N-type. Referring to fig. 2, the field effect Transistor (FIELD EFFECT Transistor, FET) includes a Gate (Gate) 304a on the upper surface of the semiconductor substrate 302, and a Source (Source) 304b and a Drain (Drain) 304c in the semiconductor substrate 302 on both sides of the Gate 304a, and further includes a sidewall 304d on a sidewall surface of the Gate 304 a. The Field effect transistor may include a Metal-Oxide-semiconductor Field effect transistor (MOSFET) including a PMOS transistor and an NMOS transistor or a Fin Field effect transistor (FinFET) including a Fin Field-Effect Transistor. The insulated gate bipolar transistor (Insulate-Gate Bipolar Transistor-IGBT) comprises a grid electrode, a collector electrode and an emitter electrode, wherein the doping degrees of the grid electrode and the doping types of the emitter electrode and the collector electrode are different, for example, when the doping type of the grid electrode is P type, the doping types of the emitter electrode and the collector electrode are N type.
Referring to fig. 3, the semiconductor chip 300 without internal wiring is mounted in the recess 110, and an upper surface of a device layer of the semiconductor chip 300 without internal wiring is flush with an upper surface of the glass substrate 100.
In one embodiment, an adhesive is applied to the lower surface (and the side) of the semiconductor chip 300 without internal wiring before the semiconductor chip 300 without internal wiring is mounted in the recess 110.
Referring to fig. 4, an inorganic dielectric layer 104 and first and second interconnect structures 101 and 305 located in the inorganic dielectric layer 104 are formed on an upper surface of a glass substrate 100 and an upper surface of a device layer of the semiconductor chip 300 without internal wiring, the first interconnect structure 101 is electrically connected to an upper end surface of the glass via interconnect structure 103, the second interconnect structure 305 is electrically connected to a semiconductor device 304 in the semiconductor chip 300 without internal wiring, and a part of the second interconnect structure 305 is also electrically connected to a part of the first interconnect structure 101, and the semiconductor chip 300 without internal wiring, the second interconnect structure 305, and a part of the inorganic dielectric layer 104 constitute a first semiconductor chip 301.
The inorganic dielectric layer 104 is used for isolation between adjacent first interconnect structures 101, between adjacent second interconnect structures 305, and between adjacent first interconnect structures 101 and second interconnect structures 305.
The first interconnect structure 101 is used for interconnection between different chips. In an embodiment, a portion of the first interconnect structure 101 may be used to interconnect a second semiconductor chip 201 (refer to fig. 5) subsequently mounted on the upper surface of the inorganic dielectric layer 104 with the glass via interconnect structure 103 in the glass substrate 100. In another embodiment, part of the first interconnection structure 101 may also be used for interconnection between a plurality of second semiconductor chips 201 to be mounted later. In another embodiment, a portion of the first interconnect structure 101 may also be used to interconnect with a portion of the second interconnect structure 305.
The second interconnect structure 305 is used for interconnection between semiconductor devices 304 in the device layer of the unwired semiconductor chip 300. A portion of the second interconnect structure 305 is further configured to interconnect with a portion of the first interconnect structure 101, such that the first semiconductor chip 301 may be interconnected with a second semiconductor chip 201 subsequently mounted, or may also be interconnected with a glass via interconnect structure 103 in the glass substrate 100, through a portion of the second interconnect structure 305 and a portion of the first interconnect structure 101.
The inorganic dielectric layer 104 is a multi-layer (the multi-layer is equal to or greater than two layers) stacked structure, the first interconnection structure 101 and the second interconnection structure 305 may be multi-layer stacked structures, the number of layers of the first interconnection structure 101 is the same as the number of layers of the inorganic dielectric layer 104, and the number of layers of the second interconnection structure 305 may be equal to or less than the number of layers of the inorganic dielectric layer 104. In an embodiment, when the inorganic dielectric layers 104 are N-layer stacked structures (N may be 2,3,4,5,6 or greater than 6), the corresponding first interconnect structure 101 is also an N-layer stacked structure, the second interconnect structure 305 is an N-layer or N-M-layer stacked structure (M is less than N and greater than 0, M may be 1,2 or greater than 2), that is, each of the inorganic dielectric layers 104 may have one of the first interconnect structures 101, and for the second interconnect structures 305, each of the inorganic dielectric layers 104 may have one of the second interconnect structures 305, or may have a corresponding L-layer second interconnect structure 305 in the L-layer (L is less than N) inorganic dielectric layer 104 near the upper surface of the glass substrate 101, while the N-L inorganic dielectric layers 104 far from the upper surface of the glass substrate 101 have no second interconnect structure 305 and only the first interconnect structure 101. In fig. 4, the inorganic dielectric layer 104 has three layers, and the corresponding first interconnect structure 101 also has three layers, and the second interconnect structure 305 has two layers, which are illustrated as examples, and the number of layers of the inorganic dielectric layer 104, the first interconnect structure 101, and the second interconnect structure 305 should not limit the protection scope of the present application, and the specific structures of the inorganic dielectric layer 104, the first interconnect structure 101, and the second interconnect structure 305 in fig. 4 are also merely illustrative, and the specific structures thereof should not limit the protection scope of the present application. In other embodiments, the inorganic dielectric layer 104 and the corresponding first interconnect structure 101 may have other layers, and the inorganic dielectric layer 104 and the corresponding first interconnect structure 101 may have other specific structures.
In an embodiment, the first interconnection structure 101 and the second interconnection structure 305 may include one or a combination of several of metal wires, metal plugs, damascene structures, or dual damascene structures, the material of the inorganic dielectric layer 104 is one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or a low dielectric constant material, and the material of the first interconnection structure and the second interconnection structure 305 is one or a combination of several (two or more) of Cu, al, W, ag, au, pt, ni, ti, ta, tiN, taN, taC, WN.
As is well known, the fabrication process of the existing semiconductor includes a front-end-of-line process and a back-end-of-line process. Semiconductor front-End-Of-Line processes are used to fabricate devices such as transistors, resistors, capacitors, etc., and internal wiring interconnecting these devices, and are further subdivided into front-End-Of-Line (FEOL, front End Of Line) processes used to fabricate devices such as transistors, resistors, capacitors, etc., and Back-End-Of-Line (BEOL) processes used to fabricate internal wiring interconnecting devices such as transistors, resistors, capacitors, etc. The back-end-of-line semiconductor processing generally includes wafer testing, thinning, die attach, rewiring (RDL, redistribution Layer), packaging, and the like. In the conventional packaging of semiconductor chips, re-wiring is usually performed by a re-wiring (RDL, redistribution Layer) process in a back-end of line process of the semiconductor, such as forming a resin material layer (such as ABF resin layer) on a surface of a substrate (such as an inorganic material substrate, a PCB substrate or a glass substrate), exposing and developing the resin material layer to form a recess, and forming a re-wiring layer in the recess and on an upper surface of the resin material, wherein the re-wiring layer is formed in a relatively small density. In the conventional semiconductor manufacturing process, back End Of Line (BEOL) in the front End Of Line (front End Of Line) is not applied to the Back End Of Line (Back End Of Line) in the front End Of Line (front End Of Line) Of the semiconductor.
The inventor finds that, due to the ultra-low flatness (extremely flat) and better thermal stability and mechanical stability of the glass substrate, the glass substrate is similar to the characteristics of the silicon wafer, even some characteristics are better than those of the silicon wafer, so that the BEOL process in the front-end of line process of the semiconductor can be very adapted when wiring is performed on the glass substrate, therefore, in an embodiment, the BEOL process in the front-end of line process of the semiconductor is used for the partial rewiring layer (the inorganic dielectric layer 104, the first interconnection structure 101 and the second interconnection structure 305) in the back-end process, and the density of the first interconnection structure 101 is higher than that of the third interconnection structure 102 (refer to fig. 5) formed on the lower surface of the glass substrate 101, so that the feature size of the first interconnection structure 101 is smaller than that of the third interconnection structure 102 formed later, namely, the semiconductor chip 100 can be more connected with the corresponding port (the first interconnection structure 101 and the second interconnection structure) in a larger size than the front-end of line process of the semiconductor chip, and the port can be more connected with the corresponding semiconductor chip 101 in a larger number of the front-end of line process.
In an embodiment, the density of the second interconnect structures 305 may be greater than or equal to the density of the first interconnect structures 101.
In one embodiment, the feature size of the first interconnect structure 101 and the second interconnect structure 305 is 0.2-0.8 microns, and the feature size of the third interconnect structure 102, which is subsequently formed, is 1.5-2.5 microns.
In an embodiment, before the inorganic dielectric layer 104, the first interconnect structure 101 and the second interconnect structure 305 are formed, an upper pad is formed on the upper surface of the glass substrate 100, and the upper pad is electrically connected to the upper end surface of the glass via interconnect structure 103, and the upper pad is also correspondingly used as a part of the first interconnect structure 101 and the second interconnect structure 305.
Referring to fig. 5, an organic passivation layer 105 and a third interconnect structure 102 located in the organic passivation layer 105 are formed on a lower surface of the glass substrate 100, the third interconnect structure 102 being electrically connected with a lower end surface of the glass via interconnect structure 103.
In one embodiment, the third interconnect structure 102 is a rewiring layer (RDL, redistribution Layer). The organic passivation layer 105 is a single-layer or multi-layer stacked structure, and the third interconnection structure 102 is a single-layer or multi-layer stacked structure, respectively. The material of the organic passivation layer 105 is a resin material, such as ABF resin or other resin, and the material of the third interconnect structure 102 is one or a combination of several Cu, al, W, ag, au, pt, ni, ti, ta, tiN, taN, taC, WN.
In an embodiment, a lower pad is formed on the lower surface of the glass substrate 100 before the organic passivation layer 105 and the third interconnect structure 102 are formed, and the lower pad is electrically connected to the lower end surface of the glass via interconnect structure 103, and the lower pad is also used as a part of the third interconnect structure 102.
In one embodiment, the organic passivation layer 105 and the third interconnect structure 102 are fabricated using RDL processing in a back-end-of-line semiconductor process. In one embodiment, the organic passivation layer 105 and the third interconnect structure 102 are fabricated by using an RDL process in a back-end-of-line semiconductor process, which includes forming the organic passivation layer 105 on the lower surface of the glass substrate 100, the forming process of the organic passivation layer 105 including spin coating, exposing and developing the organic passivation layer 105 to form a recess exposing the lower end surface of the glass via interconnect structure 103 or an upper pad formed on the lower end surface of the glass via interconnect structure 103, and forming the third interconnect structure 102 in the recess and on a portion of the upper surface of the organic passivation layer 105, wherein the forming process of the third interconnect structure 102 includes electroplating.
In an embodiment, the density of the formed third interconnect structure 102 is smaller than that of the first interconnect structure 101, the feature size of the third interconnect structure 102 is larger than that of the first interconnect structure 101, and the organic passivation layer 105 and the third interconnect structure 102 are formed after the inorganic dielectric layer 104 and the first interconnect structure 101 are formed, so that the lower surface of the glass substrate 100 can maintain higher flatness when the inorganic dielectric layer 104 and the first interconnect structure 101 are formed on the upper surface of the glass substrate 100, which is beneficial to BEOL process in the semiconductor front-end process with more advanced process on the upper surface of the glass substrate 100, so as to manufacture the first interconnect structure with higher density and smaller feature size.
Referring to fig. 6, at least one second semiconductor chip 201 is mounted on the upper surface of the inorganic dielectric layer 104, and the second semiconductor chip 201 is electrically connected to the first interconnection structure 101.
The second semiconductor chip 201 includes a back surface and an active surface, an integrated circuit (not shown) with a specific function is formed in the second semiconductor chip, and a plurality of external bumps 202 (the external bumps 202 are corresponding to a plurality of external ports of the second semiconductor chip) are formed on the active surface, and the external bumps 202 are electrically connected with the integrated circuit. The external bump 202 is a micro bump (μbump), and the material of the external bump 202 is one or a combination of several of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.
In an embodiment, the second semiconductor chip 201 is flip-chip mounted, specifically, the active surface of the second semiconductor chip 201 is mounted on the upper surface of the inorganic dielectric layer 104 in a downward manner, and the external bump 202 on the active surface of the second semiconductor chip 201 is soldered with the corresponding first interconnection structure 101.
The number of the mounted second semiconductor chips 201 is one or more (2 or more). Two second semiconductor chips 201 are mounted as an example in fig. 4.
In an embodiment, when the number of the mounted second semiconductor chips 201 is plural, the plural second semiconductor chips 201 may be semiconductor chips with the same function or different functions.
In an embodiment, the plurality of second semiconductor chips 201 may include logic chips and/or memory chips. In some embodiments, the logic chip may include, but is not limited to, a gate array, a cell substrate array, an embedded array, a structured Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), a Micro Processing Unit (MPU), a Micro Controller Unit (MCU), a logic Integrated Circuit (IC), an Application Processor (AP), a Display Driver IC (DDI), a Radio Frequency (RF) chip, a power chip, or a Complementary Metal Oxide Semiconductor (CMOS) image sensor. In some embodiments, the Memory chip may include, but is not limited to, a dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), a Static Random-Access Memory (SRAM), a magnetoresistive Random Access Memory (Magnetoresistive Random Access Memory, MRAM), a Phase-change Memory (PRAM), a resistive Memory (RESISTIVE RANDOM ACCESS MEMORY, RRAM), or a nonvolatile Memory chip (such as Flash (Flash)).
In one embodiment, referring to FIG. 7, further comprising forming a plurality of discrete first solder bumps 106 on a lower surface of the organic passivation layer 105, the first solder bumps 106 being electrically connected to the third interconnect structure 102.
The first solder bump 106 is used for a port when the package structure is connected to other substrates, other package structures and devices. In an embodiment, the material of the first solder bump 106 is one or a combination of several of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.
In an embodiment, before forming the first bonding bump 106, a second inorganic passivation layer (not shown in the drawing) may be further formed on a lower surface of the organic passivation layer 105, and the second inorganic passivation layer exposes a portion of a lower surface of the third interconnect structure 102.
In another embodiment of the present application, referring to fig. 8, the main difference between the present embodiment and the previous embodiment is that a passive device 401 is provided, the passive device 401 is embedded in the glass substrate 100 from the direction of the lower surface of the glass substrate 100, the passive device 401 is electrically connected with the third interconnection structure 102, so as to further improve the function and performance of the package structure, and the passive device 401 does not occupy the wiring space on the lower surface of the glass substrate 100 and does not increase the thickness of the package structure when embedded in the glass substrate 100. In a specific embodiment, a second groove (not shown) is formed in the glass substrate 100 in advance, the second groove is located on the lower surface of the glass substrate 100, and the passive device 401 is mounted in the second groove, so that the passive device 401 is embedded in the glass substrate 100. The passive device 401 embedded position is located below the semiconductor chip 300 embedded position where no internal wiring is provided.
In an embodiment, the passive device 401 is one or more of a resistor, a capacitor, or an inductor.
In another embodiment of the present application, referring to fig. 9, the main difference between the present embodiment and the previous embodiment is that a passive device 401 is provided, and the passive device 401 is mounted on the lower surface of the glass substrate 100, and is electrically connected to the third interconnection structure 102, so as to further improve the functions and performances of the package structure. Another embodiment of the present application further provides a semiconductor package structure, referring to fig. 7, including:
A glass substrate 100, wherein a plurality of discrete glass through hole interconnection structures 103 are provided in the glass substrate 100, the upper surface and the lower surface of the glass substrate 100 respectively expose the upper end surface and the lower end surface of the glass through hole interconnection structures 103, the glass substrate is further provided with a groove 110 (refer to fig. 1 or 3), and the groove 110 is positioned on the upper surface of the glass substrate 100;
A semiconductor chip 300 without internal wiring in the recess 110, the semiconductor chip 300 without internal wiring including a semiconductor substrate 302 and a device layer on an upper surface of the semiconductor substrate 302, the device layer having a semiconductor device 304 therein, the upper surface of the device layer of the semiconductor chip 300 without internal wiring being flush with the upper surface of the glass substrate 100;
An inorganic dielectric layer 104 located on an upper surface of the glass substrate 100 and an upper surface of a device layer of the semiconductor chip 300 without internal wiring, and a first interconnect structure 101 and a second interconnect structure 305 located in the inorganic dielectric layer 104, the first interconnect structure 101 being electrically connected to an upper end surface of the glass via interconnect structure 103, the second interconnect structure 305 being electrically connected to a semiconductor device 304 in the semiconductor chip 300 without internal wiring, and a part of the second interconnect structure 305 being also electrically connected to a part of the first interconnect structure 101, the semiconductor chip 300 without internal wiring, the second interconnect structure 305, and a part of the inorganic dielectric layer 104 constituting a first semiconductor chip 301;
An organic passivation layer 105 located on a lower surface of the glass substrate 100 and a third interconnect structure 102 located in the organic passivation layer 105, the third interconnect structure 102 being electrically connected to a lower end surface of the glass via interconnect structure 103, and a density of the first interconnect structure 101 being greater than a density of the third interconnect structure 102, a feature size of the first interconnect structure 101 being smaller than a feature size of the third interconnect structure 102;
At least one second semiconductor chip 201 mounted on the upper surface of the inorganic dielectric layer 104, where the second semiconductor chip 201 is electrically connected to the first interconnection structure 101.
In an embodiment, a plurality of discrete first solder bumps 106 located on the lower surface of the organic passivation layer 105 are further included, the first solder bumps 106 being electrically connected to the third interconnect structure 102.
In an embodiment, the first interconnect structure 101 and the second interconnect structure 305 comprise one or a combination of metal lines, metal plugs, damascene structures, or dual damascene structures, and the third interconnect structure 102 is a rewiring layer.
In an embodiment, the inorganic dielectric layer 104 is a multi-layer stacked structure, the first interconnection structure 101 and the second interconnection structure 305 are multi-layer stacked structures, the material of the inorganic dielectric layer 104 is one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer 105 is a resin material, and the material of the first interconnection structure 101, the second interconnection structure 305 and the third interconnection structure 102 is one or a combination of several of Cu, al, W, ag, au, pt, ni, ti, ta, tiN, taN, taC, WN.
In an embodiment, the inorganic dielectric layer 104, the first interconnect structure 101 and the second interconnect structure 305 are formed by BEOL process in front-end-of-line semiconductor process, the organic passivation layer 105 and the third interconnect structure 102 are formed by RDL process in back-end-of-line semiconductor process, the density of the first interconnect structure 101 is greater than that of the third interconnect structure 102, the feature size of the first interconnect structure 101 is smaller than that of the third interconnect structure 102, and the density of the second interconnect structure 305 is greater than or equal to that of the first interconnect structure 101. In one embodiment, the feature size of the first interconnect structure 101 and the second interconnect structure 305 is 0.2-0.8 microns and the feature size of the third interconnect structure 102 is 1.5-2.5 microns.
In an embodiment, referring to fig. 2, the device layer further includes an underlying inorganic dielectric layer 303 on the upper surface of the semiconductor substrate 302, the underlying inorganic dielectric layer 303 covering the semiconductor device 304, and the device layer further includes a conductive connection structure 307 in the underlying inorganic dielectric layer 303 electrically connected to the active region of the semiconductor device 304, the conductive connection structure 307 being electrically connected to the second interconnect structure 305.
In one embodiment, the semiconductor device 304 includes one or a combination of bipolar transistors, field effect transistors (see fig. 9), and insulated gate bipolar transistors.
In another embodiment, the semiconductor device 304 may further include one or a combination of several of a diode, a resistor, a capacitor, and an inductor.
In an embodiment, the package structure further includes a passive device 401, the passive device 401 is mounted on the lower surface of the glass substrate (refer to fig. 9) or embedded in the glass substrate 101 from the direction of the lower surface of the glass substrate 101 (refer to fig. 8), and the passive device 401 is electrically connected to the third interconnection structure 102.
It should be noted that, in the foregoing embodiment of the semiconductor package structure, the same or similar parts as those in the foregoing embodiment of the method for forming a semiconductor package structure are not described in detail, and reference is made to the definition or description of the corresponding parts in the foregoing embodiment of the method for forming a semiconductor package structure.
Although the present application has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present application by using the methods and technical matters disclosed above without departing from the spirit and scope of the present application, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present application are within the scope of the technical matters of the present application.
Claims (21)
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