CN119690184A - Transient enhancement circuit, linear voltage regulator and transient enhancement method - Google Patents
Transient enhancement circuit, linear voltage regulator and transient enhancement method Download PDFInfo
- Publication number
- CN119690184A CN119690184A CN202411872478.3A CN202411872478A CN119690184A CN 119690184 A CN119690184 A CN 119690184A CN 202411872478 A CN202411872478 A CN 202411872478A CN 119690184 A CN119690184 A CN 119690184A
- Authority
- CN
- China
- Prior art keywords
- circuit
- control signal
- transistor
- control
- mirror
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
本发明公开了一种瞬态增强电路、线性稳压器及瞬态增强方法，瞬态增强电路包括：比较电路、延时电路以及补偿电路。比较电路用于接收待调节电路的输出电流，并将输出电流与参考电流进行比较产生第一控制信号，同时基于待调节电路的输出电流产生表征输出电流大小的控制电压；延时电路用于对第一控制信号进行延迟产生第二控制信号；补偿电路用于基于控制电压和第二控制信号调节自身的电阻值和/或电容值以给待调节电路环路提供零点。根据本发明的瞬态增强电路、线性稳压器及瞬态增强方法，能够通过检测功率管上电流变化来判断系统进入负载跳变阶段，并在此阶段内通过瞬态增强电路增大环路带宽进而优化瞬态响应特性。
The present invention discloses a transient enhancement circuit, a linear voltage regulator and a transient enhancement method. The transient enhancement circuit includes: a comparison circuit, a delay circuit and a compensation circuit. The comparison circuit is used to receive the output current of the circuit to be adjusted, and compare the output current with the reference current to generate a first control signal, and at the same time generate a control voltage representing the magnitude of the output current based on the output current of the circuit to be adjusted; the delay circuit is used to delay the first control signal to generate a second control signal; the compensation circuit is used to adjust its own resistance value and/or capacitance value based on the control voltage and the second control signal to provide a zero point for the loop of the circuit to be adjusted. According to the transient enhancement circuit, the linear voltage regulator and the transient enhancement method of the present invention, it is possible to judge whether the system has entered the load jump stage by detecting the current change on the power tube, and in this stage, the loop bandwidth is increased by the transient enhancement circuit to optimize the transient response characteristics.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a transient enhancement circuit, a linear voltage stabilizer and a transient enhancement method.
Background
Linear voltage regulators have become an important component of portable electronic products by virtue of low noise, small size and the like, and with more and more applications in highly integrated system designs, the transient response of the whole circuit has become more important, and in particular, for example, in application circuits with ultra-low power consumption, the transient response speed has also been more and more demanded.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a transient enhancement circuit, a linear voltage stabilizer and a transient enhancement method, which can optimize and improve loop bandwidth in a load jump stage, accelerate node establishment speed and improve output transient response.
In order to achieve the above object, a specific embodiment of the present invention provides a transient enhancement circuit for a circuit to be regulated, where the transient enhancement circuit includes a comparison circuit, a delay circuit, and a compensation circuit.
The circuit comprises a comparison circuit, a delay circuit and a compensation circuit, wherein the comparison circuit is used for receiving output current of a circuit to be regulated, comparing the output current with reference current to generate a first control signal, generating control voltage representing the magnitude of the output current based on the output current of the circuit to be regulated, the delay circuit is used for delaying the first control signal to generate a second control signal, and the compensation circuit is used for regulating the resistance value and/or the capacitance value of the compensation circuit based on the control voltage and the second control signal so as to provide zero point for a circuit loop to be regulated.
In one or more embodiments of the present invention, the compensation circuit includes an adjustment unit, where the adjustment unit includes a first transistor and an adjustment module, the first transistor and the adjustment module are connected in series, the first transistor controls an on-state of itself based on a control voltage to cooperate with the adjustment module to adjust a resistance value and/or a capacitance value of the compensation circuit itself, and the adjustment module controls on-state or off-state of itself based on a second control signal to adjust the resistance value and/or the capacitance value of itself.
In one or more embodiments of the present invention, the first transistor is turned on under the control of the control voltage when the output current of the circuit to be regulated changes transiently, the regulating module increases the resistance value and/or capacitance value of the compensating circuit under the control of the ineffective second control signal generated when the output current of the circuit to be regulated changes transiently, based on the resistance value and/or capacitance value of the regulating module and the turning-on degree of the first transistor, and the regulating module is turned on under the control of the effective second control signal generated by the delay to reduce the resistance value and/or capacitance value of the compensating circuit by reducing the resistance value and/or capacitance value of the regulating module.
In one or more embodiments of the present invention, the adjusting module includes a resistor unit and a second transistor, the resistor unit is connected in series with the first transistor, the second transistor is connected in parallel with the resistor unit, and a control terminal of the second transistor is used for receiving a second control signal.
In one or more embodiments of the present invention, the compensation circuit further includes a first capacitor and a first resistor connected in series between the circuit to be adjusted and the first reference voltage, a first end formed by the second transistor and the resistor unit connected in parallel with each other is connected to the first capacitor and the first resistor, and a second end formed by the second transistor and the resistor unit connected in parallel with each other is connected to the second transistor.
In one or more embodiments of the invention, the comparison circuit comprises a current mirror unit and a current source for generating a reference current, the current mirror unit being connected to the circuit to be regulated and to the current source for mirroring the output current and comparing it with the reference current to generate the first control signal.
In one or more embodiments of the present invention, the current mirror unit includes a first mirror, a second mirror, and a third mirror, the control terminal of the first mirror is connected to the band adjustment circuit, the first terminal of the first mirror is connected to the second reference voltage, the second terminal of the second mirror is connected to the second terminal of the first mirror, the control terminal of the second mirror is connected to the control terminal of the third mirror and the second terminal of the second mirror to generate the control voltage, the first terminal of the second mirror and the first terminal of the third mirror are connected to the first reference voltage, the second terminal of the third mirror is connected to the first terminal of the current source to generate the first control signal, and the second terminal of the current source is connected to the second reference voltage.
In one or more embodiments of the invention, the transient enhancement circuit further comprises a schmitt trigger, the schmitt trigger being connected between the comparison circuit and the delay circuit.
In one or more embodiments of the present invention, the transient enhancement circuit further includes a shaping unit, an input end of the shaping unit is connected to the delay circuit, and the shaping unit is configured to shape the second control signal and output a third control signal to control the compensation circuit.
The invention also discloses a linear voltage stabilizer, which comprises the transient enhancement circuit, wherein the comparison circuit is connected with the control end of the power tube of the linear voltage stabilizer to receive the output current on the power tube, and the compensation circuit is connected with the output end of the amplifier of the linear voltage stabilizer to carry out zero compensation.
The invention also discloses a transient enhancement method, which comprises the following steps of:
When the output current of the circuit to be regulated is subjected to transient variation, comparing the output current with a reference current through a comparison circuit to generate a first control signal, and generating a control voltage representing the magnitude of the output current based on the output current of the circuit to be regulated;
Delaying the first control signal through a delay circuit to generate a second control signal;
the resistance value and/or the capacitance value of the circuit loop to be regulated are/is regulated by the compensation circuit based on the control voltage and the second control signal so as to provide zero point for the circuit loop to be regulated.
In one or more embodiments of the present invention, the adjusting, by the compensation circuit, the resistance value and/or the capacitance value of itself based on the control voltage and the second control signal to provide the zero point to the circuit loop to be adjusted includes:
when the output current of the circuit to be regulated is subjected to transient variation, the first transistor is started based on the control of the control voltage, and the resistance value and/or the capacitance value of the first transistor are increased based on the resistance value and/or the capacitance value of the first transistor and the starting degree of the first transistor under the control of an invalid second control signal through regulation control;
after the delay time, the adjusting module is started under the control of the effective second control signal generated by the delay, so that the resistance value and/or the capacitance value of the compensating circuit are reduced by reducing the resistance value and/or the capacitance value of the compensating circuit.
Compared with the prior art, the transient enhancement circuit and the transient enhancement method can be applied to various circuits, wherein the transient enhancement circuit and the transient enhancement method are widely applied to linear voltage regulators, particularly ultra-low power consumption linear voltage regulators, and because the loop quiescent current of the ultra-low power consumption linear voltage regulators under light load or no load is extremely small, when the load is rapidly changed, the loop current is small, the node establishment speed is low, and the transient response has a larger gap compared with the common linear voltage regulators.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a linear voltage regulator combined with a transient enhancement circuit in an embodiment.
Fig. 2 is a waveform diagram of each node of the transient enhancement circuit in an embodiment.
Detailed Description
In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection via an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance, and may also include a connection via other active or passive devices, such as a circuit or component via a switch, follower, etc., that achieves the same or similar functional purpose. Furthermore, in the invention, words such as "first," "second," and the like are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number, or order between the technical features.
In the detailed description of the present specification, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.
Various operations in the specification may be described as multiple discrete acts or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed in additional embodiments and/or the described operations may be omitted.
For the purposes of this disclosure, the phrase "a and/or B" refers to (a), (B) or (a and B). For the purposes of this disclosure, the phrase "a, B and/or C" refers to (a), (B), (C), (a and B), (a and C), (B and C) or (a, B and C).
Various components, devices may be referred to or shown herein in the singular (e.g., "transistor," "switch," etc.), but this is for convenience of discussion only and any element referred to in the singular may comprise a plurality of such elements in accordance with the teachings herein.
The description uses the phrases "in one embodiment" or "in other embodiments" or "in some embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.
As shown in fig. 1, a transient enhancement circuit in an embodiment of the present invention is used for a circuit to be regulated, and the transient enhancement circuit includes a comparison circuit 10, a delay circuit 20, and a compensation circuit 30.
The comparison circuit 10 is configured to receive the output current ILOAD of the circuit to be regulated, and compare the output current ILOAD with the reference current IBS to generate the first control signal V1, and generate the control voltage VNB indicative of the magnitude of the output current ILOAD based on the output current ILOAD of the circuit to be regulated. The delay circuit 20 is used for delaying the first control signal V1 to generate the second control signal V2. The compensation circuit 30 is configured to adjust its resistance value based on the control of the control voltage VNB and the second control signal V2 to provide a zero point for the circuit loop to be adjusted. In an embodiment, when the output current ILOAD of the circuit to be regulated changes transiently, the compensation circuit 30 increases its own resistance value based on the control voltage VNB to provide the circuit loop to be regulated with a corresponding zero point, and after the delay time of the delay circuit 20, the compensation circuit 30 decreases its own resistance value based on the control of the second control signal V2 to provide the circuit loop to be regulated with a corresponding zero point.
In other embodiments, the compensation circuit 30 may also adjust its capacitance value based on the control voltage VNB to provide a corresponding zero point for the circuit loop to be adjusted, and adjust its capacitance value based on the control of the second control signal V2 to provide a corresponding zero point for the circuit loop to be adjusted after the delay time of the delay circuit 20, or the compensation circuit 30 may also adjust its resistance value and capacitance value simultaneously to provide a corresponding zero point.
In one embodiment, the circuit to be regulated may be a linear regulator. As shown in fig. 1, the linear regulator includes an amplifier EA, a buffer tube MK, a mirror tube MU, a power tube MH, and a feedback unit. The output end of the amplifier EA is connected to the control end of the buffer tube MK and the compensation circuit 30, the first end of the buffer tube MK is connected to the first reference voltage AVSS, the second end of the buffer tube MK is connected to the second end of the mirror tube MU and the control end of the mirror tube MU, the control end of the power tube MH is connected to the control end of the mirror tube MU, the first end of the mirror tube MU and the first end of the power tube MH are connected to the second reference voltage AVDD, and in one embodiment, the first reference voltage AVSS is the ground voltage, and the second reference voltage AVDD is the power supply voltage. The second end of the mirror image tube MU is connected with the feedback unit to generate an output voltage VOUT, the feedback unit is connected with the first input end of the amplifier EA, the feedback unit generates a feedback voltage VFB based on the output voltage VOUT, the first output end of the amplifier EA is connected with the feedback unit to receive the feedback voltage VFB, the second input end of the amplifier EA is used for receiving the reference voltage VREF, in one embodiment, the first input end of the amplifier EA is a negative input end, and the second input end of the amplifier EA is a positive input end. In other embodiments, the circuit to be regulated may be other circuits.
In one embodiment, the feedback unit includes a first feedback resistor Ra, a second feedback resistor Rb, and a filter capacitor CFF. The first end of the first feedback resistor Ra is connected to the second end of the power tube MH, the second end of the first feedback resistor Ra is connected to the first end of the second feedback resistor Rb and the first input end of the amplifier EA, and the second end of the second feedback resistor Rb is connected to the first reference voltage AVSS. In other embodiments, the filter capacitor CFF may not be provided.
As shown in fig. 1, the comparison circuit 10 includes a current mirror unit and a current source A1, wherein the current source A1 is used for generating a reference current IBS, the current mirror unit is connected to the circuit to be regulated and the current source A1 to mirror the output current ILOAD and compare the output current ILOAD with the reference current IBS to generate a first control signal V1, and the current mirror unit generates a control voltage VNB representing the magnitude of the output current ILOAD during the process of mirroring the output current ILOAD.
In one embodiment, the current mirror unit includes a first mirror MX1, a second mirror MX2, and a third mirror MX3. The control end of the first mirror tube MX1 is connected to the control end of the power tube MH, the first end of the first mirror tube MX1 is connected to the second reference voltage AVDD, the ratio of the width-to-length ratio of the power tube MH to the width-to-length ratio of the first mirror tube MX1 may be n:1, so that the output current ILOAD on the power tube MH is mirrored in proportion by the first mirror tube MX1, the second end of the second mirror tube MX2 is connected to the second end of the first mirror tube MX1, the control end of the second mirror tube MX2 is connected to the control end of the third mirror tube MX3 and the second end of the second mirror tube MX2 to generate the control voltage VNB, and the first ends of the second mirror tube MX2 and the third mirror tube MX3 are connected to the first reference voltage AVSS. A second terminal of the third mirrored tube MX3 is connected to a first terminal of the current source A1 for generating the first control signal V1, and a second terminal of the current source A1 is connected to the second reference voltage AVDD. The ratio of the width-to-length ratio of the second mirror tube MX2 to the width-to-length ratio of the third mirror tube MX3 may be m:1, and the current on the first mirror tube MX1 is further mirrored through the second mirror tube MX2 and the third mirror tube MX3, and compared with the reference current IBS generated by the current source A1 to generate the first control signal V1.
As shown in fig. 1, the transient enhancement circuit further includes a schmitt trigger ST, where the schmitt trigger ST is connected between the comparison circuit 10 and the delay circuit 20, and is configured to invert the first control signal V1 to output an intermediate signal and prevent false triggering of the subsequent circuit through its own hysteresis interval. In other embodiments, the schmitt trigger ST may not be provided.
In one embodiment, as shown in FIG. 1, the delay circuit 20 includes a resistor R0 and a capacitor C0. The first end of the resistor R0 is connected to the output terminal of the schmitt trigger ST, the second end of the resistor R0 is connected to the first end of the capacitor C0, and the second end of the capacitor C0 is connected to the first reference voltage AVSS. The intermediate signal output from the schmitt trigger ST is delayed by the resistor R0 and the capacitor C0 to generate the second control signal V2. In other embodiments, the delay circuit 20 may be other circuit configurations.
As illustrated in fig. 1, the transient enhancement circuit further comprises a shaping unit. The input end of the shaping unit is connected to the delay circuit 20, and the shaping unit is configured to shape the second control signal and output a third control signal v_ctrl to control the compensation circuit 30. In an embodiment, the shaping unit includes a first inverter ANV1 and a second inverter AVN2, the first inverter ANV1 and the second inverter AVN2 are connected in series and connected to the second end of the resistor R0, and the second control signal V2 is shaped by the first inverter ANV1 and the second inverter AVN2 to output a third control signal v_ctrl. In other embodiments, the shaping unit may be of other circuit structures, or may not be provided, and if the shaping unit is not provided, the third control signal v_ctrl and the second control signal V2 submitted above and below are the same signal.
As shown in fig. 1, the compensation circuit 30 includes a first capacitor C1, a first resistor R1 and an adjusting unit, wherein a first end of the first capacitor C1 is connected to the output end of the amplifier EA, a second end of the first capacitor C1 is connected to a first end of the first resistor R1, and a second end of the first resistor R1 is connected to the first reference voltage AVSS. The adjusting unit is connected to the first end of the first resistor R1 and the first reference voltage AVSS, and reduces the resistance value of the compensating circuit 30 itself based on the control voltage VNB and reduces the resistance value of the compensating circuit 30 itself again based on the control of the third control signal v_ctrl (if the shaping unit is not provided, the compensating circuit 30 is directly controlled by the second control signal V2). In other embodiments, the adjusting unit is connected to the first capacitor C1, and the adjusting unit can adjust the capacitance value of the compensating circuit 30 itself based on the control voltage VNB, and adjust the capacitance value of the compensating circuit 30 itself again based on the control of the second control signal V2. Or the adjusting unit is connected to the first capacitor C1 and the first resistor R1, and the adjusting unit can adjust the capacitance value and the resistance value of the compensating circuit 30 itself based on the control voltage VNB and adjust the capacitance value and the resistance value of the compensating circuit 30 itself again based on the control of the third control signal v_ctrl.
As shown in fig. 1, in an embodiment, the adjusting unit includes a first transistor M1 and an adjusting module, the first transistor M1 and the adjusting module are connected in series, the adjusting module controls on or off of itself based on the third control signal v_ctrl to adjust the resistance value of itself, and the first transistor M1 controls on degree of itself based on the control voltage VNB to adjust the resistance value of the compensating circuit 30 in cooperation with the adjusting module.
Specifically, when the output current ILOAD changes transiently, the first transistor M1 is turned on based on the control of the control voltage VNB, and the adjustment module is turned on based on its own resistance value and/or capacitance value and the turned-on level of the first transistor M1 to increase the resistance value of the compensation circuit 30 under the control of the ineffective third control signal v_ctrl generated when the output current ILOAD changes transiently, so as to decrease the resistance value of the compensation circuit by decreasing its own resistance value and/or capacitance value, wherein "increasing the resistance value of the compensation circuit 30" is compared to when the adjustment module is turned on. In one embodiment, the inactive third control signal v_ctrl is a low level third control signal v_ctrl, and the active third control signal v_ctrl is a high level third control signal v_ctrl.
In other embodiments, the adjusting module controls on or off of itself based on the third control signal v_ctrl to adjust the capacitance value of itself, and the first transistor M1 controls on degree of itself based on the control voltage VNB to coordinate with the adjusting module to adjust the capacitance value of the compensating circuit 30. Or the adjusting module controls the self-turn-on or turn-off of the first transistor M1 to adjust the self-capacitance value and the self-resistance value based on the third control signal v_ctrl, and the first transistor M1 controls the self-turn-on degree based on the control voltage VNB to adjust the capacitance value and the self-resistance value of the compensating circuit 30 in cooperation with the adjusting module.
In an embodiment, as shown in fig. 1, the adjusting module includes a resistor unit R2 and a second transistor M2, the resistor unit R2 is connected in series with the first transistor M1, the second transistor M2 is connected in parallel with the resistor unit R2, and a control terminal of the second transistor M2 is configured to receive the third control signal v_ctrl. In other embodiments, the resistor unit R2 may be replaced by a capacitor unit, and the adjusting module is connected in parallel with the first capacitor C1, or a series-parallel resistor and capacitor are used to replace the resistor unit R2, and the number of the second transistors M2 may be set according to the number of resistors and capacitors.
As can be seen from fig. 1, the dynamic zero point can be compensated for the loop by controlling the on-state of the first transistor M1 by controlling the voltage VNB to adjust the impedance of the compensation circuit 30, so as to ensure the loop stability under light and heavy loads. The comparison circuit 10 detects the load condition of the linear voltage regulator when the transient boost circuit is required to switch by mirroring the output current ILOAD of the power transistor MH and comparing the mirrored output current ILOAD with the reference current IBS, and when the output current ILOAD becomes larger, the control voltage VNB increases, and the switching point of the comparison circuit 10 may be expressed as iload=m×n×ibs. When the output current ILOAD on the left side of the formula is greater than that on the right side, the first control signal V1 is pulled down, and a delayed third control signal v_ctrl is sent out after passing through the delay circuit 20 on the subsequent stage, so that the signal controls the first transistor M1.
When the load changes from light load or no load to heavy load, the change rate of the control voltage VNB is faster, the resistance value of the first transistor M1 will be smaller, but the third control signal v_ctrl is actually increased by a delay time compared with the first control signal V1 of the detected load change, that is, after a delay time, the third control signal v_ctrl will be changed from low to high, during the time when the third control signal v_ctrl is at low level, the resistor unit R2 is connected, at this time, the zero point generated by the compensation circuit 30 is determined by the resistor unit R2 and the resistance value of the first transistor M1 together, compared with the case that the third control signal v_ctrl is at high level, and the second transistor M2 is turned on to short-circuit the resistor unit R2 to generate the corresponding zero point.
The loop compensation zero point positions in both cases where the third control signal v_ctrl is low or high can be expressed as:
In the load transient variation, the zero point expression generated by the low level of the third control signal v_ctrl is z1=1/{ c1 [ r1| (r2+rm1) ] }, the zero point expression generated by the high level of the third control signal v_ctrl is z2=1/{ c1 [ (r1|rm 1) ] }, RM1 is the resistance value of the first transistor M1, and it can be seen that when the first transistor M1 is turned on and the second transistor M2 is turned off, the resistance of the whole compensation circuit 30 is larger due to the connection of the resistance unit R2 than that of the whole compensation circuit 30 which is shorted by the turned on of the second transistor M2, and both the zero point Z1 and the zero point Z2 can be changed according to the related parameter.
Fig. 2 shows actual working waveforms of each node when the load changes from no load or light load to heavy load, where the time point t1 corresponds to the time point when the load changes from light load or no load to heavy load, and the signal inversion occurs in the first control signal V1 by detecting, where the time of generating the first control signal V1 is mainly related to the change of the control voltage VNB caused by the change of the output current ILOAD on the power tube MH, the time point t2 is the time point when the third control signal v_ctrl is inverted, the difference between the two times is mainly determined by the delay circuit 20 formed by the resistor R0 and the capacitor C0, and the middle Δt time is the time period when the second transistor M2 in the loop is not yet opened, and it is in this time period that the zero point position in the loop in the transient change is moved to the left by accessing the resistor unit R2 to increase the bandwidth, so as to optimize the transient response.
The application also discloses a linear voltage stabilizer, which comprises the transient enhancement circuit, wherein the comparison circuit 10 is connected with the control end of a power tube MH of the linear voltage stabilizer to receive the output current ILOAD on the power tube, and the compensation circuit 30 is connected with the output end of an amplifier EA of the linear voltage stabilizer to carry out zero point compensation.
The application also discloses a transient enhancement method, which is based on the transient enhancement circuit, and comprises the following steps:
When the output current ILOAD of the circuit to be regulated is subjected to transient variation, the comparison circuit 10 compares the output current ILOAD with the reference current IBS to generate the first control signal V1, and simultaneously generates the control voltage VNB representing the magnitude of the output current ILOAD based on the output current ILOAD of the circuit to be regulated. In one embodiment, the circuit to be regulated may be a linear voltage regulator as described above.
The first control signal V1 is delayed by the delay circuit 20 to generate the second control signal V2.
The resistance and/or capacitance of itself is adjusted by the compensation circuit 30 based on the control voltage VNB and the second control signal V2 to provide a zero point for the circuit loop to be adjusted.
When the output current ILOAD of the circuit to be regulated is subjected to transient variation, the first transistor M1 is turned on based on the control of the control voltage VNB, and the adjustment module is controlled by the inactive second control signal V2 to increase the resistance value and/or capacitance value of the compensation circuit 30 based on the resistance value and/or capacitance value of the adjustment module and the turn-on degree of the first transistor M1;
After the delay time, the compensation circuit 30 is turned on under the control of the effective second control signal V2 generated by the delay through the adjusting module to reduce the resistance value and/or capacitance value of the compensation circuit by reducing the resistance value and/or capacitance value of the compensation circuit;
Controlled by the inactive and active second control signal V2 to provide corresponding zero points at different time periods. In the case where the shaping unit is provided, the second control signal V2 is the third control signal v_ctrl output by the shaping unit.
The application also discloses a chip comprising the transient enhancement circuit.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (12)
1. A transient enhancement circuit for a circuit to be conditioned, the transient enhancement circuit comprising:
The comparison circuit is used for receiving the output current of the circuit to be regulated, comparing the output current with the reference current to generate a first control signal, and generating a control voltage representing the magnitude of the output current based on the output current of the circuit to be regulated;
a delay circuit for delaying the first control signal to generate a second control signal, and
And the compensation circuit is used for adjusting the resistance value and/or the capacitance value of the compensation circuit based on the control voltage and the second control signal so as to provide zero point for the circuit loop to be adjusted.
2. The transient enhancement circuit according to claim 1, wherein the compensation circuit comprises an adjustment unit, the adjustment unit comprises a first transistor and an adjustment module, the first transistor and the adjustment module are connected in series, the first transistor controls the turn-on degree of the first transistor based on the control voltage so as to cooperate with the adjustment module to adjust the resistance value and/or the capacitance value of the compensation circuit, and the adjustment module controls the turn-on or turn-off of the first transistor based on the second control signal so as to adjust the resistance value and/or the capacitance value of the compensation circuit.
3. The transient enhancement circuit according to claim 2, wherein the first transistor is turned on under control of a control voltage when an output current of the circuit to be regulated changes transiently, the regulating module is controlled by an ineffective second control signal generated when the output current of the circuit to be regulated changes transiently to increase the resistance value and/or the capacitance value of the compensating circuit based on the resistance value and/or the capacitance value of the regulating module and the degree of turning on the first transistor, and the regulating module is turned on under control of an effective second control signal generated by delaying to decrease the resistance value and/or the capacitance value of the compensating circuit by decreasing the resistance value and/or the capacitance value of the regulating module.
4. The transient enhancement circuit of claim 2, wherein the regulation module comprises a resistor unit and a second transistor, the resistor unit and the first transistor being connected in series, the second transistor and the resistor unit being connected in parallel, a control terminal of the second transistor being configured to receive the second control signal.
5. The transient enhancement circuit of claim 4, wherein the compensation circuit further comprises a first capacitor and a first resistor, the first capacitor and the first resistor are connected in series with each other between the circuit to be regulated and the first reference voltage, a first end of the second transistor formed by connecting the second transistor and the resistor unit in parallel with each other is connected to the first capacitor and the first resistor, and a second end of the second transistor formed by connecting the second transistor and the resistor unit in parallel with each other is connected to the second transistor.
6. The transient enhancement circuit of claim 1, wherein the comparison circuit comprises a current mirror unit and a current source for generating a reference current, the current mirror unit being coupled to the circuit to be regulated and the current source to mirror the output current and compare it to the reference current to generate the first control signal.
7. The transient boost circuit of claim 6, wherein the current mirror unit comprises a first mirror, a second mirror, and a third mirror, the control terminal of the first mirror is coupled to the band adjustment circuit, the first terminal of the first mirror is coupled to the second reference voltage, the second terminal of the second mirror is coupled to the second terminal of the first mirror, the control terminal of the second mirror is coupled to the control terminal of the third mirror and the second terminal of the second mirror to generate the control voltage, the first terminal of the second mirror and the first terminal of the third mirror are coupled to the first reference voltage, the second terminal of the third mirror is coupled to the first terminal of the current source to generate the first control signal, and the second terminal of the current source is coupled to the second reference voltage.
8. The transient enhancement circuit of claim 1, further comprising a schmitt trigger coupled between the comparison circuit and the delay circuit.
9. The transient enhancement circuit of claim 1, further comprising a shaping unit, wherein an input of the shaping unit is connected to the delay circuit, and the shaping unit is configured to shape the second control signal to output a third control signal to control the compensation circuit.
10. A linear voltage regulator, comprising the transient enhancement circuit according to any one of claims 1 to 9, wherein the comparison circuit is connected to a control terminal of a power tube of the linear voltage regulator to receive an output current on the power tube, and the compensation circuit is connected to an output terminal of an amplifier of the linear voltage regulator to perform zero compensation.
11. A transient enhancement method based on the transient enhancement circuit according to any one of claims 1 to 9, the transient enhancement method comprising:
When the output current of the circuit to be regulated is subjected to transient variation, comparing the output current with a reference current through a comparison circuit to generate a first control signal, and generating a control voltage representing the magnitude of the output current based on the output current of the circuit to be regulated;
Delaying the first control signal through a delay circuit to generate a second control signal;
the resistance value and/or the capacitance value of the circuit loop to be regulated are/is regulated by the compensation circuit based on the control voltage and the second control signal so as to provide zero point for the circuit loop to be regulated.
12. The transient enhancement method of claim 11, wherein the adjusting, by the compensation circuit, the resistance value and/or the capacitance value of itself based on the control voltage and the second control signal to provide a zero point to the circuit loop to be adjusted comprises:
When the output current of the circuit to be regulated is subjected to transient variation, the first transistor is started based on the control of the control voltage, and the resistance value and/or the capacitance value of the first transistor are/is increased based on the resistance value and/or the capacitance value of the first transistor and the starting degree of the first transistor under the control of an invalid second control signal through the regulating module;
after the delay time, the adjusting module is started under the control of the effective second control signal generated by the delay, so that the resistance value and/or the capacitance value of the compensating circuit are reduced by reducing the resistance value and/or the capacitance value of the compensating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411872478.3A CN119690184A (en) | 2024-12-18 | 2024-12-18 | Transient enhancement circuit, linear voltage regulator and transient enhancement method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411872478.3A CN119690184A (en) | 2024-12-18 | 2024-12-18 | Transient enhancement circuit, linear voltage regulator and transient enhancement method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119690184A true CN119690184A (en) | 2025-03-25 |
Family
ID=95034920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411872478.3A Pending CN119690184A (en) | 2024-12-18 | 2024-12-18 | Transient enhancement circuit, linear voltage regulator and transient enhancement method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119690184A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7863875B1 (en) * | 2008-04-23 | 2011-01-04 | Fairchild Semiconductor Corporation | Non-linear control techniques for improving transient response to load current step change |
| CN103427636A (en) * | 2013-08-27 | 2013-12-04 | 电子科技大学 | Transient response enhancement control circuit used for switch power source |
| CN106774578A (en) * | 2017-01-10 | 2017-05-31 | 南方科技大学 | Low dropout linear regulator |
| CN113721688A (en) * | 2021-09-08 | 2021-11-30 | 成都芯港微电子有限公司 | High PSRR (power supply rejection ratio) and high transient response low dropout linear regulator capable of being quickly and stably connected |
| CN113835463A (en) * | 2021-09-30 | 2021-12-24 | 西北工业大学太仓长三角研究院 | A Small Area Fast Transient Response Fully On-Chip Integrated LDO Circuit |
| CN115328255A (en) * | 2022-09-11 | 2022-11-11 | 北京工业大学 | Low-power-consumption light-heavy load conversion LDO circuit based on voltage comparator |
| CN115599152A (en) * | 2022-09-09 | 2023-01-13 | 豪威集成电路（成都）有限公司（Cn） | Multiple LDO output voltage circuit with overshoot suppression and adaptive compensation |
| CN116069116A (en) * | 2023-03-01 | 2023-05-05 | 北京奕斯伟计算技术股份有限公司 | Low-dropout linear regulator LDO circuit, dynamic compensation method and electronic equipment |
| CN116627202A (en) * | 2023-05-26 | 2023-08-22 | 西安紫光国芯半导体股份有限公司 | Voltage regulating circuit, chip and module equipment |
-
2024
- 2024-12-18 CN CN202411872478.3A patent/CN119690184A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7863875B1 (en) * | 2008-04-23 | 2011-01-04 | Fairchild Semiconductor Corporation | Non-linear control techniques for improving transient response to load current step change |
| CN103427636A (en) * | 2013-08-27 | 2013-12-04 | 电子科技大学 | Transient response enhancement control circuit used for switch power source |
| CN106774578A (en) * | 2017-01-10 | 2017-05-31 | 南方科技大学 | Low dropout linear regulator |
| CN113721688A (en) * | 2021-09-08 | 2021-11-30 | 成都芯港微电子有限公司 | High PSRR (power supply rejection ratio) and high transient response low dropout linear regulator capable of being quickly and stably connected |
| CN113835463A (en) * | 2021-09-30 | 2021-12-24 | 西北工业大学太仓长三角研究院 | A Small Area Fast Transient Response Fully On-Chip Integrated LDO Circuit |
| CN115599152A (en) * | 2022-09-09 | 2023-01-13 | 豪威集成电路（成都）有限公司（Cn） | Multiple LDO output voltage circuit with overshoot suppression and adaptive compensation |
| CN115328255A (en) * | 2022-09-11 | 2022-11-11 | 北京工业大学 | Low-power-consumption light-heavy load conversion LDO circuit based on voltage comparator |
| CN116069116A (en) * | 2023-03-01 | 2023-05-05 | 北京奕斯伟计算技术股份有限公司 | Low-dropout linear regulator LDO circuit, dynamic compensation method and electronic equipment |
| CN116627202A (en) * | 2023-05-26 | 2023-08-22 | 西安紫光国芯半导体股份有限公司 | Voltage regulating circuit, chip and module equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113110694B (en) | Low dropout regulator circuit with current surge suppression | |
| US11314267B2 (en) | Adjuster and chip | |
| CN108508951B (en) | LDO voltage regulator circuit without off-chip capacitor | |
| KR101508391B1 (en) | Voltage regulator | |
| JP6785736B2 (en) | An electronic circuit that reduces undershoot of the output of the voltage regulator | |
| EP1508078A2 (en) | Voltage regulator with dynamically boosted bias current | |
| CN112068630A (en) | Digital low dropout regulator with quick response | |
| US11822360B2 (en) | High-speed low-impedance boosting low-dropout regulator | |
| CN112860002B (en) | Instantaneous response linear voltage regulator | |
| US20160357205A1 (en) | Voltage compensation circuit including low dropout regulators and operation method thereof | |
| CN114510112A (en) | A Transient Enhancement Circuit for Low-Power Fully Integrated Low-Dropout Linear Regulators | |
| TW201833707A (en) | Voltage generator | |
| US20050088154A1 (en) | Voltage regulator | |
| CN118210349A (en) | Linear voltage stabilizer circuit, memory circuit and micro-processing chip | |
| CN111694394B (en) | Digital voltage stabilizing system and control method thereof | |
| CN114253331B (en) | Transient enhanced digital LDO circuit | |
| US7122996B1 (en) | Voltage regulator circuit | |
| CN119690184A (en) | Transient enhancement circuit, linear voltage regulator and transient enhancement method | |
| CN118838461A (en) | LDO circuit with dynamic compensation and transient enhancement and working method thereof | |
| CN109462332B (en) | Power supply system | |
| CN115913202B (en) | Quick power-on protection circuit for high-voltage circuit | |
| TW591367B (en) | Regulator and related method capable of performing pre-charging | |
| CN111835195B (en) | Self-adaptive power supply voltage regulating circuit | |
| CN110445362B (en) | A Transient Enhancement Circuit for Buck Converter | |
| CN106774588B (en) | A kind of low pressure difference linear voltage regulator using analog circuit compensating electric capacity |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |