Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The method embodiments provided in the embodiments of the present application may be executed in a server apparatus or similar computing device. Taking the example of running on a server device, fig. 1 is a block diagram of a hardware structure of a server device of a control method of a data transmission device according to an embodiment of the present application. As shown in fig. 1, the server apparatus may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU, a programmable logic device FPGA, or the like, and a memory 104 for storing data, wherein the server apparatus may further include a transmission apparatus 106 for communication functions and an input-output apparatus 108. It will be appreciated by those of ordinary skill in the art that the architecture shown in fig. 1 is merely illustrative and is not intended to limit the architecture of the server apparatus described above. For example, the server device may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a control method of a data transmission apparatus in an embodiment of the present application, and the processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above-described method. The memory 104 may include high speed random access memory, but may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory. In some examples, the memory 104 may further include memory remotely located with respect to the processor 102, which may be connected to the server device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station so as to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.
In this embodiment, a control method of a data transmission device is provided, which is applied to a controller of a data transmission system, where an initial data transmission system includes a target device and a reference device, the target device and the reference device are configured to allow data to be transmitted when a transition edge of a clock signal arrives, and the controller is connected to the target device and the reference device, respectively, and fig. 2 is a flowchart of a control method of the data transmission device according to an embodiment of the present application, as shown in fig. 2, where the flowchart includes the steps of:
step S202, detecting the current transmission delay information of an initial data transmission system, wherein the transmission delay information is used for indicating the delay condition when data is transmitted between target equipment and reference equipment;
Step S204, positioning a system adjustment position on an initial data transmission system according to the transmission delay information and detecting a system adjustment parameter to be adjusted at the system adjustment position, wherein the system adjustment position comprises at least one of target equipment, reference equipment and a transmission link between the target equipment and the reference equipment, and the system adjustment parameter is used for reducing the influence degree of the transmission delay information on data transmission between the target equipment and the reference equipment at the system adjustment position;
Step S206, the initial data transmission system is adjusted according to the system adjustment parameters at the system adjustment position to obtain the target data transmission system.
Through the steps, the controller of the data transmission system can detect the time delay condition when the data is transmitted between the current target equipment and the reference equipment of the initial data transmission system, a system adjustment position is positioned on the initial data transmission system according to the time delay condition, a system adjustment parameter to be adjusted on the system adjustment position is detected, and the initial data transmission system is adjusted on the system adjustment position according to the system adjustment parameter, so that the influence degree of the time delay condition on the data transmission between the target equipment and the reference equipment is reduced, the data transmission efficiency between the target equipment and the reference equipment is improved, the problem that the data transmission efficiency between the equipment is lower is solved, and the effect of improving the data transmission efficiency between the equipment is achieved.
Optionally, in the embodiment of the present application, the data transmission system may include, but is not limited to, a target device and a reference device that need to perform data transmission, where there is more demand, there may be other devices between the target device and the reference device, for example, where there is a level shift device between the target device and the reference device where the communication levels of the target device and the reference device are inconsistent.
Alternatively, in the embodiment of the present application, the target device may be, but is not limited to, a device capable of controlling the data transmission process, for example, a CPU, a BMC, a microcontroller, a digital signal processor, a field programmable gate array, a digital signal decoder, a memory controller, and the like.
Alternatively, in the embodiment of the present application, the reference device may be, but not limited to, a device supporting full duplex communication that may perform data transmission in response to control of the target device, for example, a storage device for storing data, such as FLASH or an electrically erasable programmable read-only memory.
Alternatively, in an embodiment of the present application, the transition edge includes a rising edge and a falling edge, and the target device may be, but is not limited to being configured to allow data to be transmitted on the rising edge of the clock signal, and the reference device is configured to allow data to be received on the falling edge of the clock signal, or the target device is configured to allow data to be transmitted on the falling edge of the clock signal, and the reference device is configured to allow data to be received on the rising edge of the clock signal. The arrangement of data transmission by the reference device and data reception by the target device is similar to the above.
Alternatively, in embodiments of the present application, the clock signal may be, but is not limited to being, generated by the target device and sent to the reference device.
In the embodiment provided in step S202, the transmission delay information may be, but is not limited to, a delay condition for indicating transmission of data between the target device and the reference device, including, but not limited to, a delay time for indicating whether there is a delay in transmission of data between the target device and the reference device, or a delay time for indicating transmission of data between the target device and the reference device, and so on.
Optionally, in the embodiment of the present application, detecting the current transmission delay information of the initial data transmission system includes, but is not limited to, determining the current transmission delay information of the transmission system by detecting a receiving condition of the data sent by the target device to the reference device, where the transmission delay information is used to indicate whether there is a delay when the data is transmitted between the target device and the reference device.
Optionally, in the embodiment of the present application, detecting the current transmission delay information of the initial data transmission system includes, but is not limited to, detecting, by an oscilloscope, a time difference between a transition edge of data sent by the reference device and received by the target device, and a transition edge of the clock signal, where the transmission delay information is used to indicate a degree of delay when the data is transmitted between the target device and the reference device.
In the embodiment provided in step S204, the system adjusts the location including, but not limited to, the target device, and/or the reference device, and/or the transmission link between the target device and the reference device. The system adjusts the position as the target equipment, namely, the data driving capability of the target equipment is adjusted to drive the transmitted clock signals and data more greatly, so that the signal error of the clock signals received by the reference equipment is reduced, the influence degree of time delay on data transmission between the target equipment and the reference equipment is reduced, or the original receiving time is delayed by adjusting the time when the target equipment collects the data transmitted by the reference equipment, the normal receiving of the data with the time delay condition is realized, and the influence degree of the time delay on the data transmission between the target equipment and the reference equipment can be reduced. The system adjusts the position to be the reference equipment, namely, the data driving capability of the reference equipment is adjusted to drive the transmitted data more, so that jump edge time errors between the data received by the target equipment and the original clock signal are reduced, and the influence degree of time delay on data transmission between the target equipment and the reference equipment is reduced. The system adjusts the position to be a transmission link, namely, reduces the generation of time delay by reducing the influence degree of the transmission link on the time delay of the clock signal and the transmitted data, thereby reducing the influence degree of the time delay on the data transmission between the target equipment and the reference equipment.
Optionally, in the embodiment of the present application, current transmission delay information of an initial data transmission system is detected, a system adjustment position is located on the initial data transmission system according to the transmission delay information, and a system adjustment parameter to be adjusted at the system adjustment position is detected, including but not limited to a first delay parameter for indicating that the reference device receives a time difference between a transition edge of data sent by the target device and a transition edge of a sent clock signal, and a second delay parameter for indicating that the target device receives a time difference between the transition edge of data sent by the reference device and the transition edge of the clock signal, and when the second delay parameter is detected to be greater than a delay threshold and the first delay parameter is less than the delay threshold, the target device is determined to be the system adjustment position and the system adjustment parameter is determined to be the first parameter, wherein the first parameter is used for indicating that the target device receives data after the clock signal reaches a target time length, and the target time length has a corresponding relation with the second delay parameter, and when the second delay parameter is detected to be greater than the delay threshold and the first delay parameter is greater than the delay threshold, the second delay parameter is determined to be the system adjustment position is determined to be the second parameter, and the system adjustment parameter is determined to be the target device is determined to be the system adjustment position, and the second parameter is determined to be the target device is determined to be the system adjustment position. According to the scheme, when the delay of the signal is not serious, namely, the delay of the signal only affects the target equipment to receive data and does not affect the reference equipment to receive data, the scheme of adjusting the data receiving time of the target equipment is adopted to reduce the influence of the delay on data transmission, the limitation of equipment performance and link performance is avoided, the method is easy to realize, when the delay of the signal is serious, namely, the delay of the signal affects the target equipment to receive data and the reference equipment to receive data, in order to reduce the action required to be executed for improving the data transmission efficiency, the method for improving the driving performance of the data and reducing the blocking influence of the link is adopted to directly reduce the delay degree, the problem that the target equipment cannot normally receive the data is solved, the problem that the reference equipment cannot normally receive the data is solved, different schemes are adopted in combination with the above mode, the operation can be reduced as much as possible, and the data transmission efficiency is improved effectively.
In the embodiment provided in step S206, the initial data transmission system is adjusted at the system adjustment location according to the system adjustment parameters, including but not limited to improving the data driving performance of the target device, and/or improving the data driving performance of the reference device, and/or adjusting the data reception timing of the target device, and/or improving the data blocking effect of the transmission link, etc.
Optionally, in the embodiment of the present application, fig. 3 is a schematic diagram of a data transmission system according to the embodiment of the present application, as shown in fig. 3, where a BMC/CPU (target device) is used as a master device side of an SPI bus, a FLASH (reference device) is used as a slave device side of the SPI bus, a communication level of the BMC/CPU is specified to be 1 V8, and a working level of the FLASH is 3V3, so that a level conversion IC needs to be added between the BMC/CPU and the FLASH, and the level conversion IC introduces a larger time delay, and in addition, due to complexity of a server, materials on a board are numerous, a distance from the CPU/BMC to the FLASH is excessively long, a longer PCB trace further aggravates a time delay of a signal, and due to a common PROT (Protocol Analysis ) in the server, branches of the SPI trace inevitably occur, and a star connection of the PCB trace often introduces a larger STUB (STUB, a protruding structure on a wire), which further increases a time delay of a signal. The time delay introduced by the above cases can greatly influence the SPI signal time sequence requirement, so that SPI communication is abnormal, and data transmission between the target equipment and the parameter equipment is further influenced. More specifically, as shown in fig. 3, the CPU accesses the BIOS FLASH via a 2-stage MUX (multiplexer), and the channels are l,4,5. The BMC is used here to upgrade the BIOS FLASH, and the channels are 2,3,4,5. The PROT is used for monitoring the existence of SPI buses of the CPU and the BMC accessing the BIOS FLASH, and also has the function of accessing the BIOS FLASH, wherein 7 of a channel is monitored, and 6 and 5 of channels are accessed to the BIOS FLASH. The level conversion device is arranged between the channels 2 and 3, and the level conversion at two ends of the device is required because the working levels of the BMC and the BIOS FLASH are not consistent. In practical applications, it was found that when PROT is in place (PROT is a separate PCB (Printed Circuit Board, printed circuit board) board, removable), and the SPI bus works at 50Mhz, the BMC always makes errors when upgrading the BIOS FLASH, as shown in the following code:
00000:/home/taobao#bios-update.sh/tmp
BIOS image is/tmp/bios.bin
BIOS upgrade started at Thu Aug 8 06:33:07 UTC 2024
Check host server power state first
Host server powered off
PROT device is not available
switch BIOS flash to bmc
Bind spi-nor driver
/usr/bin/bios-update.sh:line 217:echo:write error:No such device
Unbind spi-nor driver
/usr/bin/bios-update.sh:line l 94:echo:write error:No such device
PORT device is not available
switch BIOS flash to host
Fig. 4 is a schematic diagram of a signal transmitted by a data transmission system according to an embodiment of the present application, as shown in fig. 4, after actual test analysis, the root cause of failure in upgrading FLASH is SPI timing abnormality caused by objective factors, the effective rising edge or falling edge is delayed by about 8ns after passing through the level conversion device, and the effective collecting time of the 50Mhz SPI bus is only 10ns, in addition, due to guidance of objective factors such as PROT, the timing requirement of the SPI bus is further deteriorated, and finally the SPI bus is abnormal. At this time, if the upgrading of the BMC to the FLASH is to be continuously completed, the influence degree of the time delay on the data transmission between the target device and the reference device must be reduced, and the method of steps S202 to S206 may be adopted to obtain the target data transmission system, and the upgrading of the BMC to the FLASH is completed in the target data transmission system.
As an optional implementation manner, detecting the current transmission delay information of the initial data transmission system comprises detecting a target receiving parameter of a target device in the initial data transmission system, wherein the target receiving parameter is used for indicating whether the target device can normally receive data when a jump edge arrives, and the transmission delay information comprises the target receiving parameter.
Through the steps, whether the target device can normally receive data when the jump edge arrives is detected, whether the data transmission edge exists between the target device and the reference device in the initial data transmission system can be indirectly judged without intervention of other devices, and a basis is provided for improving the influence degree of time delay in the data transmission system on data transmission.
In an alternative implementation manner, the method for positioning the system adjustment position on the initial data transmission system according to the transmission delay information and detecting the system adjustment parameter to be adjusted on the system adjustment position comprises the steps of determining the system adjustment position as a transmission link and determining the link adjustment parameter as the system adjustment parameter under the condition that the target receiving parameter is detected to be used for indicating that the target device cannot normally receive data when the jump edge arrives, wherein the link adjustment parameter is used for reducing the link serial resistance of the transmission link.
Optionally, in the embodiment of the present application, the blocking effect of the transmission link on the transmitted data is reduced by reducing the link string resistance of the transmission link, so as to reduce the rising and falling time of the level signal and the clock signal corresponding to the transmitted data, and reduce the time delay.
Optionally, in the embodiment of the present application, in the data transmission system shown in fig. 3, a more specific method for reducing the influence degree of the time delay on the data transmission between the target device and the reference device by adopting the method of steps S202 to S206 may be to adjust the serial resistance from the common 33R or 22R to 0R in the first mode of adjusting the serial resistance from the master device end to the slave device end of the SPI bus, so as to reduce the rising and falling time of the signal level of the SPI bus. Fig. 5 is a schematic diagram of signals transmitted by the data transmission system according to an embodiment of the present application, and as shown in fig. 5, after the series resistance is modified, the delay time of the actual signal is adjusted from 8ns to 3ns. By adjusting the serial resistance of the SPI, the rising and falling edge time of the SPI bus is adjusted, and the phase change adjustment solves the problem of SPI time delay.
Through the steps, the method for optimizing the initial data transmission system by reducing the link series resistance of the transmission link is provided, the data transmission delay condition in the data transmission system is optimized by shortening the rising time and the falling time, and the data transmission efficiency in the data transmission system is improved.
In an alternative implementation manner, the system adjustment position is positioned on the initial data transmission system according to the transmission delay information, and the system adjustment parameter to be adjusted on the system adjustment position is detected, wherein the method comprises the steps of determining the system adjustment position as the target device and/or the reference device and determining the target adjustment parameter as the system adjustment parameter under the condition that the target receiving parameter is detected to be used for indicating that the target device cannot normally receive data when the jump edge arrives, and the target adjustment parameter is used for improving the driving performance of the target device and/or the reference device for sending data.
Optionally, in the embodiment of the present application, the time delay is reduced by reducing the rise and fall time of the level signal corresponding to the data transmitted by the target device by improving the driving performance of the data transmitted by the target device, and/or the time delay is reduced by reducing the rise and fall time of the level signal corresponding to the data transmitted by the reference device by improving the driving performance of the data transmitted by the reference device.
Optionally, in the embodiment of the present application, in the data transmission system shown in fig. 3, a more specific method for reducing the influence degree of the time delay on the data transmission between the target device and the reference device by adopting the method of steps S202 to S206 may be to adjust the time delay of the SPI by adjusting the rising edge and falling edge time of the phase-change adjustment SPI bus in the second mode of adjusting the SPI bus driving capability of the BMC/CPU/FLASH. Taking BIOS FLASH as an example, fig. 6 is a reference diagram of setting driving capability of an SPI bus according to an embodiment of the present application, as shown in fig. 6, the driving capability of the SPI bus is divided into 4 gears, and is 1 8ohm,25ohm,35ohm,50ohm from high to low. The lower the resistance, the stronger the driving capability. And adjusting the driving capability of the FLASH through the jig of the FLASH. Fig. 7 is a schematic diagram three of signals transmitted by the data transmission system according to an embodiment of the present application, fig. 8 is a schematic diagram four of signals transmitted by the data transmission system according to an embodiment of the present application, as shown in fig. 7 and 8, fig. 7 shows a waveform diagram before tuning operation is adopted, and fig. 8 shows a waveform diagram after tuning operation is adopted, it can be seen that rising edges and falling edges of MISO signals of FLASH (i.e., signals sent to BMC by FLASH) are significantly improved from 7ns to about 3ns before tuning and after tuning.
Through the steps, the method for improving the driving performance of the target equipment and/or the reference equipment for sending the data to regulate and optimize the initial data transmission system is provided, and the data transmission delay condition in the data transmission system is regulated and optimized by shortening the rising time and the falling time of the level signal corresponding to the transmitted data, so that the data transmission efficiency in the data transmission system is improved.
The method comprises the steps of controlling target equipment and reference equipment to conduct transmission testing according to a plurality of reference transmission settings to obtain a plurality of transmission test results, wherein each reference transmission setting is used for indicating the target equipment to send data when a jump edge arrives and receive the data after the jump edge arrives reference time, the transmission testing is used for testing the data receiving capacity of the target equipment under the plurality of reference transmission settings, and screening out target transmission settings with the data receiving capacity meeting transmission requirements from the plurality of reference transmission settings according to the plurality of transmission test results, wherein the transmission time delay information comprises the target transmission settings.
Optionally, in the embodiment of the present application, the delay condition of the electric v signal corresponding to the data received by the target device is determined by, but not limited to, a pre-test method, so as to delay the receiving opportunity of the data received by the target device, thereby reducing the influence degree of the transmission delay on the data transmission between the target device and the reference device without changing the delay, and improving the data transmission efficiency between the devices.
Through the steps, the target transmission setting that the data receiving capacity of the corresponding target equipment meets the transmission requirement is screened out by a method for carrying out transmission test on a plurality of reference transmission settings, so that the target equipment delays the data receiving in the process of carrying out data transmission between the actual target equipment and the reference equipment, the influence of the time delay brought by the transmission process of a data signal and a clock signal on the data receiving is reduced, and the data transmission efficiency is improved.
As an optional implementation manner, the control target device and the reference device perform transmission test according to a plurality of reference transmission settings to obtain a plurality of transmission test results, and the control target device comprises traversing the plurality of reference transmission settings, configuring the traversed reference transmission settings to the target device, sending first test data to the reference device when a jump edge arrives according to the configured reference transmission settings, sending second test data to the target device when the jump edge arrives, wherein the second test data are the first test data received by the reference device, receiving the second test data after the jump edge arrives according to the configured reference transmission settings to obtain third test data, and comparing the similarity degree of the first test data and the third test data to obtain the transmission test results.
Optionally, in the embodiment of the present application, because the clock signal and the data signal received by the reference device side are both affected by the transmission link, the delay difference between the clock signal and the data signal is not very large, so in general, the similarity between the first test data and the second test data is very high, while on the target device side, the reference device sends the data according to the indication of the clock signal after the delay is generated, the timing of sending the data itself generates a certain delay, and the data signal transmitted by the reference device is affected by the transmission link, on the target device side, the data signal received by the target device side is further delayed, in this case, the target device receives the data according to the indication of the accurate clock signal without delay, so that the situation that the data cannot be normally received easily occurs, that is, the similarity between the first test data and the third test data is more easily affected by the delay, so the transmission test result is determined by determining the similarity between the first test data and the third test data.
In an alternative implementation, the method for positioning the system adjustment position on the initial data transmission system according to the transmission delay information and detecting the system adjustment parameter to be adjusted on the system adjustment position comprises the steps of determining the system adjustment position as a target device and determining the system adjustment parameter as a data transmission setting of the target device under the condition that the transmission delay information is a target transmission setting, wherein the data transmission setting is used for indicating the time for transmitting data and receiving data by the target device.
Optionally, in the embodiment of the present application, in the data transmission system shown in fig. 3, the delay of the SPI bus is adjusted by adopting the two modes, but because the parameter setting of each FLASH is different, even including the driving capability of each BMC/CPU, the two modes need to be adjusted for the actual SPI topology and the actual application. Thus, although the SPI signal can be adjusted, the workload is increased, and uniform adjustment cannot be performed for each SPI signal. The method provides more modes for the delay of the SPI bus, namely, the method three is that the time delay judgment is added at the BMC/CPU end, and the SPI bus time sequence is regulated from the inside of the BMC/CPU by leading in SPI drive. Fig. 9 is a reference diagram for setting a delay judgment register of a BMC according to an embodiment of the present application. As shown in fig. 9, the delay judgment register of the SPI bus of the BMC is configured to receive the high-low level value of the SPI signal from the FLASH, and the BMC defaults to falling edge sampling. As shown in fig. 9, the 8-bit register may be set to adjust the time for the BMC to collect the SPI bus data on the falling edge, which is equivalent to the time specified by the BMC delay, and then determine the value of the level, so that the influence of the SPI delay time on the timing sequence of the SPI bus may be adjusted from within the BMC. Wherein, HCLK is 200Mhz, coarse tuning is to tune delay time of 5,1 ns by taking single HCLK as a unit, or fine tuning is to tune DI parameter, and delay time judgment time is tuned by taking 0.5ns as a unit.
However, the BMC cannot set the parameter every time the BMC is powered on, and the delay of each SPI bus is inconsistent due to different parameters including the level conversion factor in the circuit according to the actual PCB trace, so that the BMC selects an optimal delay judgment value by performing traversal access to the FLASH device of the SPI bus when the BMC is powered on, and works after importing.
The specific implementation process comprises the following steps:
Step S1, firstly judging that the value of the initial space 0-0x4FF is not all zero in the FLASH device space of the BMC downlink, and confirming the value when FLASH is selected.
In step S2, the BMC initializes SPI driving, and the default delay judgment value is 0 (the default does not need to introduce delay judgment).
And S3, the SPI bus of the BMC carries out repeated read-write access aiming at the 0-0x4FF space of the FLASH. Specifically, the b2 system values of n 10101010 in the 0-0x4FF space are written first, then the BMC reads back the values in the 0-0x4FF space through the SPI bus, whether the written values are consistent with the read values is judged, and if the written values are consistent with the read values, no abnormality exists by default.
And S4, the BMC sets the value of the delay judgment register, and each delay value is executed from the smallest 0 (no delay) to the largest set delay, so that the judgment on which delay interval can meet the normal SPI working requirement is performed.
And S5, if the BMC can work normally in all the options of the delay register, the BMC sets the intermediate delay value to be the optimal value.
And S6, if the operation is normal in a certain section of interval, and if the operation is not normal in another section of interval, selecting an intermediate delay value as an optimal value by taking one end of the normal operation interval as a base point.
Because the actual PCB wiring of the SPI comprises a possible STUB including MUX or LEVEL SHIF level conversion devices, the SPI signals from the main equipment to the auxiliary equipment or from the auxiliary equipment to the main equipment of the SPI have delay, and the delay is difficult to avoid, the influence of the delay on the SPI bus time sequence can be reduced as much as possible through the first mode and the second mode, and the normal operation of the SPI is further ensured. After the third mode is imported, delay judgment time is set in the BMC, so that the judgment time for the BMC to collect the high and low effective levels of SPI signals from FLASH can be delayed, the delayed time counteracts the delay interference caused by the actual physical factors such as PCB wiring and STUB, the delay can be completely avoided, and SPI time sequence can be optimized. And the normal work of the SPI bus is ensured.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method of the various embodiments of the present application.
In this embodiment, a control device of a data transmission device is further provided, which is applied to a controller of a data transmission system, where an initial data transmission system includes a target device and a reference device, where the target device and the reference device are configured to allow data to be transmitted when a transition edge of a clock signal arrives, and the controller is connected to the target device and the reference device, respectively. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
Fig. 10 is a block diagram of a control apparatus of a data transmission device according to an embodiment of the present application, as shown in fig. 10, including:
the detection module 1 002 is configured to detect current transmission delay information of the initial data transmission system, where the transmission delay information is used to indicate a delay condition when data is transmitted between the target device and the reference device;
The positioning module 1004 is configured to position a system adjustment position on an initial data transmission system according to transmission delay information, and detect a system adjustment parameter to be adjusted at the system adjustment position, where the system adjustment position includes at least one of a target device, a reference device, and a transmission link between the target device and the reference device, and the system adjustment parameter is configured to reduce, at the system adjustment position, a degree of influence of the transmission delay information on data transmission between the target device and the reference device;
the adjustment module 1 006 is configured to adjust the initial data transmission system at a system adjustment position according to the system adjustment parameter, so as to obtain a target data transmission system.
Through the steps, the controller of the data transmission system can detect the time delay condition when the data is transmitted between the current target equipment and the reference equipment of the initial data transmission system, a system adjustment position is positioned on the initial data transmission system according to the time delay condition, a system adjustment parameter to be adjusted on the system adjustment position is detected, and the initial data transmission system is adjusted on the system adjustment position according to the system adjustment parameter, so that the influence degree of the time delay condition on the data transmission between the target equipment and the reference equipment is reduced, the data transmission efficiency between the target equipment and the reference equipment is improved, the problem that the data transmission efficiency between the equipment is lower is solved, and the effect of improving the data transmission efficiency between the equipment is achieved.
The detection module comprises a test unit and a screening unit, wherein the test unit is used for controlling target equipment and reference equipment to carry out transmission tests according to a plurality of reference transmission settings to obtain a plurality of transmission test results, each reference transmission setting is used for indicating the target equipment to send data when a jump edge arrives and receive the data after the jump edge arrives for a reference time length, the transmission test is used for testing the data receiving capability of the target equipment under the plurality of reference transmission settings, and the screening unit is used for screening out target transmission settings with the data receiving capability meeting transmission requirements from the plurality of reference transmission settings according to the plurality of transmission test results, and the transmission delay information comprises the target transmission settings.
The test unit is further used for traversing a plurality of reference transmission settings, configuring the traversed reference transmission settings to target equipment, controlling the target equipment to send first test data to the reference equipment when a jump edge arrives according to the configured reference transmission settings, controlling the reference equipment to send second test data to the target equipment when the jump edge arrives, wherein the second test data are the first test data received by the reference equipment, controlling the target equipment to receive the second test data after the jump edge arrives according to the configured reference transmission settings, obtaining third test data, and comparing the similarity degree of the first test data and the third test data to obtain a transmission test result.
As an optional implementation manner, the positioning module comprises a first determining unit, a second determining unit and a third determining unit, wherein the first determining unit is used for determining a system adjustment position as a target device and determining a system adjustment parameter as a data transmission setting of the target device when the transmission delay information is the target transmission setting, and the data transmission setting is used for indicating the time for transmitting data and receiving data of the target device.
As an optional implementation manner, the detection module comprises a detection unit, a first detection unit and a second detection unit, wherein the detection unit is used for detecting target receiving parameters of target equipment in an initial data transmission system, the target receiving parameters are used for indicating whether the target equipment can normally receive data when a jump edge arrives, and the transmission delay information comprises the target receiving parameters.
The positioning module comprises a second determining unit, a first determining unit and a second determining unit, wherein the second determining unit is used for determining the system adjustment position as the target device and/or the reference device and determining the target adjustment parameter as the system adjustment parameter under the condition that the target receiving parameter is detected to be used for indicating that the target device cannot normally receive data when the jump edge arrives, and the target adjustment parameter is used for improving the driving performance of the target device and/or the reference device for sending data.
The positioning module comprises a third determining unit, a second determining unit and a third determining unit, wherein the third determining unit is used for determining the system adjustment position as a transmission link and determining the link adjustment parameter as the system adjustment parameter under the condition that the target receiving parameter is detected to be used for indicating that the target device cannot normally receive data when the jump edge arrives, and the link adjustment parameter is used for reducing the link serial resistance of the transmission link.
It should be noted that each of the above modules may be implemented by software or hardware, and the latter may be implemented by, but not limited to, the above modules all being located in the same processor, or each of the above modules being located in different processors in any combination.
Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
In an exemplary embodiment, the computer readable storage medium may include, but is not limited to, a U disk, a Read-Only Memory (ROM), a random access Memory (Random AccessMemory, RAM), a removable hard disk, a magnetic disk, or an optical disk, etc. various media in which a computer program may be stored.
An embodiment of the application also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.
Embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.
Embodiments of the present application also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.
Embodiments of the present application also provide a computer program comprising computer instructions stored on a computer readable storage medium, a processor of a computer device reading the computer instructions from the computer readable storage medium, the processor executing the computer instructions to cause the computer device to perform the steps of any of the method embodiments described above.
Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.
It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.