CN119730236A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN119730236A CN119730236A CN202311272632.9A CN202311272632A CN119730236A CN 119730236 A CN119730236 A CN 119730236A CN 202311272632 A CN202311272632 A CN 202311272632A CN 119730236 A CN119730236 A CN 119730236A
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
本公开实施例公开了一种半导体结构及其形成方法。其中，半导体结构包括：基底和m条字线。基底，包括分立的多个有源区柱；多个有源区柱，位于基底的正面，且均沿竖直方向延伸；多个有源区柱，沿第一方向和第二方向排布，构成m行n列的阵列。m条字线，沿第一方向延伸，且沿第二方向排布；其中，第2i‑1条和第2i条字线，位于第2i‑1行和第2i行有源区柱之间的第一沟槽，且分别覆盖对应的有源区柱的侧壁；第2i‑1条和第2i条字线之间具有空气隙。
The disclosed embodiment discloses a semiconductor structure and a method for forming the same. The semiconductor structure includes a substrate and m word lines. The substrate includes a plurality of discrete active area columns; the plurality of active area columns are located on the front side of the substrate and extend in a vertical direction; the plurality of active area columns are arranged in a first direction and a second direction to form an array of m rows and n columns. The m word lines extend in a first direction and are arranged in a second direction; the 2i-1st and 2i-th word lines are located in a first groove between the 2i-1st and 2i-th active area columns and cover the side walls of the corresponding active area columns respectively; there is an air gap between the 2i-1st and 2i-th word lines.
Description
Technical Field
The present disclosure relates to, but is not limited to, a semiconductor structure and a method of forming the same.
Background
The 3D stacking technique is to form three-dimensional integration in the vertical direction using stacking techniques or by interconnect and other micro-fabrication techniques. The 3D stacking technology can be used for packaging more than two chips with different functions in the original packaging body, so that the functional diversity of the chips is realized. In the related art, there is still room for further optimization of the structure of chips for stacking.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which can improve the integration level and the electrical performance.
The technical scheme of the embodiment of the disclosure is realized as follows:
The embodiment of the disclosure provides a semiconductor structure, which comprises a substrate, a plurality of active area pillars, an array of m rows and n columns, an m word line, a 2i-1 th word line and a 2 i-th word line, wherein the plurality of active area pillars are arranged on the front surface of the substrate and extend along the vertical direction, the plurality of active area pillars are arranged along the first direction and the second direction to form the array of m rows and n columns, m and n are both larger than 1, the first direction and the second direction intersect and are respectively perpendicular to the vertical direction, the m word line extends along the first direction and is arranged along the second direction, the 2i-1 th word line and the 2 i-th word line are located in a first groove between the 2i-1 th row and the 2 i-th row and are respectively covered on the side wall of the corresponding active area pillars, and an air gap is reserved between the 2i-1 th word line and the 2 i-th word line, and i is larger than or equal to 1 and smaller than m/2.
In the scheme, the semiconductor structure further comprises a plurality of isolation structures which extend along the first direction and are sequentially arranged along the second direction, a plurality of second grooves are formed between the 2 i-th row and the 2i+1-th row of the active region columns, and the depth of the second grooves is larger than that of the first grooves.
In the scheme, the semiconductor structure further comprises a grid oxide layer formed between each word line and the corresponding side wall of the active region column.
In the scheme, the semiconductor structure further comprises a plurality of node contact structures, wherein each node contact structure is positioned at the top end of a corresponding active area column, and a plurality of bit line contact structures, and the bottom ends of every two active area columns are connected with a corresponding bit line contact structure.
In the scheme, the semiconductor structure further comprises n bit lines extending along the second direction and located on the back surface of the substrate, and each bit line is electrically connected with the bottom ends of a corresponding row of active region columns through the bit line contact structure.
In the scheme, the semiconductor structure further comprises a plurality of capacitors, and each capacitor is electrically connected with the top end of a corresponding active area column through one node contact structure.
In the scheme, the included angle between the first direction and the second direction is 60 degrees, and the capacitors are distributed in a honeycomb shape.
In the scheme, the semiconductor structure further comprises a dielectric layer which covers the top ends of the active region pillars and surrounds the side walls of the node contact structures.
In the scheme, the semiconductor structure further comprises a bonding pad structure which is positioned on the back surface of the substrate and is electrically connected with the corresponding bit line.
The embodiment of the disclosure also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a plurality of initial active region columns extending along the vertical direction on the front surface of the substrate, forming a plurality of m/2 rows and n columns of arrays along the first direction and the second direction on the initial active region columns, forming shallow trench isolation structures between adjacent initial active region columns, wherein m and n are both larger than 1, the first direction and the second direction are respectively perpendicular to the vertical direction, etching the shallow trench isolation structures, forming first trenches extending along the first direction between two adjacent rows of initial active region columns, covering the side walls of the initial active region columns by the rest of shallow trench isolation structures, forming a gate oxide layer, forming m word lines extending along the first direction, forming corresponding first trenches in the first trenches and respectively covering the corresponding first trenches, forming a second i-1 row and a second i word line, and forming a dielectric layer between the first active region and the second active region columns, and forming a first channel between the first active region columns and the second active region columns, and forming a second channel layer between the first channel and the second channel and the first channel 1 row and the second channel and the first channel and the second channel.
In the scheme, after the dielectric layer is deposited to cover the tops of the active area columns, a patterned mask is formed on the dielectric layer, the dielectric layer is etched according to the mask, a plurality of through holes are formed in the dielectric layer, each through hole exposes the top end of a corresponding active area column, a plurality of node contact structures are deposited in the plurality of through holes, each node contact structure is connected with the top end of a corresponding active area column, a plurality of capacitors are formed, and each capacitor is electrically connected with the top end of a corresponding active area column through one node contact structure.
In the scheme, after the capacitors are formed, the method further comprises the steps of thinning the back surface of the substrate, forming a plurality of bit line contact structures at the bottom ends of the active region columns, connecting the bottom ends of every two active region columns with a corresponding bit line contact structure, filling metal materials into the back surface of the substrate to form n bit lines, and electrically connecting the bottom ends of a corresponding column of active region columns through the bit line contact structures.
In the scheme, after the n bit lines and the plurality of bit line contact structures are formed, the method further comprises forming a pad structure on the back surface of the substrate, wherein the pad structure is electrically connected with the corresponding bit line.
In the scheme, the formation of m word lines extending along the first direction comprises filling word line conductive materials in the first grooves, and etching the word line conductive materials in each first groove to cut the word line conductive materials into two parts so as to form two word lines.
In the scheme, after the second groove is etched and formed, the method further comprises the step of depositing dielectric materials in the second groove to form an isolation structure extending along the first direction.
It can be seen that the disclosed embodiments provide a semiconductor structure and a method of forming the same. The semiconductor structure comprises a substrate and m word lines. The device comprises a substrate, a plurality of active area columns and a plurality of active area columns, wherein the plurality of active area columns are separated, are positioned on the front surface of the substrate and extend along the vertical direction, are distributed along the first direction and the second direction to form an array of m rows and n columns, m and n are larger than 1, and the first direction and the second direction intersect and are respectively perpendicular to the vertical direction. m word lines extending in a first direction and arranged in a second direction; the 2i-1 th and 2i th word lines are positioned in the first groove between the 2i-1 st row and the 2i nd row active area columns and respectively cover the side walls of the corresponding active area columns; an air gap is arranged between the 2i-1 th word line and the 2i th word line, wherein i is larger than or equal to 1 and smaller than m/2. It will be appreciated that the embodiments of the present disclosure provide active area pillars arranged in an array, and further, the 2i-1 th and 2 i-th word lines are disposed in the first trench between the 2i-1 st row and the 2 i-th row of active area pillars, and an air gap is disposed between the 2i-1 st and 2 i-th word lines 20. In this way, the 2i-1 th and 2 i-th word lines with smaller spacing are electrically isolated by using the air gap with better insulativity and lower dielectric constant, and meanwhile, the spacing between the 2 i-th and 2i+1-th word lines is increased, so that the parasitic capacitance C wl between every two adjacent word lines is kept in a smaller range. That is, the embodiments of the present disclosure do not need to increase the space between adjacent active region pillars, so that the overall occupied area of the semiconductor structure is smaller, and at the same time, it is ensured that the parasitic capacitance C wl between adjacent word lines is kept in a smaller range. Namely, the embodiment of the disclosure provides a semiconductor structure with higher integration level and better electrical performance.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram III of a semiconductor structure according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 5 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 7 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the disclosure;
fig. 8 is a second flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the disclosure;
Fig. 9 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the disclosure;
fig. 10A is a schematic structural view of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 10B is a schematic structural diagram of a second method for forming a semiconductor structure according to an embodiment of the disclosure;
fig. 11A is a schematic structural view III of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 11B is a schematic structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
Fig. 12A is a schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 12B is a schematic structural view of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
Fig. 13A is a schematic structural diagram seven of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
Fig. 13B is a schematic structural view eight of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
Fig. 14A is a schematic structural diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 14B is a schematic structural view of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 15 is a schematic diagram eleven of a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.
When a layer/element is referred to herein as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, in one orientation, one layer/element is located "on" another layer/element, which may be located "under" the other layer/element when the orientation is reversed.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
Fig. 1 and 2 are schematic structural views of an alternative semiconductor structure provided in an embodiment of the present disclosure, wherein fig. 1 is a top view, and fig. 2 is a cross-sectional view taken along a line of sight A-A1 in fig. 1.
As shown in fig. 1 and 2, the semiconductor structure includes a substrate 00 and m word lines 20. The substrate 00 includes a discrete plurality of active area pillars 10. A plurality of active area pillars 10 are located on the front side of the substrate 00 and each extend in the vertical direction Z. The plurality of active region pillars 10 are arranged in the first direction X and the second direction Y to form an array of m rows and n columns. Wherein m and n are both greater than 1, and the first direction X and the second direction Y intersect and are respectively perpendicular to the vertical direction Z.
The m word lines 20 extend in the first direction X and are arranged in the second direction Y. The 2i-1 th and 2 i-th word lines 20 are located in the first trenches between the 2i-1 st row and the 2 i-th row of active area pillars 10, and cover the sidewalls of the corresponding active area pillars 10, respectively. An air gap 30 is provided between the 2i-1 th and 2 i-th word lines 20. Wherein i is greater than or equal to 1 and less than m/2.
In the disclosed embodiment, referring to fig. 1 and 2, the substrate 00 is composed of a semiconductor material, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The substrate 00 includes a plurality of discrete active area pillars 10, each of which active area pillars 10 can correspond to a transistor, such that the plurality of active area pillars 10 arranged in an array can form an array of transistors.
In the disclosed embodiment, with continued reference to fig. 1 and 2, the 2i-1 and 2i word lines 20 are located in the first trenches between the 2i-1 and 2i rows of active area pillars 10 and cover the sidewalls of the corresponding active area pillars 10, respectively. That is, every second word line 20 is located in the first trench between the corresponding two rows of active area pillars 10, where each row of active area pillars 10 is aligned in the first direction X. In the meantime, each word line 20 covers the sidewalls of a corresponding row of the active area pillars 10, so that the portion of the active area pillars 10 covered by the word line 20 may form a channel of a transistor, and a voltage on the word line 20 may control on or off of the channel.
Further, with continued reference to fig. 1 and 2, the m word lines 20 are arranged along the second direction Y, and the spacing between two adjacent word lines 20 is different. In one aspect, the spacing between the 2i and 2i+1 th word lines 20 (i.e., two adjacent word lines 20 located in different first trenches) is larger, and thus, the parasitic capacitance C wl between the 2i and 2i+1 th word lines 20 is correspondingly smaller. On the other hand, if the pitch between the 2i-1 th and 2 i-th word lines 20 (i.e., the adjacent two word lines 20 located in the same first trench) is small, an air gap 30 is provided between the 2i-1 th and 2 i-th word lines 20. The air gap 30 has better insulation and lower dielectric constant than a general dielectric, so that the parasitic capacitance C wl between the 2i-1 th and 2 i-th word lines 20 can be kept in a small range as well.
It will be appreciated that the presently disclosed embodiments provide a novel semiconductor structure having an array of active area pillars 10 arranged such that the 2i-1 and 2 i-th word lines 20 are disposed in the first trench between the 2i-1 and 2 i-th rows of active area pillars 10, and an air gap 30 is disposed between the 2i-1 and 2 i-th word lines 20. In this way, the 2i-1 th and 2 i-th word lines 20 with smaller pitches are electrically isolated by the air gap 30 with better insulation and lower dielectric constant, and at the same time, the pitches between the 2 i-th and 2i+1-th word lines 20 are pulled up, so that the parasitic capacitance C wl between every two adjacent word lines is kept in a small range.
That is, the embodiments of the present disclosure do not need to increase the space between adjacent active region pillars 10, so that the overall occupied area of the semiconductor structure is smaller, while ensuring that the parasitic capacitance C wl between adjacent word lines is kept in a smaller range. Namely, the embodiment of the disclosure provides a semiconductor structure with higher integration level and better electrical performance.
In some embodiments of the present disclosure, referring to fig. 1 and 2, the semiconductor structure further includes a plurality of isolation structures 40. The plurality of isolation structures 40 extend along the first direction X and are sequentially disposed along the second direction Y. A plurality of isolation structures 40 are located in the second trench between row 2i and 2i+1 active area pillars 10. The depth of the second trench is greater than the depth of the first trench.
In the disclosed embodiment, with continued reference to fig. 1 and 2, the air gap 30 is located in the first trench between row 2i-1 and row 2i active area pillars 10, i.e., the air gap 30 is located between row 2i-1 and row 2i word lines 20, and the isolation structure 40 is located in the second trench between row 2i and row 2i+1 active area pillars 10, i.e., the isolation structure 40 is located between row 2i and row 2i+1 word lines 20.
It will be appreciated that the air gaps 30 and the isolation structures 40 are spaced apart in the second direction Y, wherein between the word lines 20 having a smaller pitch (i.e., between the 2i-1 th and 2i th word lines 20), the air gaps 30 having a better insulation and a lower dielectric constant are used, and between the word lines 20 having a larger pitch (i.e., between the 2i-1 th and 2i+1 th word lines 20), the isolation structures 40 are used, thereby ensuring that the parasitic capacitance C wl between the word lines 20 is kept within a smaller range.
Meanwhile, compared with the air gap 30, the isolation structure 40 has stronger stability and can play a good supporting role on the whole semiconductor structure, so that the air gap 30 and the isolation structure 40 which are arranged at intervals can also consider the stability of the whole semiconductor structure and avoid collapse or structural damage.
In the disclosed embodiment, with continued reference to fig. 1 and 2, the second trench in which the isolation structure 40 is located has a depth that is greater than the depth of the first trench in which the air gap 30 is located. In this way, the isolation structure 40 is able to better isolate the different rows of active area pillars 10 from shorting and cross-talk.
In some embodiments of the present disclosure, referring to fig. 2, the semiconductor structure further includes a gate oxide layer 11. A gate oxide layer 11 is formed between each word line 20 and the sidewalls of the corresponding active region pillar 10. In this way, the voltage on the word line 20 can be used as the gate voltage of the transistor to control the turning on or off of the channel in the active area column 10.
It can be understood that the word line 20 covers the sidewall of the active region pillar 10 to control the on or off of the channel, so that the contact area between the word line 20 and the channel is larger, thereby increasing the control force on the channel and enabling the on or off of the channel to be more thorough, further increasing the on current I on of the transistor and reducing the off current I off of the transistor, thereby reducing the power consumption.
Fig. 3 is a schematic structural view of an alternative semiconductor structure provided in an embodiment of the disclosure, and fig. 3 is a cross-sectional view.
In some embodiments of the present disclosure, referring to fig. 3, the semiconductor structure further includes a plurality of Node Contacts (NC) 12 and a plurality of Bit Line Contacts (BLC) 13. Wherein each node contact structure 12 is located at the top end of a corresponding one of the active region pillars 10, and the bottom ends of every two active region pillars 10 are connected to a corresponding one of the bit line contact structures 13.
It will be appreciated that, on the one hand, the plurality of node contact structures 12 and the plurality of bit line contact structures 13 are disposed at the top and bottom ends (i.e., the front and back sides of the substrate) of the active region pillar 10, respectively, so that there is enough space to dispose the node contact structures 12 and the bit line contact structures 13, and the node contact structures 12 and the bit line contact structures 13 can be designed to be larger in size, thereby reducing the resistance of the node contact structures 12 and the bit line contact structures 13, and thus, the power consumption of the entire semiconductor structure. On the other hand, since the node contact structure 12 and the bit line contact structure 13 are respectively disposed at both ends of the active region pillar 10, the node contact structure 12 and the bit line contact structure 13 can be processed from both ends, respectively, without interfering with each other during the manufacturing process, thereby simplifying the manufacturing process.
In the disclosed embodiment, with continued reference to fig. 3, the bottom ends of each two active area pillars 10 are connected to a corresponding one of the bit line contact structures 13. Compared with each active region pillar corresponding to one bit line contact structure, the size of each bit line contact structure 13 can be made larger in the embodiment of the disclosure, so that on one hand, the resistance of the bit line contact structure 13 is lower, and on the other hand, the contact surface between the bit line contact structure 13 and the bit line is larger, thereby reducing the power consumption of the whole semiconductor structure.
Fig. 4 and 5 are schematic structural views of an alternative semiconductor structure provided in an embodiment of the present disclosure, wherein fig. 4 is a top view and fig. 5 is a cross-sectional view taken along a line of sight A-A1 in fig. 4. It should be noted that, in fig. 4, the middle portion of each bit line 50 is blocked and not shown due to the blocking relationship.
In some embodiments of the present disclosure, referring to fig. 4 and 5, the semiconductor structure further includes n bit lines 50.n bit lines 50 extending in the second direction Y are located on the back of the substrate. Each bit line 50 is electrically connected to the bottom ends of a corresponding column of active area pillars 10 through bit line contact structures 13.
It will be appreciated that the bit lines 50 are provided on the back side of the substrate, so that the bit lines can be cut off from the back side during the manufacturing process, array boundaries (array boundaries) are not required, and the size of each cell can be designed to be smaller, thereby improving the integration level, and on the other hand, the arrangement of each region is easier in the chip design, and the design difficulty is reduced.
Fig. 6 is a schematic structural view of an alternative semiconductor structure provided in an embodiment of the disclosure, and fig. 6 is a cross-sectional view.
In some embodiments of the present disclosure, referring to fig. 6, the semiconductor structure further includes a plurality of capacitors 60. Each capacitor 60 is electrically connected to the top of a corresponding one of the active area pillars 10 through a node contact structure 12.
In the disclosed embodiment, the capacitor 60 may be a sleeve capacitor. The bottom plate in each capacitor 60 is electrically connected to the top of a corresponding one of the active area pillars 10. Thus, the active region pillar 10 forms a Transistor, and one end of the source or drain of the Transistor is connected to the lower plate of the Capacitor 60, thereby forming a 1T1C (1 Transistor-1 Capacitor) memory cell.
In some embodiments of the present disclosure, referring to fig. 1 or 4, the included angle of the first direction X and the second direction Y may be 60 °. Accordingly, the plurality of capacitors 60 in fig. 6 may be arranged in a honeycomb shape in a top view. In this way, on the one hand, the cross-sectional dimensions of each capacitor 60 can be increased, thereby increasing the capacity of each capacitor 60, and on the other hand, the robustness of the overall semiconductor structure is also increased.
In some embodiments of the present disclosure, referring to fig. 5, the semiconductor structure further includes a dielectric layer 41. Dielectric layer 41 covers the top ends of the plurality of active area pillars 10 and surrounds the sidewalls of the plurality of node contact structures 12, electrically isolating the different node contact structures 12.
In some embodiments of the present disclosure, referring to fig. 6, the semiconductor structure further includes a pad structure 70. The pad structure 70 is located on the back surface of the substrate and electrically connected to the corresponding bit line 50. The pad structure 70 may be bonded (bonded) with corresponding pads of other chips, for example, hybrid bonding (hybrid bonding) of a memory chip and a logic chip, thereby implementing a 3D stacked structure.
Fig. 10A to 15 illustrate intermediate structures in the method for forming a semiconductor structure according to the embodiment of the present disclosure, for describing and clearly illustrating the steps of the method for forming a semiconductor structure. Fig. 10A, 11A, 12A, 13A, and 14A are plan views, and fig. 10B, 11B, 12B, 13B, and 14B are corresponding cross-sectional views (cross-sectional line A-A 1).
Fig. 7 is a schematic flow chart of an alternative method for forming a semiconductor structure according to an embodiment of the disclosure. As shown in FIG. 7, the method for forming the semiconductor structure includes steps S101 to S105, which will be described in connection with the steps.
S101, providing a substrate, forming a plurality of initial active area columns extending along the vertical direction on the front surface of the substrate, forming an array of m/2 rows and n columns along the first direction and the second direction, and forming a shallow trench isolation structure between adjacent initial active area columns, wherein m and n are both greater than 1, and the first direction and the second direction are respectively perpendicular to the vertical direction.
In the disclosed embodiment, referring to fig. 10A and 10B, the front surface of the substrate 00 is extended in the vertical direction Z with a plurality of initial active region pillars 01. A plurality of initial active area pillars 01 form an array of m/2 rows and n columns along a first direction X and a second direction Y. Wherein each row of initial active region pillars 01 is arranged along a first direction X, and each column of initial active region pillars 01 is arranged along a second direction Y. The first direction X and the second direction Y are perpendicular to the vertical direction Z, respectively.
With continued reference to fig. 10A and 10B, shallow trench isolation structures 42 are formed between adjacent initial active area pillars 01. The shallow trench isolation structure 42 is composed of a dielectric material (e.g., semiconductor oxide) to electrically isolate the different initial active region pillars 01.
S102, etching the shallow trench isolation structure, and forming a first trench extending along a first direction between two adjacent rows of initial active region columns, wherein the rest shallow trench isolation structure covers the side wall of the initial active region columns to form a gate oxide layer.
In the embodiments of the present disclosure, the shallow trench isolation structure 42 in fig. 10A and 10B may be etched, and a first trench extending along the first direction X is formed between two adjacent rows of the initial active region pillars 01. Further, referring to fig. 11A and 11B, the remaining shallow trench isolation structure 42 covers the sidewall of the initial active region pillar 01, forming the gate oxide layer 11.
S103, forming m word lines extending along a first direction, wherein the 2i-1 th word line and the 2i-1 th word line are formed in a corresponding first groove and respectively cover the side walls of corresponding initial active area columns, and i is larger than or equal to 1 and smaller than m/2.
In the embodiment of the present disclosure, referring to fig. 11A and 11B, the word line 20 extending in the first direction X may be formed in the first trench. Each two word lines 20 are formed in a corresponding first trench, each word line 20 covers a sidewall of a corresponding initial active region pillar 01, and the gate oxide 11 is located between the word line 20 and the sidewall of the initial active region pillar 01.
In some embodiments of the present disclosure, the word line 20 shown in fig. 11A and 11B may be formed by first filling the first trenches with a word line conductive material, and then etching the word line conductive material in each of the first trenches to sever the word line conductive material into two portions, thereby forming two word lines 20. Thus, two word lines 20 are formed in one first trench, and a void is formed at the position where etching is cut off, so that an air gap can be formed.
S104, etching to form second grooves extending along the first direction in the middle of each row of initial active area columns, and dividing each row of initial active area columns into two rows of active area columns.
In the embodiment of the disclosure, after the word line 20 is formed, the second trench extending along the first direction X may be etched in the middle of each row of the initial active region pillars 01 in fig. 11A and 11B, so that each row of the initial active region pillars 01 in fig. 11A and 11B is divided into two rows of the active region pillars 10 in fig. 12A and 12B. Since the outer side of the initial active region pillar 01 located at the outermost edge is not covered with the word line 20, only half of the word line 20 is covered as the active region pillar 10 after being divided into two by etching.
That is, each of the initial active region pillars 01 of fig. 11A and 11B is divided into two corresponding active region pillars 10 of fig. 12A and 12B, such that a plurality of active region pillars 10 are formed in an array of m rows and n columns in the first direction X and the second direction Y.
Meanwhile, the 2i-1 th and 2 i-th word lines 20 are located in the first trenches between the 2i-1 st and 2 i-th rows of the active region pillars 10, and cover the sidewalls of the corresponding active region pillars 10, respectively. The portion of the active area pillar 10 covered by the word line 20 may form the channel of the transistor, and the voltage on the word line 20 may control the channel to be turned on or off.
It can be understood that the word line 20 covers the sidewall of the active region pillar 10 to control the on or off of the channel, so that the contact area between the word line 20 and the channel is larger, thereby increasing the control force on the channel and enabling the on or off of the channel to be more thorough, further increasing the on current I on of the transistor and reducing the off current I off of the transistor, thereby reducing the power consumption.
In some embodiments of the present disclosure, referring to fig. 12A and 12B, after etching to form the second trenches, dividing each row of initial active area pillars into two corresponding rows of active area pillars 10, a dielectric material may be deposited within the second trenches to form isolation structures 40 extending along the first direction X.
It will be appreciated that the isolation structures 40 are located between row 2i and 2i+1 active area pillars 10, and between row 2i and 2i+1 word lines 20. The isolation structure 40 is used between the word lines 20 with larger spacing (i.e., between the 2i-th and 2i+1-th word lines 20), which ensures that the parasitic capacitance C wl between the word lines 20 is kept within a small range. At the same time, the isolation structure 40 can provide good support for the entire semiconductor structure, ensuring the stability of the entire semiconductor structure.
In the disclosed embodiment, with continued reference to fig. 12B, the depth of the second trench in which the isolation structure 40 is located is greater than the depth of the first trench in which the air gap 30 is located. In this way, the isolation structure 40 is able to better isolate the different rows of active area pillars 10 from shorting and cross-talk.
S105, a deposited dielectric layer covers the tops of the active area columns, and an air gap is formed between the 2i-1 th word line and the 2 i-th word line.
In the disclosed embodiment, referring to fig. 12A and 12B, after the word lines 20 are formed, a dielectric layer may be deposited to cover the tops of the active area pillars 10, such that an air gap 30 is formed between the 2i-1 st and 2 i-th word lines (i.e., between the word lines 20 of the same first trench). The air gap 30 has better insulation and lower dielectric constant than a general dielectric, so that the parasitic capacitance C wl between the 2i-1 th and 2 i-th word lines 20 can be kept in a small range.
It will be appreciated that the presently disclosed embodiments form a novel semiconductor structure having an array of active area pillars 10 arranged such that the 2i-1 and 2 i-th word lines 20 are disposed in the first trench between the 2i-1 and 2 i-th rows of active area pillars 10, and an air gap 30 is disposed between the 2i-1 and 2 i-th word lines 20. In this way, the 2i-1 th and 2 i-th word lines 20 with smaller pitches are electrically isolated by the air gap 30 with better insulation and lower dielectric constant, and at the same time, the pitches between the 2 i-th and 2i+1-th word lines 20 are pulled up, so that the parasitic capacitance C wl between every two adjacent word lines is kept in a small range.
That is, the embodiments of the present disclosure do not need to increase the space between adjacent active region pillars 10, so that the overall occupied area of the semiconductor structure is smaller, while ensuring that the parasitic capacitance C wl between adjacent word lines is kept in a smaller range. That is, the embodiment of the disclosure forms a semiconductor structure with higher integration level and better electrical property.
In some embodiments of the present disclosure, after S105 shown in fig. 7, the method for forming a semiconductor structure further includes S106 to S109 shown in fig. 8, which will be described in connection with the steps.
S106, forming a patterned mask on the dielectric layer.
And S107, etching the dielectric layer according to the mask, and forming a plurality of through holes in the dielectric layer, wherein each through hole exposes the top end of a corresponding active area column.
S108, depositing and forming a plurality of node contact structures in the plurality of through holes, wherein each node contact structure is connected with the top end of a corresponding active area column.
In the embodiment of the present disclosure, referring to fig. 13A and 13B, node contact structures 12 are formed at the top ends of the active region pillars 10, each node contact structure 12 being connected to the top end of a corresponding one of the active region pillars 10. Dielectric layer 41 covers the top of each active region pillar 10 and surrounds the sidewalls of each node contact structure 12, electrically isolating the different node contact structures 12.
And S109, forming a plurality of capacitors, wherein each capacitor is electrically connected with the top end of a corresponding active area column through a node contact structure.
In the disclosed embodiment, with continued reference to fig. 13A and 13B, a plurality of capacitors 60 are formed over dielectric layer 41. Each capacitor 60 is electrically connected to the top of a corresponding one of the active area pillars 10 through a node contact structure 12.
In the disclosed embodiment, the capacitor 60 may be a sleeve capacitor. The bottom plate in each capacitor 60 is electrically connected to the top of a corresponding one of the active area pillars 10. In this way, the active region pillars 10 form transistors, and one of the source or drain of the transistor is connected to the lower plate in the capacitor 60, thereby forming a 1T1C memory cell.
In some embodiments of the present disclosure, referring to fig. 13A, the included angle of the first direction X and the second direction Y may be 60 °. Accordingly, the plurality of capacitors 60 may be arranged in a honeycomb shape in a top view. In this way, on the one hand, the cross-sectional dimensions of each capacitor 60 can be increased, thereby increasing the capacity of each capacitor 60, and on the other hand, the robustness of the overall semiconductor structure is also increased.
In some embodiments of the present disclosure, after S109 shown in fig. 8, the method for forming a semiconductor structure further includes S110 to S112 shown in fig. 9, which will be described in connection with the steps.
S110, thinning the back surface of the substrate.
S111, forming a plurality of bit line contact structures at the bottom ends of the plurality of active region columns, wherein the bottom ends of every two active region columns are connected with a corresponding bit line contact structure.
S112, filling metal materials into the substrate from the back of the substrate to form n bit lines, wherein each bit line is electrically connected with the bottom end of a corresponding column of active region columns through a bit line contact structure.
In the embodiment of the present disclosure, referring to fig. 14A and 14B, n bit lines 50 extending in the second direction Y are formed at the back surface of the substrate. In this way, in the manufacturing process, an array boundary (array boundary) is not required to be set, and the size of each unit can be designed to be smaller, so that on one hand, the integration level can be improved, on the other hand, each area is easier to arrange in the chip design, and the design difficulty is reduced.
In the embodiment of the present disclosure, referring to fig. 14B, the bottom ends of each of the two active region pillars 10 are connected to a corresponding one of the bit line contact structures 13. Each bit line 50 is electrically connected to the bottom ends of a corresponding column of active area pillars 10 through bit line contact structures 13. In this embodiment of the disclosure, the dimension of each bit line contact structure 13 may be made larger than that of each active region pillar corresponding to one bit line contact structure, so that, on one hand, the resistance of the bit line contact structure 13 itself is lower, and on the other hand, the contact area between the bit line contact structure 13 and the bit line is larger and the contact resistance is lower. At the same time, the bit line contact structure 13 is larger in size, improving the sensing capability (sensing) of the bit line to the device. In summary, the power consumption of the entire semiconductor structure is reduced.
It will be appreciated that, on the one hand, the plurality of node contact structures 12 and the plurality of bit line contact structures 13 are disposed at the top and bottom ends (i.e., the front and back sides of the substrate) of the active region pillar 10, respectively, so that there is enough space to dispose the node contact structures 12 and the bit line contact structures 13, and the node contact structures 12 and the bit line contact structures 13 can be designed to be larger in size, thereby reducing the resistance of the node contact structures 12 and the bit line contact structures 13, and thus, the power consumption of the entire semiconductor structure. On the other hand, since the node contact structure 12 and the bit line contact structure 13 are respectively disposed at both ends of the active region pillar 10, the node contact structure 12 and the bit line contact structure 13 can be processed from both ends, respectively, without interfering with each other during the manufacturing process, thereby simplifying the manufacturing process.
In some embodiments of the present disclosure, after S113 shown in fig. 9, the method for forming a semiconductor structure further includes S114, which will be described in connection with the steps.
And S114, forming a pad structure on the back surface of the substrate, wherein the pad structure is electrically connected with the corresponding bit line.
In the disclosed embodiment, referring to fig. 15, after the bit line 50 is formed on the back surface of the substrate, a pad structure 70 may be formed on the back surface of the substrate. The pad structure 70 is electrically connected to the corresponding bit line 50. The pad structure 70 may be bonded (bonded) with corresponding pads of other chips, for example, hybrid bonding (hybrid bonding) of a memory chip and a logic chip, thereby implementing a 3D stacked structure.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.
Claims (15)
1.A semiconductor structure, the semiconductor structure comprising:
The device comprises a substrate, a plurality of active area columns, a plurality of light-emitting diode (OLED) display panel, a display panel and a display panel, wherein the plurality of active area columns are arranged on the front surface of the substrate and extend along the vertical direction;
The device comprises an active area column, an m word line, an air gap, a second air gap and a third air gap, wherein the m word line extends along the first direction and is arranged along the second direction, the 2i-1 th word line and the 2 i-th word line are located in a first groove between the active area column of the 2i-1 th row and respectively cover the side wall of the corresponding active area column, and the air gap is arranged between the 2i-1 th word line and the 2 i-th word line, wherein i is larger than or equal to 1 and smaller than m/2.
2. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
the isolation structures extend along the first direction and are sequentially arranged along the second direction, and the isolation structures are located in second grooves between the 2 i-th row and the 2i+1-th row of the active area columns.
3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
And the grid electrode oxidation layer is formed between each word line and the corresponding side wall of the active region column.
4. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
a plurality of node contact structures, each node contact structure being located at a top end of a corresponding one of the active region pillars;
and the bottom ends of every two active area columns are connected with a corresponding bit line contact structure.
5. The semiconductor structure of claim 4, further comprising n bit lines extending in the second direction and located on a backside of the substrate, each bit line electrically connected to a bottom end of a corresponding column of the active region pillars through the bit line contact structure.
6. The semiconductor structure of claim 4, further comprising a plurality of capacitors;
each capacitor is electrically connected with the top end of a corresponding active area column through one node contact structure.
7. The semiconductor structure of claim 6, wherein,
The included angle between the first direction and the second direction is 60 degrees;
the capacitors are arranged in a honeycomb mode.
8. The semiconductor structure of claim 4, wherein the semiconductor structure further comprises:
And the dielectric layer covers the top ends of the active area pillars and surrounds the side walls of the node contact structures.
9. The semiconductor structure of claim 5, wherein the semiconductor structure further comprises:
And the bonding pad structure is positioned on the back surface of the substrate and is electrically connected with the corresponding bit line.
10. A method of forming a semiconductor structure, the method comprising:
The method comprises the steps of providing a substrate, forming a plurality of initial active area columns extending along the vertical direction on the front surface of the substrate, forming an array of m/2 rows and n columns along a first direction and a second direction on the initial active area columns, and forming a shallow trench isolation structure between adjacent initial active area columns, wherein m and n are both greater than 1, and the first direction and the second direction are respectively perpendicular to the vertical direction;
Etching the shallow trench isolation structure to form a first trench extending along the first direction between two adjacent rows of the initial active region columns, wherein the rest shallow trench isolation structure covers the side wall of the initial active region columns to form a gate oxide layer;
Forming m word lines extending along the first direction, wherein the 2i-1 th word line and the 2i-1 th word line are formed in a corresponding first groove and respectively cover the side walls of the corresponding initial active area column, and i is larger than or equal to 1 and smaller than m/2;
Etching to form second grooves extending along the first direction in the middle of each row of the initial active area columns, and dividing each row of the initial active area columns into two rows of active area columns;
a deposited dielectric layer covers the tops of the active area pillars and forms an air gap between the word lines of clauses 2i-1 and 2 i.
11. The method of claim 10, wherein after depositing the dielectric layer to cover the tops of the active area pillars, the method further comprises:
Forming a patterned mask on the dielectric layer;
Etching the dielectric layer according to the mask to form a plurality of through holes in the dielectric layer, wherein each through hole exposes the top end of a corresponding active area column;
Depositing a plurality of node contact structures in the plurality of through holes, wherein each node contact structure is connected with the top end of a corresponding active area column;
And each capacitor is electrically connected with the top end of a corresponding active area column through one node contact structure.
12. The method of forming a semiconductor structure of claim 11, wherein after forming a plurality of the capacitors, the method further comprises:
Thinning the back surface of the substrate;
Forming a plurality of bit line contact structures at the bottom ends of the active region columns, wherein the bottom ends of every two active region columns are connected with a corresponding bit line contact structure;
and each bit line is electrically connected with the bottom end of a corresponding column of the active region column through the bit line contact structure.
13. The method of forming a semiconductor structure of claim 12, wherein after forming n of said bit lines and a plurality of said bit line contact structures, said method further comprises:
And forming a bonding pad structure on the back surface of the substrate, wherein the bonding pad structure is electrically connected with the corresponding bit line.
14. The method of forming a semiconductor structure of claim 10, wherein forming m of the word lines extending in the first direction comprises:
filling word line conductive materials in the first grooves;
And etching the word line conductive material in each first groove, and cutting the word line conductive material into two parts to form two word lines.
15. The method of claim 10, further comprising, after etching to form the second trench:
A dielectric material is deposited within the second trench forming an isolation structure extending along the first direction.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120018801A1 (en) * | 2010-07-20 | 2012-01-26 | Powerchip Technology Corporation | Vertical channel transistor array and manufacturing method thereof |
| CN115188763A (en) * | 2022-07-18 | 2022-10-14 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN116133393A (en) * | 2021-09-13 | 2023-05-16 | 长鑫存储技术有限公司 | Method for forming semiconductor structure and semiconductor structure |
| CN116133381A (en) * | 2021-08-25 | 2023-05-16 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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| US7359226B2 (en) * | 2006-08-28 | 2008-04-15 | Qimonda Ag | Transistor, memory cell array and method for forming and operating a memory device |
| CN115915750B (en) * | 2021-08-16 | 2025-08-22 | 长鑫存储技术有限公司 | Semiconductor device, electronic device and manufacturing method |
| CN115148706A (en) * | 2022-05-23 | 2022-10-04 | 长鑫存储技术有限公司 | Semiconductor structure, test structure, preparation method and test method |
| CN115483270A (en) * | 2022-10-11 | 2022-12-16 | 长鑫存储技术有限公司 | Semiconductor device, manufacturing method thereof and memory |
| CN115472612A (en) * | 2022-10-11 | 2022-12-13 | 长鑫存储技术有限公司 | Semiconductor device and its forming method, memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20120018801A1 (en) * | 2010-07-20 | 2012-01-26 | Powerchip Technology Corporation | Vertical channel transistor array and manufacturing method thereof |
| CN116133381A (en) * | 2021-08-25 | 2023-05-16 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN116133393A (en) * | 2021-09-13 | 2023-05-16 | 长鑫存储技术有限公司 | Method for forming semiconductor structure and semiconductor structure |
| CN115188763A (en) * | 2022-07-18 | 2022-10-14 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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