CN119761298B - A method, device, equipment and storage medium for optimizing solder ball arrangement - Google Patents
A method, device, equipment and storage medium for optimizing solder ball arrangement Download PDFInfo
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- CN119761298B CN119761298B CN202510262946.3A CN202510262946A CN119761298B CN 119761298 B CN119761298 B CN 119761298B CN 202510262946 A CN202510262946 A CN 202510262946A CN 119761298 B CN119761298 B CN 119761298B
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Abstract
The application discloses a method, a device, equipment and a storage medium for optimizing solder ball arrangement, which relate to the technical field of semiconductor packaging; and planning the arrangement mode of the signal balls in the solder ball arrangement area according to the temperature distribution of the power supply. According to the application, temperature factors are introduced, the arrangement of the solder balls is evaluated in a finer manner, and the risk of products is eliminated from the source end.
Description
Technical Field
The present application relates to the field of semiconductor packaging technology, and in particular, to a method, an apparatus, a device, and a storage medium for optimizing solder ball arrangement.
Background
BGA (Ball GRID ARRAY ) arrangement refers to the layout of solder balls at the bottom of the package in Ball grid array packaging technology. The BGA package is connected with a PCB (Printed Circuit Board ) through a series of solder balls at the bottom, and the solder balls are arranged according to a certain array, so that more input/output pins can be provided than the traditional package type, and meanwhile, the solder balls are directly positioned at the bottom of the package, so that the packaging density and the electrical performance of a circuit are improved.
Generally, solder balls consist essentially of power balls (Power Balls) and signal balls (Signal Balls):
Power balls refer to solder balls dedicated to connecting power and ground. These solder balls are responsible for providing power and ground references for the chip in the BGA package and are critical to ensure stable operation of the circuit. The power ball is typically designed to be larger than the signal ball to withstand higher currents depending on the current requirements.
The signal balls refer to solder balls for transmitting data signals and control signals. The signal ball connects the input/output pin of the chip to the corresponding welding spot on the PCB, which is responsible for data transmission. The arrangement of the signal balls needs to consider factors such as signal integrity, electromagnetic compatibility, thermal distribution and the like.
In BGA layout designs, attention is usually paid to signal integrity, however, existing solder ball arrangements are more considered based on experience of related products, whether routing is smooth, and distribution of related structural members, which brings a certain risk to subsequent products.
Disclosure of Invention
The application provides a method, a device, equipment and a storage medium for optimizing solder ball arrangement, which introduce temperature factors, evaluate the arrangement of solder balls in a finer manner and avoid the risk of products from a source end.
In a first aspect, an embodiment of the present application provides a method for optimizing solder ball arrangement, where the method for optimizing solder ball arrangement includes the following steps:
determining an arrangement area of the power supply balls;
carrying out temperature rise region simulation on the power supply based on the arrangement region of the power supply balls, and determining the temperature distribution of the power supply;
and planning the arrangement mode of the signal balls in the solder ball arrangement area according to the temperature distribution of the power supply.
With reference to the first aspect, in an implementation manner, the determining an arrangement area of the power balls includes:
And estimating the arrangement area of the power supply balls according to the preliminary arrangement of the chip floor plan floorplan.
With reference to the first aspect, in an implementation manner, the performing temperature rise region simulation on the power supply based on the arrangement region of the power supply balls to determine a temperature distribution of the power supply includes:
determining the type of the power supply according to the power consumption information;
Determining the temperature distribution of each type of power supply based on the power supply type and the arrangement area of the corresponding power supply ball;
And integrating the temperature distribution of all power supply types to determine the temperature distribution of the final total power supply.
In combination with the first aspect, in one embodiment, when the arrangement area of the signal balls is insufficient, the position of the power bump on floorplan is adjusted so that the temperature influence of the power is more concentrated.
With reference to the first aspect, in an implementation manner, the step of planning, according to a temperature distribution of the power supply, an arrangement manner of the signal balls in the solder ball arrangement area includes:
dividing the temperature grade of the solder ball arrangement area according to the temperature distribution of the power supply, and determining a critical temperature grade;
and arranging the signal balls with the speed not lower than the set value on the area not higher than the critical temperature level.
In a second aspect, an embodiment of the present application provides an apparatus for optimizing solder ball arrangement, where the apparatus for optimizing solder ball arrangement includes:
a calculation module for determining an arrangement area of the power balls;
The simulation module is used for carrying out temperature rise region simulation on the power supply based on the arrangement region of the power supply balls and determining the temperature distribution of the power supply;
And the planning module is used for planning the arrangement mode of the signal balls in the solder ball arrangement area according to the temperature distribution of the power supply.
With reference to the second aspect, in one embodiment, the determining, by the computing module, an arrangement area of the power balls includes:
And estimating the arrangement area of the power supply balls according to the preliminary arrangement of the chip floor plan floorplan.
With reference to the second aspect, in one implementation manner, the simulation module performs temperature rise region simulation on the power supply based on the arrangement region of the power supply balls, and determines temperature distribution of the power supply, including:
determining the type of the power supply according to the power consumption information;
Determining the temperature distribution of each type of power supply based on the power supply type and the arrangement area of the corresponding power supply ball;
And integrating the temperature distribution of all power supply types to determine the temperature distribution of the final total power supply.
In a third aspect, an embodiment of the present application provides an apparatus for optimizing solder ball arrangement, where the apparatus for optimizing solder ball arrangement includes a processor, a memory, and a program for optimizing solder ball arrangement stored on the memory and executable by the processor, where the program for optimizing solder ball arrangement, when executed by the processor, implements the steps of the method for optimizing solder ball arrangement described above.
In a fourth aspect, a computer readable storage medium stores a program for optimizing solder ball arrangement, where the program for optimizing solder ball arrangement, when executed by a processor, implements the steps of the method for optimizing solder ball arrangement described above.
The technical scheme provided by the embodiment of the application has the beneficial effects that at least:
the method for optimizing the arrangement of the solder balls comprises the steps of determining an arrangement area of the power balls, simulating a temperature rise area of a power source based on the arrangement area of the power balls, determining temperature distribution of the power source, and planning an arrangement mode of signal balls in the arrangement area of the solder balls according to the temperature distribution of the power source. The temperature factors are introduced, so that the arrangement of the solder balls is evaluated in a finer mode, the influence of a high-power-consumption product temperature rise area on the signal integrity can be well solved, and the risk of the product is eliminated from a source end.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for optimizing solder ball placement according to the present application;
FIG. 2 is a flow chart of step S2 of the present application;
FIG. 3 is a flowchart of step S3 of the present application;
FIG. 4 is a schematic diagram showing the temperature distribution of the power supply of the present application;
FIG. 5 is a block diagram illustrating an embodiment of an apparatus for optimizing solder ball placement according to the present application;
fig. 6 is a schematic hardware structure of an apparatus for optimizing solder ball arrangement according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
In a first aspect, an embodiment of the present application provides a method for optimizing solder ball placement.
In an embodiment, referring to fig. 1, fig. 1 is a flow chart illustrating an embodiment of a method for optimizing solder ball arrangement according to the present application. As shown in fig. 1, the method for optimizing the arrangement of the solder balls comprises the following steps:
S1, determining an arrangement area of power supply balls;
It should be noted that, in this embodiment, the arrangement area of the power balls needs to be determined first, and the arrangement area of the power balls may be estimated generally according to the preliminary arrangement of the chip layout floorplan.
The layout in the chip refers to the layout of physical layout and wiring of each functional module inside the chip when designing the integrated circuit. The aim is to achieve an optimal balance of performance, power consumption and cost in a limited chip area.
S2, carrying out temperature rise region simulation on the power supply based on the arrangement region of the power supply balls, and determining the temperature distribution of the power supply;
It can be understood that after knowing the arrangement area of the power supply balls, the temperature rise area simulation can be performed on the power supply to determine the temperature distribution of the power supply.
Generally, due to different power consumption, parameters of the power supplies will be different, and for accurately determining the temperature distribution of the power supplies, as shown in fig. 2, step S2 specifically includes:
s21, determining the type of the power supply according to the power consumption information;
S22, determining the temperature distribution of each type of power supply based on the power supply type and the arrangement area of the corresponding power supply balls;
S23, integrating the temperature distribution of all power supply types, and determining the temperature distribution of the final total power supply.
That is, the resulting temperature profile is superimposed to take into account all the effects of the power supply.
S3, planning an arrangement mode of the signal balls in the solder ball arrangement area according to the temperature distribution of the power supply.
Specifically, referring to fig. 3, step S3 includes:
s31, dividing the temperature grade of the solder ball arrangement area according to the temperature distribution of the power supply, and determining a critical temperature grade;
referring to fig. 4, the power supply is corresponding to the power supply ball, namely the influence area in the diagram, and then the arrangement area of the solder balls is divided by different colors, wherein the temperature of the red area is highest, and then the temperature gradually decreases as the distance from the power supply is farther. In this embodiment, a critical temperature level is divided according to the actual situation, so as to plan the position of the signal ball,
S32, arranging the signal balls with the speed not lower than the set value on the area not higher than the critical temperature level.
It should be noted that, in this embodiment, after the temperature distribution is determined, the main thing to do is to avoid arranging the high-speed signal balls in a region with a higher temperature rise, such as a red region.
The speed of the high speed signal balls does not have a fixed value because it depends on a variety of factors including signal type, circuit design, packaging characteristics, PCB materials, manufacturing process, etc.
Taking PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, peripheral component interconnect high speed) as an example, the first generation is 2.5 Gbps, the second generation is 5 Gbps, and the third generation is 8 Gbps.
For this reason, the set value in the present embodiment may be 5 Gbps or 8 Gbps, etc., and the present embodiment does not limit this, and it may be set reasonably according to the actual situation.
After the set value is determined, the signal balls satisfying the condition will not be disposed in an area where the temperature is too high. Thus, the influence of temperature rise on signals can be well prevented. The application optimizes the arrangement of the signal balls from the source before the production of the product, and has a prospective effect compared with the prior art that the heat insulation and the heat dissipation device are additionally arranged after the product is produced.
In addition, if the arrangement area of the signal balls is insufficient based on the current floorplan, the position of the power bump on floorplan is adjusted so that the temperature influence of the power is more concentrated. It will be appreciated that if the distribution of the power balls is too diffuse, the area it will affect will be wider, and if the power balls are relatively concentrated, the area they cover will be smaller, at which point more area will be available for routing the signal balls.
It should be noted that, the Bump refers to a tiny Bump on the chip body, for connecting the chip and the package, and the size of the Bump is smaller than that of Ball (power Ball, signal Ball), and typically, multiple bumps are connected to one Ball. If the arrangement area of the signal balls is insufficient, the position of the power supply lamp needs to be adjusted at the source, so that the position of the power supply balls is adjusted, and an arrangement space is reserved for the signal balls. That is, the design of the power supply lamp on floorplan can be optimized in reverse through the arrangement condition of the signal balls, so that the structure of the chip is more reasonable.
In summary, the method for optimizing the arrangement of the solder balls comprises the steps of determining an arrangement area of the power balls, simulating a temperature rise area of a power source based on the arrangement area of the power balls, determining the temperature distribution of the power source, and planning the arrangement mode of the signal balls in the arrangement area of the solder balls according to the temperature distribution of the power source. The temperature factors are introduced, so that the arrangement of the solder balls is evaluated in a finer mode, the influence of a high-power-consumption product temperature rise area on the signal integrity can be well solved, and the risk of the product is eliminated from a source end.
In a second aspect, the embodiment of the application further provides a device for optimizing the arrangement of the solder balls.
In an embodiment, referring to fig. 5, fig. 5 is a schematic functional block diagram of an apparatus for optimizing solder ball arrangement according to an embodiment of the present application. As shown in fig. 5, the device for optimizing solder ball arrangement includes an acquisition module, a simulation module and a planning module.
The computing module is used for determining an arrangement area of the power supply balls; the simulation module simulates the temperature rise area of the power supply based on the arrangement area of the power supply balls to determine the temperature distribution of the power supply, and the planning module plans the arrangement mode of the signal balls in the arrangement area of the solder balls according to the temperature distribution of the power supply.
Further, in an embodiment, the calculating module determines an arrangement area of the power balls, including:
And estimating the arrangement area of the power supply balls according to the preliminary arrangement of the chip floor plan floorplan.
Further, in an embodiment, the simulation module performs temperature rise region simulation on the power supply based on the arrangement region of the power supply balls, and determines the temperature distribution of the power supply, including:
determining the type of the power supply according to the power consumption information;
Determining the temperature distribution of each type of power supply based on the power supply type and the arrangement area of the corresponding power supply ball;
And integrating the temperature distribution of all power supply types to determine the temperature distribution of the final total power supply.
Further, in an embodiment, the planning module plans an arrangement mode of the signal balls in the solder ball arrangement area according to a temperature distribution of the power supply, including:
dividing the temperature grade of the solder ball arrangement area according to the temperature distribution of the power supply, and determining a critical temperature grade;
and arranging the signal balls with the speed not lower than the set value on the area not higher than the critical temperature level.
The function implementation of each module in the device for optimizing solder ball arrangement corresponds to each step in the method embodiment for optimizing solder ball arrangement, and the function and implementation process of the function implementation are not described in detail herein.
In a third aspect, an embodiment of the present application provides an apparatus for optimizing solder ball arrangement, where the apparatus for optimizing solder ball arrangement may be a device having a data processing function, such as a personal computer (personal computer, PC), a notebook computer, a server, or the like.
Referring to fig. 6, fig. 6 is a schematic diagram of a hardware structure of an apparatus for optimizing solder ball arrangement according to an embodiment of the present application. In an embodiment of the present application, an apparatus for optimizing solder ball arrangement may include a processor, a memory, a communication interface, and a communication bus.
The communication bus may be of any type for implementing the processor, memory, and communication interface interconnections.
Communication interfaces include input/output (I/O) interfaces, physical interfaces, logical interfaces, and the like for implementing device interconnections within the device that optimizes solder ball placement, and interfaces for implementing interconnection of the device that optimizes solder ball placement with other devices (e.g., other computing devices or user devices). The physical interface may be an ethernet interface, an optical fiber interface, an ATM interface, etc., and the user device may be a Display screen (Display), a Keyboard (Keyboard), etc.
The memory may be various types of storage media such as random access memory (randomaccess memory, RAM), read-only memory (ROM), nonvolatile RAM (non-volatileRAM, NVRAM), flash memory, optical memory, hard disk, programmable ROM (PROM), erasable PROM (erasable PROM, EPROM), electrically erasable PROM (ELECTRICALLY ERASABLE PROM, EEPROM), and the like.
The processor may be a general-purpose processor, and the general-purpose processor may call a program for optimizing solder ball arrangement stored in the memory, and execute the method for optimizing solder ball arrangement provided by the embodiment of the present application. For example, the general purpose processor may be a central processing unit (central processing unit, CPU). The method executed when the procedure for optimizing solder ball arrangement is called may refer to various embodiments of the method for optimizing solder ball arrangement according to the present application, and will not be described herein.
Those skilled in the art will appreciate that the hardware configuration shown in fig. 6 is not limiting of the application and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
In a fourth aspect, embodiments of the present application also provide a readable storage medium.
The readable storage medium of the present application stores a program for optimizing solder ball arrangement, wherein the program for optimizing solder ball arrangement realizes the steps of the method for optimizing solder ball arrangement as described above when executed by a processor.
The method implemented when the procedure for optimizing solder ball arrangement is executed may refer to various embodiments of the method for optimizing solder ball arrangement according to the present application, and will not be described herein.
It should be noted that, the foregoing reference numerals of the embodiments of the present application are merely for describing the embodiments, and do not represent the advantages and disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above, comprising several instructions for causing a terminal device to perform the method according to the embodiments of the present application.
The terms "comprising" and "having" and any variations thereof in the description and claims of the application and in the foregoing drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The terms "first," "second," and "third," etc. are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order, and are not limited to the fact that "first," "second," and "third" are not identical.
In describing embodiments of the present application, "exemplary," "such as," or "for example," etc., are used to indicate by way of example, illustration, or description. Any embodiment or design described herein as "exemplary," "such as" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "such as" or "for example," etc., is intended to present related concepts in a concrete fashion.
In the description of the embodiment of the present application, "/" means or, for example, a/B may mean a or B, and "and/or" in the text is merely an association relationship describing an association object, means that three relationships may exist, for example, a and/or B, three cases where a exists alone, a and B exist together, and B exists alone, and further, in the description of the embodiment of the present application, "a plurality" means two or more.
In some of the processes described in the embodiments of the present application, a plurality of operations or steps occurring in a particular order are included, but it should be understood that the operations or steps may be performed out of the order in which they occur in the embodiments of the present application or in parallel, the sequence numbers of the operations merely serve to distinguish between the various operations, and the sequence numbers themselves do not represent any order of execution. In addition, the processes may include more or fewer operations, and the operations or steps may be performed in sequence or in parallel, and the operations or steps may be combined.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
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| CN108133113A (en) * | 2018-01-10 | 2018-06-08 | 华南理工大学 | Power amplifier chip design optimization method based on electric heating joint modeling and simulating |
| CN114638190A (en) * | 2022-03-28 | 2022-06-17 | 西安电子科技大学 | Array welding spot arrangement design method for minimizing mean square error of packaging stress |
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| JP3634048B2 (en) * | 1996-02-28 | 2005-03-30 | 富士通株式会社 | Semiconductor device |
| US7472363B1 (en) * | 2004-01-28 | 2008-12-30 | Gradient Design Automation Inc. | Semiconductor chip design having thermal awareness across multiple sub-system domains |
| CN100361298C (en) * | 2005-08-10 | 2008-01-09 | 威盛电子股份有限公司 | Ball grid array packaging structure and substrate thereof |
| US9740804B2 (en) * | 2014-11-03 | 2017-08-22 | Mentor Graphics Corporation | Chip-scale electrothermal analysis |
| CN118553724A (en) * | 2024-05-15 | 2024-08-27 | 嘉善复旦研究院 | Test chip, preparation method, packaging structure and packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108133113A (en) * | 2018-01-10 | 2018-06-08 | 华南理工大学 | Power amplifier chip design optimization method based on electric heating joint modeling and simulating |
| CN114638190A (en) * | 2022-03-28 | 2022-06-17 | 西安电子科技大学 | Array welding spot arrangement design method for minimizing mean square error of packaging stress |
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