CN119782218A

CN119782218A - Memory system and operation method thereof, electronic device and operation method thereof

Info

Publication number: CN119782218A
Application number: CN202311288611.6A
Authority: CN
Inventors: 高山; 何逍阳; 刘增林
Original assignee: Beijing Xiaomi Mobile Software Co Ltd
Current assignee: Beijing Xiaomi Mobile Software Co Ltd
Priority date: 2023-10-07
Filing date: 2023-10-07
Publication date: 2025-04-08

Abstract

The present disclosure relates to a memory system and an operation method thereof, an electronic device and an operation method thereof. The memory system comprises: a storage device and a volatile memory device; wherein the storage device comprises a non-volatile memory device, a first memory controller coupled to the non-volatile memory device, and a first interface; the first memory controller is configured to control the non-volatile memory device; the volatile memory device comprises a second interface; the second interface is coupled to the first interface so that the storage device and the volatile memory device can interact.

Description

Memory system, method of operating the same, electronic device, and method of operating the same

Technical Field

The present disclosure relates to the field of computer communications, and more particularly, to a memory system and an operating method thereof, an electronic device and an operating method thereof.

Background

In the related art, the interaction between the host and the volatile memory device may be implemented through a controller of the volatile memory device in the host, and the interaction between the host and the nonvolatile memory device may be implemented through a controller of the nonvolatile memory device in the host. In the case where the controller of the volatile memory device in the host is turned off, the volatile memory device cannot be accessed, resulting in waste of resources. How to improve the utilization rate of the volatile memory device is a problem to be solved.

Disclosure of Invention

To overcome the problems in the related art, the present disclosure provides a memory system and an operating method thereof, an electronic device and an operating method thereof.

According to a first aspect of embodiments of the present disclosure, there is provided a memory system comprising:

a memory device and a volatile memory means, wherein,

The storage device includes a non-volatile memory apparatus, a first memory controller coupled with the non-volatile memory apparatus, the first memory controller configured to control the non-volatile memory apparatus, the volatile memory apparatus including a second interface coupled with the first interface such that the storage device is capable of interacting with the volatile memory apparatus.

In some embodiments, the volatile memory means comprises a double rate synchronous dynamic random access memory and the storage device comprises a universal flash memory, an embedded multimedia card.

In some embodiments, the storage device is packaged on the same substrate as the volatile memory apparatus.

In some embodiments, the first interface includes a first clock signal pin area, a first power signal pin area, a first command address signal pin area, and a first data pin area, and the second interface includes a second clock signal pin area, a second power signal pin area, a second command address signal pin area, and a second data pin area;

The first clock signal pin area is coupled to the second clock signal pin area, the first power signal pin area is coupled to the second power signal pin area, the first command address signal pin area is coupled to the second command address signal pin area, and the first data pin area is coupled to the second data pin area.

According to a second aspect of embodiments of the present disclosure, there is provided an electronic device comprising a memory system as described in any of the embodiments above, and a host, the host comprising a second memory controller coupled to the memory device, a third memory controller coupled to the volatile memory means.

In some embodiments, a third memory controller includes a third interface coupled with the second interface.

In some embodiments, the third memory controller includes a third interface, the volatile memory device further includes a fourth interface, and the third interface is coupled with the fourth interface.

In some embodiments, the volatile memory device includes a plurality of modules, the first interface and the second interface each further including a functional signal pin area coupled to each other, the functional signal pin area including a first chip select signal pin and a second chip select signal pin;

the first chip select signal pin in the second interface is configured to receive a first chip select signal; the volatile memory device is configured to operate a designated module of the plurality of modules according to the first slice select signal;

The second chip select signal pin in the second interface is configured to receive a second chip select signal, and the volatile memory apparatus is configured to select to interact with the third memory controller or with the storage device according to the second chip select signal.

According to a third aspect of embodiments of the present disclosure, there is provided a method of operating a memory system, comprising:

The memory device interacts with the volatile memory apparatus based on a memory device coupled with the volatile memory apparatus, the memory device including a non-volatile memory apparatus, a first memory controller coupled with the non-volatile memory apparatus.

According to a fourth aspect of embodiments of the present disclosure, there is provided a method of operating an electronic device, comprising:

The volatile memory device interacts with the host and/or the storage device based on the volatile memory device being coupled to both the host and the storage device.

In some embodiments, the host includes a second memory controller coupled with the storage device and a third memory controller coupled with the volatile memory device;

the volatile memory-based apparatus is coupled to both a host and a storage device, the volatile memory apparatus interacting with the host and/or the storage device, comprising:

the volatile memory means interacting with the storage device when the third memory controller is in a closed state;

The volatile memory device interacts with the host when the third memory controller is in an on state.

In some embodiments, the volatile memory-based apparatus is coupled to both a host and a storage device, the volatile memory apparatus interacting with the host and/or the storage device, comprising:

When the bandwidth ratio of the host to the volatile memory device is smaller than or equal to a preset value, the volatile memory device interacts with the host and the storage equipment;

the volatile memory device interacts with the host when the bandwidth ratio of the host to the volatile memory device is greater than a preset value.

a first storage area in the volatile memory device interacts with the host and a second storage area in the volatile memory device interacts with the storage device.

The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects:

According to the embodiment of the disclosure, the first interface is arranged in the storage equipment, the second interface is arranged in the volatile memory device, and the first interface is coupled with the second interface, so that the control of the volatile memory device by using the first memory controller in the storage equipment is realized, the storage equipment and the volatile memory device can be directly interacted, the utilization rate of the volatile memory device is improved, the working efficiency of the storage equipment is improved, the storage equipment can be directly interacted with the volatile memory device without depending on a host, the host resource can be saved, the additional hardware cost is not required, and the competitiveness of consumer electronics such as a mobile phone can be improved by applying the technology.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a block diagram of a memory system shown in accordance with an exemplary embodiment;

FIG. 2 is a schematic diagram illustrating a first interface coupled to a second interface according to an example embodiment;

FIG. 3 is a block diagram of an electronic device, shown in accordance with an exemplary embodiment;

FIG. 4 is a flowchart illustrating a method of operation of a memory system, according to an example embodiment;

Fig. 5 is a flowchart illustrating a method of operation of an electronic device, according to an example embodiment.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.

Fig. 1 is a block diagram of a memory system 10, the memory system 10 including a memory device 100 and a volatile memory apparatus 200, according to an exemplary embodiment, wherein,

The memory device 100 comprises a non-volatile memory means 110, a first memory controller 120 coupled to the non-volatile memory means 110, a first interface 130, the first memory controller 120 being configured to control the non-volatile memory means 110, the volatile memory means 200 comprising a second interface 230, the second interface 230 being coupled to the first interface 130 such that the memory device 100 is capable of interacting with the volatile memory means 200.

The storage device 100 in embodiments of the present disclosure includes, but is not limited to, a universal flash storage (Universal Flash Storage, UFS) device, an embedded multimedia card (embedded Multi-MEDIA CARD, EMMC).

The memory device 100 includes a non-volatile memory arrangement 110 and a first memory controller 120. The nonvolatile Memory device 110 includes, but is not limited to, a NAND Flash Memory (NAND FLASH Memory), a NOR Flash Memory (NOR Flash Memory), a Read-Only Memory (ROM), and the like. Nonvolatile memory device 110 refers to a memory device that may retain stored data after power is turned off. The storage device 100 is illustrated as a UFS device in the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited thereto.

The first memory controller 120 in implementations of the present disclosure may be configured to control the non-volatile memory device 110. In some embodiments, the first memory controller 120 may interact with the nonvolatile memory device 110 based on instructions sent by the host. In other embodiments, the first memory controller 120 may also interact with the nonvolatile memory device 110 based on instructions embedded in the nonvolatile memory device 110. In this embodiment of the present disclosure, the storage device 100 may be a UFS device, and correspondingly, the first memory controller 120 may be an internal controller of the UFS device.

Volatile memory device 200 in the implementations of the present disclosure includes, but is not limited to, dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM), magnetic random access memory (Magnetoresistive Random Access Memory, MRAM), phase change random access memory (PHASE CHANGE Random Access Memory, PCRAM), resistive random access memory (RESISTIVE RANDOM ACCESS MEMORY, RRAM), nano random access memory (Nano Random Access Memory, NRAM), and double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate Synchronous Dynamic Random Access Memory, LPDDR SDRAM), and the like. The embodiments of the present disclosure are described in terms of the volatile memory device 200 being LPDDR5 in DDR SDRAM, it being understood that the present disclosure is not limited thereto.

In some embodiments, when storage device 100 is a UFS device, non-volatile memory apparatus 110 may be a NAND flash memory and first memory controller 120 may be an internal controller of the UFS device.

In some embodiments, when the storage apparatus 100 is eMMC, the nonvolatile memory device 110 may be a NAND flash memory, and the first memory controller 120 may be an eMMC internal controller.

The memory device 100 in the embodiments of the present disclosure includes a first interface 130, the volatile memory apparatus 200 includes a second interface 230, and the first interface 130 is coupled with the second interface 230. As such, interactions between the storage device 100 and the volatile memory apparatus 200 may be performed through the first interface 130 and the second interface 230. In some embodiments, the storage device 100 interacts with the volatile memory apparatus 200 including, but not limited to, writing data from the storage device 100 to the volatile memory apparatus 200, reading data from the volatile memory apparatus 200 and storing in the storage device 100, erasing data in the volatile memory apparatus 200 with the storage device 100, and so forth.

The first interface 130 and the second interface 230 may be coupled directly or indirectly. For example, the first interface 130 may be indirectly connected to the second interface 230 by a lead wire, thereby achieving an indirect electrical connection. For another example, the first interface 130 may include a plurality of metal pins, and the second interface 230 may also include a plurality of metal pins, where the plurality of metal pins of the first interface 130 directly contact the corresponding plurality of metal pins of the second interface 230, thereby implementing a direct electrical connection.

The first memory controller 120 may also be configured to control the volatile memory device 200. Here, the first memory controller 120 may interact with the volatile memory device 200 based on instructions transmitted from the host, or may interact with the volatile memory device 200 based on instructions embedded in the nonvolatile memory device 110. The interactions herein include, but are not limited to, performing operations of reading data, erasing data, writing data, etc. on the volatile memory device 200.

In some embodiments, the storage device 100 may be a memory and the volatile memory apparatus 200 may be a memory. It should be noted that, the storage apparatus 100 may additionally include the volatile memory device 200, but the storage apparatus 100 uses the nonvolatile memory device 110 therein as a storage medium, and uses the volatile memory device 200 included in the storage apparatus 100 as a buffer, where the buffer may temporarily store write data provided from a host or data read from the nonvolatile memory 110. The volatile memory device 200 itself serves as a storage medium.

According to the embodiment of the disclosure, the first interface 130 is arranged in the storage device 100, the second interface 230 is arranged in the volatile memory device 200, and the first interface 130 is coupled with the second interface 230, so that the control of the volatile memory device 200 by using the first memory controller 120 in the storage device 100 is realized, the storage device 100 and the volatile memory device 200 can directly interact, the utilization rate of the volatile memory device 200 is improved, the working efficiency of the storage device 100 is improved, and the competitiveness of consumer electronics such as mobile phones can be improved by applying the technology.

In some embodiments, the memory device 100 is packaged on the same substrate as the volatile memory apparatus 200.

In the embodiment of the disclosure, the storage device 100 may be a UFS device, the volatile memory device 200 may be an LPDDR5, and the storage device 100 and the volatile memory device 200 may be stacked and packaged on the same substrate by using a Multi-chip packaging technology (Multi CHIP PACKAGE, MCP) to form a universal flash Multi-layer package chip (UFS Multi CHIP PACKAGE, UMCP).

In some embodiments, the memory device 100 may be eMMC, and the volatile memory device 200 may be LPDDR5, both of which may be stacked and packaged on the same substrate using Multi-Chip packaging technology, constituting an embedded Multi-Chip-Package (eMCP).

By placing the memory device 100 and the volatile memory device 200 perpendicular to the substrate stack, the area occupied by the memory device 100 and the volatile memory device 200 can be saved, so that the uMCP chip or the eMCP chip formed after packaging is more suitable for miniaturized mobile phones and computers.

FIG. 2 is a schematic diagram illustrating a first interface 130 coupled to a second interface 230, the first interface 130 including a first clock signal pin field 410, a first power signal pin field 420, a first command address signal pin field 430, and a first data pin field 440, the second interface 230 including a second clock signal pin field 510, a second power signal pin field 520, a second command address signal pin field 530, and a second data pin field 540, according to an example embodiment;

The first clock signal pin area 410 is correspondingly coupled to the second clock signal pin area 510, the first power signal pin area 420 is correspondingly coupled to the second power signal pin area 520, the first command address signal pin area 430 is correspondingly coupled to the second command address signal pin area 530, and the first data pin area 440 is correspondingly coupled to the second data pin area 540.

The first clock signal pin field 410 and the second clock signal pin field 510 in embodiments of the present disclosure may each include multiple sets of clock signal pins. Each set of clock signal pins includes 2 clock signal pins.

The volatile memory device 200 in the embodiments of the present disclosure is LPDDR5, and the first clock signal pin area 410 and the second clock signal pin area 510 may each include 3 sets of clock signal pins. The first set of clock signal pins may include a ck_t pin and a ck_c pin. The ck_t pin is configured to transmit or receive a ck_t clock signal, and the ck_c pin is configured to transmit or receive a ck_c clock signal. The ck_t clock signal and the ck_c clock signal are a set of differential signals.

In some implementations, address, command, and control input signals are all taken on the rising edge of the ck_t clock signal, and the data strobe signal (Data Strobe Signal, DQS) is sampled at the intersection of the ck_t clock signal and the ck_c clock signal.

The second set of clock signal pins may include WCK [1:0] _t pins and WCK [1:0] _c pins. The WCK [1:0] _t pins are configured to transmit or receive WCK [1:0] _t clock signals, and the WCK [1:0] _c pins are configured to transmit or receive WCK [1:0] _c clock signals. WCK [1:0] _t clock signals and WCK [1:0] _c clock signals are a set of differential signals. WCK [1:0] _t clock signals and WCK [1:0] _c clock signals are a set of write clock signals for write operations.

The third set of clock signal pins may include RDQS [1:0] _t pins and RDQS [1:0] _c pins. The RDQS [1:0] _t pins are configured to transmit or receive RDQS [1:0] _t clock signals, and the RDQS [1:0] _c pins are configured to transmit or receive RDQS [1:0] _c clock signals. The RDQS [1:0] _t clock signal and the RDQS [1:0] _c clock signal are a set of differential signals, denoted as RDQS signals. RDQS [1:0] _t clock signal and RDQS [1:0] _c clock signal are a set of read clock signals for a read operation.

The DQS signal is a data clock signal, the RDQS signal is an inverse data clock signal, the DQS signal is used for controlling the transmission of data, the RDQS signal is used for controlling the reception of data, the DQS signal and the RDQS signal are in pairs, the phase relation of the DQS signal and the RDQS signal is very important, and accurate matching is required to ensure the correct transmission of the data.

In some embodiments, RDQS may be configured in single-ended mode through a mode register, i.e., using only one of RDQS [1:0] _t or RDQS [1:0] _c, for use in a low-speed and power-saving scenario.

In the embodiment of the present disclosure, the clock signals received by the plurality of sets of clock signal pins in the second interface 230 may be from the clock signals output by the plurality of sets of clock signal pins in the corresponding first interface 130.

The first power signal pin region 420 and the second power signal pin region 520 may each include a plurality of power signal pins. In an embodiment of the present disclosure, 5 power signal pins may be included. The first power signal pin is configured to transmit or receive a VDDQ power signal, the second power signal pin is configured to transmit or receive a VDD1 power signal, the third power signal pin is configured to transmit or receive a VDD2H power signal, and the fourth power signal pin is configured to transmit or receive a VDD2L power signal. The fifth power signal pin is configured to transmit or receive a VSS power signal.

In the disclosed embodiment, the VDDQ power supply signal may be used to power the second interface 230 of the volatile memory device 200, so that the required voltage is relatively small, e.g., may be 0.5V. The VDD1 power signal, VDD2H power signal, and VDD2L power signal power peripheral circuits in the volatile memory device 200. For example, the VDD1 power signal may be 1.8V. The VDD2H power signal is typically higher than the VDD2L power signal, which may be 1.05V, and the VDD2L power signal is 0.95V. The magnitude of the VSS power supply signal may be 0V.

In other embodiments, for example, nonvolatile memory device 110 is LPDDR4, which includes 4 power signal pins configured to transmit or receive VDDQ power signals, VDD1 power signals, VDD2 power signals (similar to VDD2H power signals in LPDDR 5), and VSS power signals, respectively.

Compared to LPDDR4, LPDDR5 can use VDD2L of low voltage, thereby saving power consumption.

It will be appreciated that the number and types of power pins included in the first power signal pin field 420 and the second voltage signal pin field 520 are the same, and may be set according to actual requirements.

In the embodiment of the present disclosure, the power signals received by the plurality of power signal pins in the second interface 230 may be from the power signals output by the plurality of power signal pins in the first interface 130.

The first command address signal pin field 430 and the second command address signal pin field 530 in embodiments of the present disclosure may each include a plurality of command address signal pins.

In an embodiment of the present disclosure, 7 command address signal pins may be included. The 7 command address signal pins are configured to receive or output command address signals in the format CA [6:0 ]. It should be understood that the above number of command address signal pins is merely an example, and the present disclosure is not limited to a specific number of command address signal pins.

In the embodiment of the present disclosure, the command address signals received by the plurality of command address signal pins in the second interface 230 may be from the command address signals output by the plurality of command address signal pins in the first interface 130.

The first data pin area 440 and the second data pin area 540 in the embodiments of the present disclosure may each include a plurality of data signal pins.

In an embodiment of the present disclosure, 16 data signal pins may be included. The 16 data signal pins are configured to receive or output data signals in a format DQ [15:0 ]. It should be understood that the above number of data signal pins is merely an example, and the present disclosure is not limited to a specific number of data signal pins.

In the embodiment of the present disclosure, the data signals received by the plurality of data signal pins in the second interface 230 may be from the data signals output by the plurality of data signal pins in the first interface 130, or the data signals received by the plurality of data signal pins in the first interface 130 may be from the data signals output by the plurality of data signal pins in the second interface 230.

In the disclosed embodiment, the first interface 130 and the second interface 230 may also each include a functional signal pin field.

Fig. 3 is a block diagram of an electronic device 20 according to an exemplary embodiment, including the memory system 10 according to the above-described embodiments, and a host 300, wherein the host 300 includes a second memory controller 310, a third memory controller 320, wherein the second memory controller 310 is coupled to the memory device 100, and wherein the third memory controller 320 is coupled to the volatile memory device 200.

In the disclosed embodiment, the electronic device 20 may include a terminal device, such as a mobile terminal or a fixed terminal. The mobile terminal can comprise a mobile phone, a tablet personal computer, a notebook computer, a wearable electronic device and other devices. The fixed terminal can comprise a desktop computer, an intelligent television, vehicle-mounted equipment and the like.

The host 300 in the embodiments of the present disclosure further includes a processor 330, where the processor 330 may be the processor 330 of the electronic device 20 (e.g., the central processing unit (Central Processing Unit, CPU) may also be the processor 330 of a System on Chip (SoC) (e.g., the application processor (Application Process, AP)).

The embodiments of the present disclosure are described with host 300 as an example of a system-on-chip, it being understood that the present disclosure is not limited thereto. The system on a chip includes a processor 330, a second memory controller 310, and a third memory controller 320.

The interaction between the system on chip and the volatile memory device 200 may be implemented by the processor 330, the third memory controller 320. The third memory controller 320 is a hardware module in the system on a chip that is responsible for managing the read and write operations of the volatile memory device 200. The processor 330 of the system-on-chip fetches instructions and sends the instructions to the third memory controller 320, which third memory controller 320 converts these commands and data into a format that can be understood by the volatile memory device 200 and sends them into the volatile memory device 200. When the volatile memory device 200 completes the read and write operations, the third memory controller 320 returns the results to the processor 330 of the system-on-chip. In this way, the system on chip may interact with the volatile memory device 200 through the third memory controller 320.

Interaction between the system-on-chip and the storage device 100 (e.g., UFS device) may be achieved by the second memory controller 310.

The communication between host 300 and UFS devices is a hierarchical communication architecture based on the mini Computer interface (INTERNET SMALL Computer SYSTEM INTERFACE, SCSI) model. For example, a specific process for interaction of host 300 with a UFS device may be that an application layer of host 300, including processor 330 (e.g., an application processor), issues SCSI commands, a transport layer of host 300, including second memory controller 310, receives the SCSI commands and encapsulates them as UFS protocol information unit (UFS Protocol Information Unit, UPIU) commands that can be recognized by the UFS, and an interconnect layer of host 300 sends the UPIU commands to an interconnect layer of the UFS device by means of an electrical signal (where the interconnect layer of the host and the interconnect layer of the UFS device are used to implement a link between the host and the UFS device). The interconnect layer of the UFS device receives the electrical signal and repackages into UPIU commands via the transport layer of the UFS device, and the application layer of the UFS device receives the UPIU commands and responds.

In some embodiments, the third memory controller 320 further comprises a third interface coupled to the second interface 230.

Here, the interconnect layer of the host 300 may be a third interface, and the interconnect layer of the UFS device may be a second interface in the storage device.

In the disclosed embodiment, volatile memory device 200 is coupled to both host 300 and the UFS device through second interface 230.

In the disclosed embodiment, the first interface 130 of the UFS device is coupled with the second interface 230 of the volatile memory device 200. The third interface of the host 300 is also coupled with the second interface 230 of the volatile memory device 200. It will be appreciated that UFS device and host 300 may share a second interface 230 in volatile memory device 200, and that UFS device and host 300 are each coupled to second interface 230 in volatile memory device 200 such that the host and UFS device may have time-shared access to the volatile memory device.

In some embodiments, the third memory controller 320 includes a third interface, and the volatile memory device 200 further includes a fourth interface, the third interface being coupled with the fourth interface.

In the disclosed embodiment, the first interface 130 of the UFS device is coupled with the second interface 230 of the volatile memory device 200, and the third interface of the third memory controller 320 is coupled with the fourth interface of the volatile memory device 200. It is understood that UFS device and host 300 may not share the same interface in volatile memory device 200, such that volatile memory device 200 may interact with host 300 and the UFS device simultaneously.

The disclosed embodiments provide for the provision of the first interface 130 on the storage device 100, the provision of the second interface 230 on the volatile memory apparatus 200, and the coupling of the first interface 130 with the second interface 230, such that the storage device 100 may also interact with the volatile memory apparatus 200. The host 300 and the storage apparatus 100 may interact with the volatile memory device 200 at the same time, and the host 300 and the storage apparatus 100 may interact with the volatile memory device 200 at different times, thereby improving the utilization of the volatile memory device 200.

In some embodiments, the volatile memory device includes a plurality of modules (RANK), the first interface and the second interface each further including a functional signal pin field coupled to each other, the functional signal pin field including a first select signal pin.

In some embodiments, the volatile memory device may include a plurality of RANK. Each RANK may include a first select signal pin thereon configured to receive a first select signal. When the first slice selection signal on the corresponding RANK is valid, the read-write operation can be performed on the designated RANK. In some embodiments the first select signal is active low and in other embodiments the first select signal is active high. Here, the setting can be performed according to the corresponding specification.

a first select signal pin in the second interface is configured to receive a first select signal; the volatile memory device is configured to operate a designated module of the plurality of modules according to the first slice select signal;

The volatile memory apparatus is configured to select to interact with the third memory controller or with the storage device according to the second chip select signal.

In some embodiments, the first interface and the second interface may each include a second chip select signal pin thereon, the second chip select signal pin on the first interface configured to transmit the second chip select signal, and the second chip select signal pin on the second interface configured to receive the second chip select signal. When the second chip select signal is at the first level, the other pins on the second interface are configured to allow the signals sent by the host to be received, and to prohibit the signals sent by the storage device from being received. When the second chip select signal is at the second level, the other pins on the second interface are configured to allow receiving signals from the memory device and prohibit receiving signals from the host. By providing the second chip select signal pin in the functional signal pin field, the host and the memory device may be made time-shared to access the volatile memory arrangement. Here, the first level may be a high level or a low level. The second level is illustratively low when the first level is high and high when the first level is low.

In some embodiments, the functional signal pin field further includes a data bus flip pin configured to transmit or receive a DMI data bus flip signal. When the data on the data bus is turned over, the DMI is a high signal, and when the data on the data bus is normal, the DMI is a low signal. Each byte data may be followed by a one-bit DMI data bus flip signal.

In some embodiments, the functional signal pin field further includes a ZQ (reference resistance) pin for calibrating output drive strength and termination resistance. LPDDR5 may include one or more Die (chips), each Die may include multiple BANKs. Each Die includes a ZQ pin.

In some embodiments, the function signal pin further comprises a Reset signal pin configured to send or receive a reset_n Reset signal. When the reset_n Reset signal is active, multiple channels (channels) on Die may be Reset. The Reset _ n Reset signal may be active low.

In some embodiments, the functional signal pins may further include other pins as required and set according to relevant specifications of JEDEC, which are specified by Joint Electron DEVICE ENGINEERING Countil (JEDEC) standards, and are not described herein.

FIG. 4 is a flowchart illustrating a method of operation of a memory system, as shown in FIG. 4, including:

In step 101, a memory device interacts with a volatile memory apparatus based on the memory device being coupled with the volatile memory apparatus, the memory device including a non-volatile memory apparatus, a first memory controller coupled with the non-volatile memory apparatus.

In some implementations, by providing a first interface in a storage device, providing a second interface in a volatile memory device, and coupling the first interface with the second interface, a first memory controller in the storage device may be utilized to interact with the volatile memory device such that utilization of the volatile memory device may be improved.

Fig. 5 is a flowchart illustrating a method of operation of an electronic device, as shown in fig. 5, according to an exemplary embodiment, the method of operation comprising:

In step 201, a volatile memory device interacts with a host and/or a storage device based on the volatile memory device being coupled to both the host and the storage device.

In some embodiments, the host and the storage device may interact with the volatile memory apparatus simultaneously, and the host and the storage device may also interact with the volatile memory apparatus in a time sharing manner.

According to the embodiment of the disclosure, the first interface is arranged in the storage device, the second interface is arranged in the volatile memory device, and the first interface and the second interface are coupled, so that the first memory controller in the storage device can be used for interacting with the volatile memory device, the electronic device further comprises a host, the host and the storage device can interact with the volatile memory device in a time-sharing or simultaneous manner, the utilization rate of the volatile memory device is improved, the performance of the storage device is improved, and the storage device can interact with the volatile memory device directly without depending on the host, so that the resources of the host can be saved.

In some embodiments, the UFS device may perform garbage collection operations in the background to ensure maximum utilization of space in the flash memory. In other embodiments, the UFS device may perform bad block management operations in the background to ensure that bad blocks in the flash memory do not affect system performance and reliability. In still other embodiments, the UFS device may perform data recovery operations in the background to ensure that data in the flash memory is not lost. Garbage collection, bad block management, and data recovery can be performed during idle time to avoid affecting system performance.

In some embodiments, when the host is in the low power mode, the third memory controller may be turned off, and the volatile memory device DDR is in an idle state, at which time the memory device 100 may utilize the high bandwidth and large capacity of the DDR to quickly complete garbage collection, bad block management, and so on.

For example, when the UFS device is performing garbage collection, the effective data in the garbage block to be garbage collected in the UFS device may be first transferred to the partial storage area of the DDR, and after the UFS device completes the erasing operation on the data in the garbage block, the effective data cached in the DDR may be stored in the designated storage block in the UFS device.

For another example, when the UFS device is doing bad block management, a partial storage area in the DDR may be used to replace the area where the bad block in the UFS device is located, and information in the bad block of the UFS device is transferred to the target storage area of the DDR.

It will be appreciated that the partial memory area in the DDR may be a designated memory area or a random write memory area, and is not limited herein.

In some embodiments, when the host is in the normal power consumption mode, the third memory controller is turned on, and the third memory controller can be used to interact with the nonvolatile memory device to complete garbage collection, bad block management and other tasks.

In the embodiment of the disclosure, the memory device is coupled with the volatile memory device, and the host is respectively coupled with the memory device and the volatile memory device, so that the host and the memory device can be accessed to the volatile memory device in a time-sharing manner, and the utilization rate of the volatile memory device can be improved.

In some embodiments, a preset value may be set for the bandwidth ratio of the host to the volatile memory device LPDDR5, and when the bandwidth ratio of the host to the LPDDR5 is equal to or less than the preset value, it may be considered that the performance of the LPDDR5 is not fully exerted at this time. The preset value may be 30% or 40%. This value may be set by the user or may be set by default before shipment. When the bandwidth duty ratio of the host to the LPDDR5 is less than or equal to a preset value, the UFS device and the host may be allowed to interact with the LPDDR5 at the same time.

In some embodiments, the host, UFS device, and LPDDR5 may comprise a cell phone. When the characteristics of an application program used by the mobile phone are simpler, for example, only basic data storage and reading operations are needed, the bandwidth ratio of the host to the LPDDR5 is smaller than or equal to a preset value, and at the moment, the UFS device can utilize a part of DDR memory to improve the data storage and reading operations.

In some embodiments, when the bandwidth duty cycle of the host to LPDDR5 is greater than a preset value, LPDDR5 may be deemed no longer suitable for interacting with UFS devices at this time, and LPDDR5 may be inhibited from receiving an interaction request from UFS. UFS devices are not allowed to interact with DDR when the handset is using large or multiple applications.

In the embodiment of the disclosure, under the condition that the bandwidth occupied by the host to the volatile memory device is smaller, the storage equipment and the host can interact with the volatile memory device at the same time, so that the utilization rate of the volatile memory device is improved.

In some embodiments, the storage areas in LPDDR5 may be partitioned, with a first storage area for interaction with a host and a second storage area for interaction with a storage device. In this way, the host and UFS devices can interact with the LPDDR5 at the same time and without interfering with each other.

In some embodiments, the intuitive benefit brought by the high-capacity LPDDR5 in the mobile phone is an increase in the number of background applications, but in practical applications, the space of the high-capacity LPDDR5 is difficult to be fully used, and at this time, the UFS device may use a portion of the DDR memory as a buffer area, thereby improving the read/write speed.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is merely a logical function division, and there may be additional divisions of actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described as separate components may or may not be physically separate, and components displayed as units may or may not be physical units, may be located in one place or distributed on a plurality of network units, and may select some or all of the units according to actual needs to achieve the purpose of the embodiment.

In addition, each functional unit in each embodiment of the disclosure may be integrated in one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of hardware plus a form of software functional unit.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A memory system, comprising:

Storage device and volatile memory device; wherein,

The storage device includes a non-volatile memory device, a first memory controller coupled to the non-volatile memory device, and a first interface; the first memory controller is configured to control the non-volatile memory device; the volatile memory device includes a second interface; the second interface is coupled to the first interface so that the storage device can interact with the volatile memory device.

2. The memory system according to claim 1 is characterized in that the volatile memory device includes a double data rate synchronous dynamic random access memory; and the storage device includes a universal flash memory and an embedded multimedia card.

3 . The memory system according to claim 1 , wherein the storage device and the volatile memory device are packaged on the same substrate.

4. The memory system according to claim 2, wherein the first interface comprises a first clock signal pin area, a first power signal pin area, a first command address signal pin area, and a first data pin area; the second interface comprises a second clock signal pin area, a second power signal pin area, a second command address signal pin area, and a second data pin area;

The first clock signal pin area is coupled to the second clock signal pin area; the first power signal pin area is coupled to the second power signal pin area; the first command address signal pin area is coupled to the second command address signal pin area; and the first data pin area is coupled to the second data pin area.

5. An electronic device, characterized in that it comprises the memory system as described in any one of claims 1 to 4, and a host; the host comprises a second memory controller and a third memory controller, the second memory controller is coupled to the storage device, and the third memory controller is coupled to the volatile memory device.

6 . The electronic device according to claim 5 , wherein the third memory controller comprises a third interface; and the third interface is coupled to the second interface.

7. The electronic device according to claim 5, characterized in that the third memory controller includes a third interface, the volatile memory device further includes a fourth interface; and the third interface is coupled to the fourth interface.

8. The electronic device according to claim 5, characterized in that the volatile memory device comprises a plurality of modules; the first interface and the second interface further comprise mutually coupled function signal pin areas, the function signal pin areas comprising a first chip select signal pin and a second chip select signal pin;

The first chip select signal pin in the second interface is configured to receive a first chip select signal; the volatile memory device is configured to operate a specified module among the plurality of modules according to the first chip select signal;

The second chip select signal pin in the second interface is configured to receive a second chip select signal; the volatile memory device is configured to select to interact with the third memory controller or the storage device according to the second chip select signal.

9. A method for operating a memory system, comprising:

Based on the storage device being coupled to the volatile memory device, the storage device interacts with the volatile memory device; the storage device includes a non-volatile memory device and a first memory controller coupled to the non-volatile memory device.

10. A method for operating an electronic device, comprising:

Based on the volatile memory device being coupled to both the host and the storage device, the volatile memory device interacts with the host and/or the storage device.

11. The operating method according to claim 10, wherein the host comprises a second memory controller and a third memory controller; the second memory controller is coupled to the storage device, and the third memory controller is coupled to the volatile memory device;

The volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and/or the storage device, including:

When the third memory controller is in a closed state, the volatile memory device interacts with the storage device;

When the third memory controller is in an on state, the volatile memory device interacts with the host.

12. The operating method according to claim 10, characterized in that the volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and/or the storage device, comprising:

When the bandwidth share of the host to the volatile memory device is less than or equal to a preset value, the volatile memory device interacts with the host and the storage device;

When the bandwidth proportion of the host to the volatile memory device is greater than a preset value, the volatile memory device interacts with the host.

13. The operating method according to claim 10, characterized in that the volatile memory device is coupled to both a host and a storage device, and the volatile memory device interacts with the host and/or the storage device, comprising:

A first storage area in the volatile memory device interacts with the host, and a second storage area in the volatile memory device interacts with the storage device.