CN119829481A - Page configuration method, DDR controller and system on chip - Google Patents
Page configuration method, DDR controller and system on chip Download PDFInfo
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Abstract
本申请涉及内存管理技术领域，公开了一种页面配置方法、DDR控制器及片上系统，其中，所述方法包括：命令队列将待处理的读写请求的地址信息发送至监测模块；监测模块基于接收到的地址信息，确定命令队列中读写请求的行冲突率，将行冲突率发送至仲裁模块；仲裁模块将接收到的行冲突率与预设的条件阈值进行匹配，并根据匹配结果表征的行冲突率区间生成页面配置策略，并将页面配置策略下发至寄存器；寄存器执行页面配置策略，将页面配置策略表征的配置参数传递至命令队列中，以使得命令队列中的读写请求按照配置参数进行处理。本申请提供的技术方案，通过优化Bank管理策略来降低系统功耗、提升系统性能，从而提供更加高效的页面配置策略。
The present application relates to the field of memory management technology, and discloses a page configuration method, a DDR controller, and an on-chip system, wherein the method comprises: the command queue sends the address information of the read and write requests to be processed to the monitoring module; the monitoring module determines the row conflict rate of the read and write requests in the command queue based on the received address information, and sends the row conflict rate to the arbitration module; the arbitration module matches the received row conflict rate with the preset condition threshold, and generates a page configuration strategy according to the row conflict rate interval represented by the matching result, and sends the page configuration strategy to the register; the register executes the page configuration strategy, and passes the configuration parameters represented by the page configuration strategy to the command queue, so that the read and write requests in the command queue are processed according to the configuration parameters. The technical solution provided by the present application reduces system power consumption and improves system performance by optimizing the Bank management strategy, thereby providing a more efficient page configuration strategy.
Description
Technical Field
The present application relates to the field of memory management technologies, and in particular, to a page configuration method, a DDR controller, and a system on a chip.
Background
In modern computer systems, the memory controller is responsible for managing and allocating memory resources, and is a bridge connecting the CPU and DDR sdram (DoubleDataRateSDRAM, double-rate synchronous dynamic random access memory), and one of the main tasks is to manage pages of the DDR memory subsystem.
In practical application, when data is read and written, a common page switching strategy of the memory controller has fixity, if the access behavior changes in the application running process, the strategy cannot be adjusted in time, and the loading time is overlong or page conflict is easy to occur, so that the overall performance is influenced. In addition, when the number of banks in the memory system is large, page management is complex, which easily results in low memory access efficiency or increases system power consumption.
In view of this, how to implement more efficient page allocation policies in terms of memory access is the focus of current research.
Disclosure of Invention
The application provides a page configuration method, a DDR controller and a system on a chip, which can provide a more efficient page configuration strategy.
The first aspect of the application provides a page configuration method which is applied to a DDR controller, the DDR controller comprises a command queue, a monitoring module, an arbitration module and a register, the command queue is used for storing a read-write request to be processed, the method comprises the steps that the command queue sends address information of the read-write request to be processed to the monitoring module, the monitoring module determines the line conflict rate of the read-write request in the command queue based on the received address information and sends the line conflict rate to the arbitration module, the arbitration module matches the received line conflict rate with a preset condition threshold, a page configuration strategy is dynamically generated according to a line conflict rate interval represented by a matching result, and the page configuration strategy is issued to the register, wherein the generated page configuration strategy is at least used for representing an open page strategy or a close page strategy, the line conflict rate under the open page strategy is lower than the line conflict rate under the close page strategy, and the register executes the page configuration strategy and transmits the page configuration strategy to a command queue to enable the read-write request to be processed according to the command queue.
According to the technical scheme provided by the embodiment of the application, the page configuration strategy can be generated according to the address information of the read-write request, and the page configuration is dynamically carried out. Firstly, obtaining address information of a read-write request in a command queue containing the read-write request, calculating a row conflict rate of the read-write request according to the address information, dynamically generating an adaptive page configuration strategy according to a section of the row conflict rate, and finally dynamically configuring a page of a memory according to the page configuration strategy. Therefore, by adopting the technical scheme provided by the embodiment of the application, page configuration can be dynamically carried out, so that the power consumption of a memory system is reduced by adopting a page closing strategy when the line conflict rate is high, the request delay is reduced and the system performance is improved by adopting an page opening strategy when the line conflict rate is low, and meanwhile, the page opening time is dynamically adjusted, so that a more efficient page configuration strategy is provided.
In a possible implementation manner, the preset condition threshold comprises a first threshold and a second threshold, and the dynamic generation of the page configuration strategy according to the line conflict rate interval represented by the matching result comprises the steps of generating a retention strategy representing maintaining the original page configuration strategy if the line conflict rate interval represented by the matching result is larger than the first threshold and smaller than the second threshold, generating an opening page strategy representing disabling the automatic precharge function if the line conflict rate interval represented by the matching result is smaller than or equal to the first threshold, and generating a closing page strategy representing enabling the automatic precharge function if the line conflict rate interval represented by the matching result is larger than or equal to the second threshold.
The technical scheme provided by the embodiment of the application refines the generation process of the page configuration strategy, and particularly relates to comparison of the line conflict rate and a plurality of threshold intervals. The interval where the line conflict rate is located can be accurately divided by using a preset condition threshold value, and then a matched page configuration strategy is generated.
In a possible implementation mode, the DDR controller further comprises a Bank resource management module, the method further comprises the step that the command queue sends target address information of a target read-write request to be processed currently to the Bank resource management module, and the Bank resource management module allocates Bank resources for the target read-write request according to the target address information and activates a target page represented by the Bank resources.
According to the technical scheme provided by the embodiment of the application, the bank resource is allocated to the target read-write request to be processed through the bank resource management module, and the corresponding target page is activated. The method introduces a bank resource management module, thereby optimizing the allocation management and page management of the bank resources.
In one possible implementation, the Bank resource management module configures a threshold counter for the target page in advance, a designated value is preloaded in the threshold counter, after the target page is activated and started, the method further comprises gradually decrementing the designated value, when the designated value is decremented to a fixed value, the Bank resource management module closes the target page, and loads a new value in the threshold counter, wherein after a new page is activated and started, the new value is gradually decremented, and when the new value is decremented to a fixed value, the Bank resource management module closes the new page.
According to the technical scheme provided by the embodiment of the application, after the target page is activated and started, the threshold counter is used for managing the duration of the target page. The threshold counter is utilized, so that the page can be ensured to be kept in an open state in the processing process of the read-write request, and meanwhile, the page can be ensured to be closed in time after being opened, further, the time length management of the target page is optimized, the unnecessary opening time length of the page is avoided, and the system power consumption and the resource occupation are reduced.
In one possible implementation, the specified value loaded in the threshold counter is determined by setting the specified value to a first value if the row collision rate is greater than a first threshold and less than a second threshold, setting the specified value to a second value if the row collision rate is less than or equal to the first threshold, setting the specified value to a third value if the row collision rate is greater than or equal to the second threshold, wherein the third value is less than the first value and the first value is less than the second value.
The technical scheme provided by the embodiment of the application further describes the setting mode of the appointed numerical value in the threshold counter. According to the different line conflict rates, the appointed numerical value is dynamically adjusted, when the line conflict rate times of the read-write request are more, the page opening time is reduced, so that access to new lines can be quickened, access delay caused by the line conflict rate is reduced, under the condition that the line conflict is frequent, the system can switch the lines frequently, therefore, the opening time is shortened, the access efficiency of a memory can be improved, performance loss caused by waiting is reduced, and meanwhile, the energy consumption is also possibly reduced. Under the condition of low line conflict rate, the system can normally access the data of the same line smoothly, and the page opening time is prolonged to enable more accesses to hit the same line, so that repeated line switching is reduced, and the efficiency of memory access is improved.
In one possible implementation, after allocating a Bank resource to the target read-write request, the method further includes, for other read-write requests except the target read-write request in the command queue, if address information of the other read-write requests characterizes that the other read-write requests are located in a same row of a same Bank as the target read-write request, marking the other read-write requests as ready-to-issue state by the Bank resource management module, wherein the read-write requests marked as ready-to-issue state in the command queue are issued continuously if a preset timing requirement is met.
The technical scheme provided by the embodiment of the application describes that the requests positioned in the same row of the same Bank can be marked as a preparation state, so that the requests can be continuously sent out in the follow-up process. Aiming at read-write requests which are located in the same Bank and are in the same row, the read-write requests can be continuously sent out under the condition of meeting DDR time sequence requirements, so that the delay of a switch page is reduced, the system consumption caused by the switch page is also reduced, and the processing efficiency of the read-write requests is improved.
In one possible implementation, after allocating a Bank resource to the target read-write request, the method further includes if the target read-write request and a previous read-write request are located in different rows of the same Bank, the Bank resource management module issues a precharge command and an activate command to reopen a target page corresponding to the target read-write request.
The technical scheme provided by the embodiment of the application describes that if the read-write requests are located in different rows of the same Bank, the read-write requests of the different rows can be normally processed by the precharge command and the activation command and then re-opened after closing the page.
In one possible implementation, the monitoring module determines a row conflict rate of the read-write requests in the command queue based on the received address information, wherein the monitoring module counts the total number of requests of the read-write requests to be processed in the command queue, the monitoring module traverses adjacent first read-write requests and second read-write requests in the read-write requests to be processed, compares the first address information of the first read-write requests and the second address information of the second read-write requests, obtains an address comparison result, and determines the ratio of the accumulated row conflict number to the total number of requests as the row conflict rate of the read-write requests in the command queue when the address comparison result represents that the first read-write requests and the second read-write requests are located in the same BankGroup and the same Bank and are located in different rows.
According to the technical scheme provided by the embodiment of the application, the row conflict rate can be calculated according to the address information of the read-write request. By comparing addresses of any adjacent read-write requests, read-write requests which are positioned in the same Bank but are in different rows are determined, and then the row conflict rate can be accurately calculated.
The DDR controller comprises a command queue, a monitoring module, an arbitration module and a register, wherein the command queue is used for storing a read-write request to be processed and sending address information of the read-write request to be processed to the monitoring module, the monitoring module is used for determining the line conflict rate of the read-write request in the command queue based on the received address information and sending the line conflict rate to the arbitration module, the arbitration module is used for matching the received line conflict rate with a preset condition threshold, dynamically generating a page configuration strategy according to a line conflict rate interval represented by a matching result and sending the page configuration strategy to the register, the generated page configuration strategy is at least used for representing an open page strategy or a close page strategy, the line conflict rate under the open page strategy is lower than the line conflict rate under the close page strategy, and the register is used for executing the page configuration strategy and transmitting the configuration parameter represented by the page configuration strategy to the command so that the read-write request of the command queue is processed according to the command queue.
The third aspect of the present application provides a system on a chip, where the system on a chip includes a DDR controller, a processor core, and a memory, where the processor core is configured to process an instruction obtained by the DDR controller from the memory, and write a processing result into the memory through the DDR controller, and the DDR controller is configured to execute the page configuration method described above on the memory.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram illustrating steps of a page configuration method according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating steps of a method for determining a row collision rate according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating a method for configuring a page according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a strategy for adaptively adjusting page opening time according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating steps of a page configuration method according to another embodiment of the present application;
FIGS. 6 (a) to (d) are timing waveforms of various access commands according to one embodiment of the present application;
FIG. 7 is a schematic diagram of a DDR controller according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a system-on-chip according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more. In addition, the use of "based on" or "according to" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" or "according to" one or more of the stated conditions or values may in practice be based on additional conditions or beyond the stated values.
The DDR memory module is composed of a plurality of memory chips, each chip is provided with an independent memory unit, and the memory units are arranged according to a certain hierarchical structure, and are sequentially channel (memory channel), DIMM (dual in-line memory module), rank (memory Bank), chip (chip), bank (memory Bank), row (column), and generally speaking, one channel may correspond to one DDR controller. Each memory cell is provided with a unique address for addressing during data read and write operations. Taking DDR5 as an example, a DDR5 chip includes a plurality of independent Bank regions, each of which has an independent row address decoder and column address gate, and by selecting different banks, a plurality of memory regions can be accessed in parallel, thereby improving the efficiency of data access. In addition, in DDR4 and DDR5, a BankGroup (Bank group) concept is introduced to facilitate the Bank management. One DDR chip may have a plurality of BankGroup and one BankGroup includes a plurality of banks.
It should be noted that, since the SDRAM has an exclusive address, if another row in the same Bank is addressed after performing a read/write operation, the original valid row is first closed and the required row is re-activated. If the two read and write operations are on different rows of the same BankGroup, the same Bank, this situation may be referred to as a row conflict.
Generally, different page policies are employed in memory management to optimize data access efficiency and latency. The page closing strategy is understood to be that once the data access to a certain row is completed, the memory controller immediately closes the row, so that the required row needs to be activated again when the data is accessed, and the strategy can avoid row conflict, so that the data access becomes more stable and predictable, but a certain time access delay is caused. The page opening policy may be understood as that the memory controller maintains an open state of a row of data in the Bank for a period of time, if consecutive memory access requests are all in the same row, these accesses will not need to reactivate the row compared with the page closing mode, so as to avoid access delay, but if the access requests are not in the same row, a row conflict situation may be caused, at this time, the data of the last valid row needs to be written back and closed, then the next required row is opened, and in this case, the read-write data delay is the greatest, which increases the access time and the system power consumption.
In the prior related art, page strategies can be statically allocated by monitoring the concentration of access behavior information. However, the mode has poor adaptability, and if the access behavior changes in the running process of the application, the strategy cannot be adjusted in time, so that the system power consumption is easy to increase. In addition, in some memory systems, if the number of banks is large, the access efficiency is easily reduced due to improper management of the activated banks, and additional hardware resources and time are required for monitoring and analyzing the memory behavior information, which increases the burden of the system.
In view of the foregoing, one or more embodiments of the present application provide a page configuration method, a DDR controller and a system on a chip, which can solve the above-mentioned problems, reduce power consumption of a memory system and improve performance of the memory system by optimizing a Bank management policy.
Referring to fig. 1, an embodiment of the present application provides a page configuration method, which is applied to a DDR controller, where the DDR controller includes a command queue, a monitoring module, an arbitration module, and a register, the command queue is used for storing a read/write request to be processed, and the method may include the following steps:
s1, the command queue sends the address information of the read-write request to be processed to the monitoring module.
Specifically, the command queue is an important component of memory management, and is responsible for storing and scheduling read-write requests. The command queue stores a plurality of entries, each entry can store a read-write request to be processed to wait for access operation, and the number of the entries in the command queue represents the maximum number of the requests which can be stored in the command queue.
In this embodiment, the DDR controller is responsible for connecting the CPU and the DDR memory unit, and generates a control signal to manage read/write operations. The DDR controller receives one or more read-write requests from the CPU and generates a corresponding command sequence.
The address information of the read/write request is understood to be the location information of the storage area to which the read/write request needs to access. In DDR memory modules, each memory cell is provided with a unique address for addressing during data read and write operations. Therefore, before addressing, bankGroup, bank, row, column of the memory area to be accessed corresponding to the request needs to be determined.
And S3, the monitoring module determines the row conflict rate of the read-write request in the command queue based on the received address information, and sends the row conflict rate to the arbitration module.
The above-mentioned line collision rate can be understood as the probability of occurrence of a line collision condition in one command queue. In a command queue, if there are two adjacent read-write requests with address information in the same BankGroup and different rows in the same Bank, a row conflict situation is considered to happen.
After determining the row conflict rate of the read-write request in the command queue, the row conflict rate may be sent to an arbitration module to dynamically generate a matched page configuration policy through the arbitration module.
And S5, the arbitration module matches the received row conflict rate with a preset condition threshold, dynamically generates a page configuration strategy according to a row conflict rate interval represented by a matching result, and transmits the page configuration strategy to the register, wherein the generated page configuration strategy is at least used for representing an open page strategy or a close page strategy, and the row conflict rate under the open page strategy is lower than the row conflict rate under the close page strategy.
In this embodiment, the page configuration policies include an open page policy and a close page policy, and the value of the line conflict rate is compared with a preset condition threshold value to determine the page configuration policy matched with the current memory system. When the row conflict rate is low, the probability that the row address information of continuous read-write requests is in the same row is high, the open state of the row in the Bank can be kept for a period of time by adopting the page opening strategy, the row does not need to be activated again, so that the request delay is reduced, and conversely, when the row conflict rate is high, the probability that the row address information of continuous read-write requests is in the same row is low, the extra access time can be avoided by adopting the page closing strategy, and the power consumption of the system is reduced.
In one possible implementation manner, the preset condition threshold includes a first threshold and a second threshold, the first threshold and the second threshold are matched according to the value of the line conflict rate, and the corresponding page configuration strategy is generated according to the line conflict rate interval represented by the matching result. The method comprises the steps of determining whether a section where a row conflict rate is located is larger than a first threshold value and smaller than a second threshold value, wherein an original page configuration strategy is adopted by a page configuration strategy at the moment, generating an open page strategy representing disabling an automatic precharge function if the section where the row conflict rate is located is smaller than or equal to the first threshold value, and generating a close page strategy representing enabling the automatic precharge function if the section where the row conflict rate is located is larger than or equal to the second threshold value.
The precharge is understood as an operation of turning off an existing operation line of one Bank. In practice, the precharge is performed to rewrite data of all the banks in the working row and reset the row address, so that the precharge operation is performed between two consecutive read-write request operations commonly used in the page-closing policy to write back the data of the last valid row and close the last valid row. The precharge may be controlled by a command or by an auxiliary setting to allow the chip to be automatically precharged after each read and write operation.
It should be noted that, when the page opening policy is adopted, the conflict rate of the requested row in the command queue is low, and the precharge operation is not required to be performed every time of memory access, so that the disabling of the auto precharge function can avoid excessive energy consumption of the system. When the page closing strategy is adopted, the conflict rate of the requested row in the command queue is higher, the precharge operation is required to be frequently carried out and the next row is required to be opened again, and the automatic precharge function can avoid causing extra access time.
And S7, the register executes the page configuration strategy and transmits configuration parameters represented by the page configuration strategy to the command queue so that the read-write request in the command queue is processed according to the configuration parameters.
In this embodiment, after the register is configured according to a specific page configuration policy, the register will transfer the configuration parameters to the command queue. After receiving the read-write requests from the processor, the command queue processes the requests according to the configuration parameters transferred in the register. The configuration parameters may include auto-precharge parameters, and the read-write requests in the command queue are configured with auto-precharge signals prior to access. In the command queue, the configuration operation and the memory management strategy of the system are ensured to be consistent, and the overall memory access performance can be optimized.
Illustratively, when an open page policy is employed, the register module configures the corresponding parameter to disable auto-precharge and passes the parameter to the command queue, thereby disabling auto-precharge for each read-write request. When the page closing strategy is adopted, the register module configures corresponding parameters for enabling automatic precharge and transmits the parameters to the command queue, so that the automatic precharge of each read-write request is enabled.
Referring to fig. 2, in one embodiment, based on the step S3, the monitoring module determines a line collision rate of the read/write request in the command queue based on the received address information, where the method for determining the line collision rate is performed according to the following steps:
S31, the monitoring module counts the total number of the read-write requests to be processed in the command queue;
S33, traversing adjacent first read-write requests and second read-write requests in the read-write requests to be processed by the monitoring module, and comparing first address information of the first read-write requests with second address information of the second read-write requests to obtain an address comparison result;
s35, accumulating row conflict times when the address comparison result represents that the first read-write request and the second read-write request are located in the same BankGroup, the same Bank and in different rows;
And S37, determining the ratio of the accumulated line conflict times to the total number of the requests as the line conflict rate of the read-write requests in the command queue.
In this embodiment, the above-mentioned line collision rate is a ratio of the number of times of accumulated line collisions occurring in the command queue to the total number of all the read/write requests to be processed. The total number of the read-write requests can be counted by the monitoring module. Specifically, the monitoring module reads item information contained in the command queue, identifies a occupation identifier representing a read-write request in the item information, and can determine the total number of the read-write requests to be processed contained in the command queue by counting the number of the occupation identifiers, wherein one read-write request corresponds to one occupation identifier. According to the technical scheme provided by the embodiment, whether the read-write request exists in the entry of the command queue is represented by the entry information, so that the total number of the requests is counted rapidly and accurately.
Illustratively, the valid value of the full_list signal is used as the occupancy flag. Each entry in the command queue has a full_list signal built in, and if a request is placed in the current entry, the full_list signal value of the entry becomes valid, thus indicating that a read/write request is detected whenever a valid value of a full_list signal is detected. Conversely, if the full_list signal in the current entry is a non-valid value, it represents that there is no read-write request in the current entry. In one specific application example, the full_list signal value may be set by a pull-up level, which may correspond to a valid value, or a pull-down level, which may correspond to a non-valid value.
In this embodiment, by comparing address information of adjacent read/write requests, whether a line collision occurs is determined, and the number of times of line collision occurrence is counted in the command queue. Whether the row conflict occurs or not can be judged by the monitoring module. Specifically, the monitoring module obtains address information of a first read-write request and a second read-write request adjacent to each other in the command queue, wherein the address information comprises a Bank group identifier, a Bank identifier and a row identifier, wherein the Bank group identifier represents BankGroup address information of the read-write request, the Bank identifier represents Bank address information of the read-write request and row address information of the row identifier represents the read-write request. Comparing the first address information of the first read-write request with the second address information of the second read-write request, if the first read-write request and the second read-write request are located in the same BankGroup, the same Bank and different row, namely, the Bank group identification representing the first address information and the second address information is consistent with the corresponding Bank identification, but the row identification is inconsistent, the first read-write request and the second read-write request indicate that a row conflict occurs. And sequentially judging whether the adjacent read-write requests in the command queue generate row conflict or not, and accumulating the times of the row conflict. According to the technical scheme provided by the embodiment, the three elements in the address information are compared one by one, so that requests which are located in the same Bank but in different rows can be accurately determined, and the number of times of row conflict is counted.
Alternatively, a counter may be used to count the number of row collisions and the total number of requests. The monitoring module is configured with a first counter and a second counter, the first counter is used for counting the total number of requests, and if one occupation mark is detected, the first counter is automatically incremented. The second counter is used for accumulating the number of row conflict times, and if judging that the adjacent read-write requests generate row conflict, the second counter is automatically increased by one. Therefore, the counter is used for counting the total number of requests and the number of row conflicts, and the method is more convenient and accurate.
In view of this, the technical solution provided in this embodiment of the present application performs address comparison for any adjacent read/write request, so as to determine requests located in the same BankGroup, the same Bank but different rows, and accurately calculate the row conflict rate, and by using a preset condition threshold, the interval where the row conflict rate is located can be accurately divided, so as to generate a matched page configuration policy.
In one embodiment, the DDR controller further includes a Bank resource management module, and further performs Bank resource management after the step S7. In practical applications, the number of banks may be large, and it is difficult for the DDR controller to control all banks, so that Bank resource management is required, and the DDR controller manages the banks in an active state to improve the command processing efficiency.
In the embodiment, a command queue sends target address information of a target read-write request to be processed currently to the Bank resource management module, and the Bank resource management module allocates Bank resources for the target read-write request according to the target address information and activates a target page represented by the Bank resources.
Specifically, the Bank resource management module allocates Bank resources for the target read-write request according to the target address information of the target read-write request. When the target Bank resource of the target read-write request is in an inactive state, the Bank resource management module allocates the corresponding Bank resource for the target read-write request and activates the target page. When the target Bank resource is in an activated state, after the last read-write request is required to be waited for completing read-write operation, the Bank resource management module allocates the target read-write request for the Bank, if the last read-write request and the target read-write request access the same row of the same BankGroup and the same Bank, the access operation is directly performed, and if the last read-write request and the target read-write request access the same BankGroup and different rows of the same Bank, the Bank resource management module needs to precharge and activate the target page represented by the Bank resource.
Further, after allocating the Bank resource to the target read-write request, the requests of the same row of the same Bank in the command queue are marked. Specifically, for other read-write requests except the target read-write request in the command queue, if there is the same row of the same BankGroup and the same Bank where the address information of the other read-write requests and the address information of the target read-write request are located, the Bank resource management module marks the other read-write requests as ready-to-issue status, and the read-write requests marked as ready-to-issue status in the command queue can be issued continuously under the condition of meeting the preset time sequence requirement.
Further, after allocating a Bank resource to a target read-write request, if the target read-write request and a previous read-write request are located in different rows of the same BankGroup and the same Bank, the Bank resource management module issues a precharge command and an activate command to reopen a target page corresponding to the target read-write request.
In this embodiment, the Bank resource management module configures a threshold counter for the target page in advance, and after the target page is activated and started, the threshold counter is used to perform the start duration management. The threshold counter is utilized, so that the page can be ensured to be kept in an open state in the processing process of the read-write request, and meanwhile, the page can be ensured to be closed in time after being opened, and further, the system power consumption and the resource occupation are reduced.
Specifically, a specified value is preloaded in the threshold counter, the specified value is gradually decreased after the target page is activated and opened, and when the specified value is decreased to a fixed value, the Bank resource management module closes the target page and preloads a new specified value in the threshold counter. After a new page is activated and opened, the new designated value is gradually decreased, and when the new value is decreased to a fixed value, the Bank resource management module closes the new page. Further, the specified value loaded in the threshold counter is determined as follows:
If the row conflict rate is larger than a first threshold value and smaller than a second threshold value, setting the appointed numerical value as a first numerical value; if the row conflict rate is smaller than or equal to the first threshold value, setting the appointed numerical value as a second numerical value;
And if the row conflict rate is greater than or equal to the second threshold value, setting the appointed numerical value as a third numerical value, wherein the third numerical value is smaller than the first numerical value, and the first numerical value is smaller than the second numerical value.
Based on the thought, the size of the appointed numerical value loaded in the threshold counter is dynamically adjusted according to the size of the row conflict rate, the appointed numerical value is sequentially a third numerical value, a first numerical value and a second numerical value, and the opening time of the page is dynamically adjusted by adjusting the size of the appointed numerical value. When the number of line conflicts of the read-write request is relatively large, the page opening time is reduced, so that access to new lines can be quickened, access delay caused by line conflicts is reduced, meanwhile, energy consumption is reduced, and the controller is prevented from being in a high-power consumption state in a waiting period for a long time.
For example, in the case of high row conflict rates, the system needs to switch rows frequently, so shortening the open time can improve the access efficiency of the memory and reduce the performance loss due to waiting. Under the condition of low line conflict rate, the system often needs to access the data of the same line, so that the page opening time is prolonged to enable more accesses to hit the same line, repeated line switching is reduced, and the efficiency of memory access is improved.
According to the technical scheme provided by the embodiment of the application, a Bank resource management module is introduced and is responsible for carrying out Bank resource allocation and Bank resource activation and management on the target read-write request, so that the allocation management and page management of the Bank resource are optimized, and the command processing efficiency is improved. Meanwhile, aiming at the read-write requests of the same row positioned in the same BankGroup and the same Bank, the read-write requests can be continuously sent out under the condition of meeting DDR time sequence requirements, thereby reducing the delay of a switch page, reducing the system consumption caused by the switch page and improving the processing efficiency of the read-write requests.
Based on the above-mentioned thought, the technical solution provided by one or more embodiments of the present application can generate a page configuration policy according to address information of a read-write request, and dynamically perform page configuration. Firstly, obtaining address information of a read-write request in a command queue containing the read-write request, calculating a row conflict rate of the read-write request according to the address information, generating an adaptive page configuration strategy according to the numerical value of the row conflict rate, and finally dynamically configuring a page of a memory according to the page configuration strategy. Therefore, by adopting the technical scheme provided by one or more embodiments of the application, page configuration can be dynamically carried out, so that the power consumption of a memory system is reduced by adopting a page closing strategy when the row conflict rate is high, and the request delay is reduced and the system performance is improved by adopting an page opening strategy when the row conflict rate is low, thereby providing a more efficient page configuration strategy.
Referring to fig. 3, the present application provides an embodiment of applying the above-mentioned page configuration method, which is implemented according to the following steps:
Step S101, a command queue in the DDR controller sends address information of a read-write request in the command queue to a monitoring module;
Step S103, the monitoring module receives the address information of the read-write request sent by the command queue and identifies the Bank Group, the Bank and the row address information in the command queue, and meanwhile, the monitoring module is provided with two counters, wherein the first counter is used for counting the total request times in the command queue, and the second counter is used for counting the times of line conflict in the command queue. And the monitoring module calculates the travel conflict rate according to the number of the row conflicts and the total request number and sends the travel conflict rate to the arbitration module.
In this embodiment, the monitoring module counts the total number of requests of the command queue, and when a full_list signal is identified, the total number of requests of the first counter is incremented by one. Specifically, the command queue includes a plurality of item information, each item information includes a full_list signal, when a request exists in the corresponding item information, the corresponding bit of the full_list signal in the item is pulled up, each full_list signal with one pulled up bit, and the first counter is incremented, so that the total request times in the command queue are determined.
In this embodiment, the monitoring module counts the number of times of line collision in the command queue, and when BankGroup addresses of address information of two adjacent requests in the command queue are the same as the Bank address and the row address are different, the number of times of the second counter is increased by one. And traversing each two adjacent requests in the command queue in turn, and determining the number of times of line conflict in the command queue.
Further, a line conflict rate is determined based on the total number of requests and the number of line conflicts in the command queue. Specifically, the line collision rate is the ratio of the number of line collisions to the total number of requests.
Step 105, the arbitration module judges whether the row conflict rate sent by the monitoring module meets the preset condition, so as to determine the configured page strategy.
In one implementation manner of this embodiment, if the row conflict rate meets the preset condition 1, that is, the row conflict rate calculated by the monitoring module is greater than the first threshold and less than the second threshold, the register module maintains the original configuration unchanged, that is, maintains the original page policy.
In one implementation manner of this embodiment, if the row conflict rate meets the preset condition 2, that is, the row conflict rate calculated by the monitoring module is smaller than the first threshold, the automatic precharge function of each command is disabled and the page strategy of opening the page is adopted. Specifically, the register module configures the corresponding parameter regarding auto-precharge, disables the auto-precharge function, and sends the parameter to the command queue module. When the row conflict rate is low, the time for re-opening the page without row conflict can be saved by disabling the automatic precharge function, so that the parameter of automatic precharge is configured for the request in the command queue, and the memory access efficiency can be improved.
In one implementation manner of this embodiment, if the row conflict rate meets the preset condition 3, that is, the row conflict rate calculated by the monitoring module is greater than the second threshold, the auto-precharge function of each command is enabled and a page-closing policy is adopted. Specifically, the register module configures the corresponding parameter regarding auto-precharge, enables the auto-precharge function and sends the parameter to the command queue.
In addition, referring to fig. 4, in the page-opening page policy, each page is provided with a threshold counter and a judgment logic for adaptively adjusting the page-opening time to meet different memory requirements. Specifically, the open page counter loads a threshold, the setting of which is determined by the line conflict rate in the DDR controller command queue, which is suitably decreased when the line conflict rate is too high, and is suitably increased when the line conflict rate is too low. When the page is opened, the threshold value is gradually decreased, and when the page is decreased to a fixed value, the opened page is closed, and a new initial threshold value is loaded in the counter for counting again. And dynamically adjusting the size of the threshold according to the size of the row conflict rate, so that the page opening time is adaptively adjusted, and the efficiency of memory access is improved. The line buffer sensitive amplifier is understood to be a page for reading and writing corresponding data.
In this embodiment, when the DDR controller issues a refresh request, an enable signal is sent to the determination logic at the same time, closing the corresponding open page and reloading the initial threshold in the counter to re-count at the next page open. It should be noted that the DDR controller needs to periodically perform a refresh operation on all the working rows in the Bank to retain the data in the memory cells. In practical applications, the currently accepted refresh rate is equal to the number of rows/64 ms, and the refresh command is valid for one row at a time, so the time interval for the refresh signal transmission varies with the total number of rows.
Referring to fig. 5, the present application provides another embodiment, which configures a Bank resource management module and is applied to the above-mentioned dynamic page management policy method, and the embodiment is implemented according to the following steps:
Step 301, when the command queue receives a new read-write request, the command queue sends address information of the read-write request to a Bank resource management module.
Step S303, the Bank resource management module allocates resources for the corresponding banks according to the address information of the read-write request.
In one implementation of this embodiment, when the Bank resource corresponding to the new request command is not allocated, the Bank resource management module allocates the Bank resource for the command, and issues an activate command to open the row corresponding to the new command. And, the command in the command queue, which is the same as the address information of the new command, is marked as a ready state, so that the commands of the same page can be continuously sent out.
In one implementation of this embodiment, when the new request command corresponds to a Bank resource that has been allocated and is a command of the same row as the previous command, then access is continued directly after the last command access is completed.
In one implementation of this embodiment, when a new request command has allocated a Bank resource and a command that is a different row from a previous command, the DDR controller allocates the same Bank resource to the new command, and issues a precharge command and an activate command to reopen the row corresponding to the new command. And, the command in the command queue, which is identical to the address information of the new command, is marked as a ready state, and the commands of the same page can be continuously issued after the time sequence requirement is met.
And S305, after the Bank resources are allocated, recovering the resources.
Specifically, after the Bank resources are allocated, the resources are selectively reclaimed, including reclaiming the Bank resources that have been opened and that have no commands corresponding to the page in the command queue, reclaiming the Bank resources that are being refreshed, and reclaiming the Bank resources of the banks that have line conflicts.
In one implementation of this embodiment, the Bank resource management module may reclaim the allocated Bank resources. The allocated Bank resources are reclaimed, i.e. the opened pages are precharged and closed. And if the read-write instruction matched with the page does not exist in the command queue, recovering the Bank resources of the opened page, and recovering the corresponding Bank resources of the page with the line conflict. The method and the device can recycle the Bank resources in time, can accelerate the allocation process of the Bank resources of the subsequent requests, and improve the processing efficiency of the read-write requests.
Therefore, in the embodiment of the present application, the monitoring module of the DDR controller counts and calculates the line collision rate in the command queue, determines the preset condition corresponding to the line collision rate in the arbitration module, and determines and switches the corresponding page policy according to the determination result. Under the page opening strategy, the opening time of the corresponding page is adaptively adjusted according to the line conflict rate, so that the page is switched in real time, the capability of the system for coping with dynamic change of the access request is improved, and meanwhile, the power consumption of the memory system is reduced.
In one possible implementation, the DDR controller sends different commands to implement the above-mentioned method for configuring a page, including a refresh command, an activate command, a precharge command, and a read/write command, where the command truth table of the DDR controller is shown in table 1, and timing waveform diagrams of commands corresponding to the page management policy are shown in fig. 6 (a) to (d), specifically:
Table 1 Command truth table for DDR memory
As can be seen from Table 1, CKE is a clock enable signal, CS_n is a rank chip select enable signal, ACT_n is an active signal, RAS_n, CAS_n, WE_n are command input signals for determining the input code of the current command, BG0-BG1 are address select signals for determining BankGroup addresses, and BA0-BA1 are address select signals for determining Bank addresses. Where 'H' represents a high level and 'L' represents a low level, when an activate command is issued, act_n is at a low level, ras_n, cas_n, we_n are used as address lines, i.e., RA in the table, and ras_n, cas_n, we_n are used as command codes when act_n is at a high level.
Referring to fig. 6 (a) to (d), fig. 6 (a) is a timing waveform diagram of an access command, and fig. 6 (b), fig. 6 (c) and fig. 6 (d) are timing waveform diagrams of stage I, stage II and stage III in fig. 6 (a), respectively. The clock enable signal of the current page is always high, and illustratively, indicates that an activate command is issued when cs_n, act_n, ras_n, cas_n, we_n all go low. When cs_n, ras_n, we_n go low and act_n and cas_n go high, it means that a precharge command is issued. When cs_n and cas_n become low and act_n, ras_n, we_n become high, it means that one write command is issued.
In this embodiment, fig. 6 (b) characterizes phase I in fig. 6 (a), where the page adopts an open-page policy, and a precharge command is sent between two read-write requests. FIG. 6 (c) characterizes phase II of FIG. 6 (a), where the row conflict rate is high, the page adopts a closed page policy, and no precharge command needs to be sent, but an auto precharge command is configured. FIG. 6 (d) shows stage III in FIG. 6 (a), where the row conflict rate is low, the page adopts an open page policy, and the read/write requests can be sent continuously.
Therefore, in the embodiment of the application, the page policy is dynamically adjusted and switched according to the size of the row conflict rate, so that the capability of the system for coping with the dynamic change of the access request is improved, and meanwhile, the system power consumption is reduced, thereby providing a more efficient page management policy.
Referring to fig. 7, the present application further provides a DDR controller, the controller including a command queue, a monitoring module, an arbitration module, and a register, wherein:
The command queue is used for storing the read-write request to be processed and sending the address information of the read-write request to be processed to the monitoring module;
the monitoring module is used for determining the row conflict rate of the read-write request in the command queue based on the received address information and sending the row conflict rate to the arbitration module;
The arbitration module is used for matching the received row conflict rate with a preset condition threshold, dynamically generating a page configuration strategy according to a row conflict rate interval represented by a matching result, and issuing the page configuration strategy to the register, wherein the generated page configuration strategy is at least used for representing an open page strategy or a close page strategy, and the row conflict rate under the open page strategy is lower than the row conflict rate under the close page strategy;
The register is used for executing the page configuration strategy and transmitting configuration parameters represented by the page configuration strategy to the command queue so that read-write requests in the command queue are processed according to the configuration parameters.
In this embodiment, the command queue is specifically configured to process the read-write requests from the processor according to the configuration parameters transferred in the register after receiving the requests, store a plurality of entry information capable of storing the read-write requests to be processed, wait for an access operation, and send the address information of the read-write requests to be processed to the monitoring module.
In this embodiment, the monitoring module is specifically configured to receive address information of read-write requests from a command queue, count total number of requests of the read-write requests to be processed in the command queue, accumulate number of times of occurrence of line collision, calculate a line collision rate of the read-write requests in the command queue, and send the line collision rate to the arbitration module.
In this embodiment, the arbitration module is specifically configured to receive the line conflict rate calculated by the monitoring module, compare the line conflict rate with a preset condition threshold, determine a range of line conflict rates, and further determine a matched page configuration policy.
In this embodiment, the register module is specifically configured to perform page configuration according to a specified page configuration policy, and transfer configuration parameters to the command queue, where the configuration parameters may include auto-precharge parameters. The register is a storage device in the computer processor, and is used for storing instructions, data and addresses.
In one embodiment, the DDR controller further includes a Bank resource management module, where the Bank resource management module is configured to allocate a Bank resource for the target read/write request according to the target address information sent by the command queue, and activate a target page represented by the Bank resource.
In this embodiment, the command queue is further configured to send target address information of a target read-write request to be currently processed to the Bank resource management module.
Further functional descriptions of the above respective modules are the same as those of the above corresponding method embodiments, and are not repeated here.
Referring to fig. 8, the present application further provides a system on a chip, the system on a chip including a DDR controller, a processor core, and a memory, wherein:
the processor core is used for processing an instruction acquired from the memory by the DDR controller and writing a processing result into the memory through the DDR controller;
The DDR controller is used for executing the page configuration method for the memory.
In this embodiment, when the processor core needs to read or write data to the memory, an access request is generated, where the access request includes a memory address, an operation type (read request or write request), and data to be transferred. The DDR controller receives and parses the access request from the processor core and prepares a corresponding memory command based on the memory address and the operation type. The DDR controller places the memory command into a command queue and sends the command in the command queue to the memory. For read requests, data read from memory by the DDR controller is transferred back to the processor core via the internal bus. For write requests, data provided by the processor core is transferred to the DDR controller via the internal bus and then written to memory.
The Processor core may be selected from a CPU (Central Processing Unit ), GPU (Graphics Processing Unit, graphics Processor), NPU (Neural Network Processing Unit, neural network Processor), TPU (TensorProcessingUnit, tensor Processor), DPU (DEEP LEARNING Processing Unit, deep learning Processor), microprocessor, DSP (DIGITAL SIGNAL Processor ), ASIC (Application SPECIFIC INTEGRATED Circuit), FPGA (Field Programmable GATE ARRAY ), or a combination of at least two of these Processor forms. The memory stores instructions executable by at least one processor, which may be of different types, including, for example, a CPU and FPGA, a CPU and artificial intelligence processor, a CPU and GPU, and the like.
The memory may be implemented by DDR memory granules, which are DDR SDRAM, (DoubleDataRateSDRAM, double-rate synchronous dynamic random access memory). The storage unit storage sequence is organized into a plurality of layers, which are channel, DIMM, rank, chip, bank, row, column in sequence, and one channel corresponds to one DDR controller. Each group of Rank can be regarded as an independent memory module, has independent address space and control logic, and can independently perform read-write operation. In the memory controller, different memory modules can be accessed by selecting different ranks, so that multiple ranks can be accessed in parallel, and the memory bandwidth and performance can be improved.
The system set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
Those skilled in the art will appreciate that embodiments of the application may be provided as methods and systems. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, systems according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Although embodiments of the present application have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the application, and such modifications and variations are within the scope of the application as defined by the appended claims.
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