CN119846443A - Chip test circuit, method, system, storage medium and program product - Google Patents
Chip test circuit, method, system, storage medium and program product Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/317—Testing of digital circuits
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Abstract
本发明提出一种芯片的测试电路、方法、系统、存储介质和程序产品，芯片的测试电路包括：复用控制电路，用于获取测试机台输出的第一时序信号；控制器，与复用控制电路的输出端连接，用于在复用控制电路处于非测试模式时，根据第一时序信号输出测试预使能信号，或者，根据第一时序信号禁止输出测试预使能信号；测试使能检测电路，与控制器的输出端连接，用于根据测试预使能信号控制芯片进入测试模式，或者，根据测试预使能信号禁止芯片进入测试模式。本发明的电路保障了芯片的安全性，提升了芯片的测试覆盖率和资源利用率，降低了芯片误进入测试模式的风险，节省了芯片和设计成本。
The present invention proposes a test circuit, method, system, storage medium and program product for a chip, wherein the test circuit of the chip includes: a multiplexing control circuit for obtaining a first timing signal output by a test machine; a controller connected to the output end of the multiplexing control circuit for outputting a test pre-enable signal according to the first timing signal when the multiplexing control circuit is in a non-test mode, or forbidding the output of the test pre-enable signal according to the first timing signal; a test enable detection circuit connected to the output end of the controller for controlling the chip to enter a test mode according to the test pre-enable signal, or forbidding the chip to enter a test mode according to the test pre-enable signal. The circuit of the present invention ensures the security of the chip, improves the test coverage and resource utilization of the chip, reduces the risk of the chip mistakenly entering the test mode, and saves chip and design costs.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a test circuit, a method, a system, a storage medium, and a program product for a chip.
Background
The security entering the chip test mode is not important for the quality assurance and the use assurance of the chip, and in the related art, the method for entering the chip test mode includes using JTAG (Joint Test Action Group) or an interface similar to JTAG, using a specific chip pin, using a specific hardware time sequence, judging whether a specific register inside the chip meets a specific value or not, and the like.
However, the method cannot guarantee the safety of the chip, the test coverage rate and the resource utilization rate of the chip are low, the risk of the chip entering a test mode by mistake is high, and the chip and the design cost are high.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art.
Therefore, an object of the present invention is to provide a chip test circuit, which guarantees the security of the chip, improves the test coverage rate and resource utilization rate of the chip, reduces the risk of the chip entering a test mode by mistake, and saves the chip and design cost.
Therefore, a second object of the present invention is to provide a method for testing a chip.
To this end, a third object of the invention is to propose a test system.
To this end, a fourth object of the present invention is to propose a computer readable storage medium.
To this end, a fifth object of the invention is to propose a computer programme product.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a test circuit for a chip, where the test circuit for a chip includes a multiplexing control circuit configured to obtain a first timing signal output by a test machine, a controller connected to an output end of the multiplexing control circuit and configured to output a test pre-enable signal according to the first timing signal or prohibit the output of the test pre-enable signal according to the first timing signal when the multiplexing control circuit is in a non-test mode, and a test enable detection circuit connected to an output end of the controller and configured to control the chip to enter a test mode according to the test pre-enable signal or prohibit the chip from entering the test mode according to the test pre-enable signal.
According to the test circuit of the chip, the controller is connected with the output end of the multiplexing control circuit, the test enabling detection circuit is connected with the output end of the controller, the multiplexing control circuit is used for obtaining the first time sequence signal output by the test machine, when the multiplexing control circuit is in the non-test mode, the test pre-enabling signal is output according to the first time sequence signal, or the test pre-enabling signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enabling signal, or the chip is forbidden to enter the test mode according to the test pre-enabling signal, so that the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost are saved.
In some embodiments, the multiplexing control circuit comprises a first multiplexing sub-circuit connected with the output end of the test machine for outputting the first timing signal when in the non-test mode, wherein the first timing signal comprises a burning mode timing and a test mode command timing, a second multiplexing sub-circuit connected with the output end of the test machine for outputting a second timing signal when in the test mode, wherein the second timing signal comprises a digital logic test timing, and a selector connected with the output end of the first multiplexing sub-circuit and the output end of the second multiplexing sub-circuit respectively for selectively outputting the first timing signal or the second timing signal.
In some embodiments, the controller includes a timing detection sub-circuit connected to an output of the multiplexing control circuit, for receiving the first timing signal, entering a burn-in mode when determining that a burn-in mode timing in the first timing signal is correct according to the first timing signal, and outputting a test mode command timing in the first timing signal, and a security detection sub-circuit connected to an output of the timing detection sub-circuit, for outputting the test pre-enable signal according to the test mode command timing, or disabling outputting the test pre-enable signal according to the test mode command timing.
In some embodiments, the safety detection sub-circuit comprises a test command detection sub-circuit connected with the output end of the time sequence detection sub-circuit and used for prohibiting the output of a test pre-enable signal when the preset number of test mode command time sequences are wrong or outputting the test pre-enable signal when the preset number of test mode command time sequences are correct, and a first test output sub-circuit connected with the output end of the test command detection sub-circuit and used for outputting the test pre-enable signal according to the test pre-enable signal or prohibiting the output of the test pre-enable signal according to the test pre-enable signal.
In some embodiments, the first test output sub-circuit comprises at least two triggers connected with the output ends of the test command detection sub-circuit and used for receiving the test enabling pre-starting signal and outputting at least two trigger output signals, and a first AND gate connected with the output ends of the at least two triggers and used for prohibiting the output of the test pre-enabling signal or outputting the test pre-enabling signal according to the at least two trigger output signals.
In some embodiments, the first test output sub-circuit is specifically configured to prohibit outputting a test pre-enable signal according to the output signals of the remaining flip-flops when the output signal of one of the flip-flops is abnormal.
In some embodiments, the test enabling detection circuit comprises a timer connected with the output end of the controller and used for outputting a reset signal when the test enabling detection circuit does not receive the test pre-enabling signal within a preset time, and at least two second test output sub-circuits connected with the output end of the timer and used for resetting the second test output sub-circuits when receiving the reset signal or controlling the chip to enter a test mode when receiving the test pre-enabling signal within the preset time.
In some embodiments, the second test output sub-circuit comprises a multi-stage trigger connected with the output end of the timer and used for filtering interference signals in the test pre-enable signals, a second AND gate connected with the output end of the multi-stage trigger and used for receiving at least two test pre-enable signals, and a third AND gate connected with the output ends of the at least two second test output sub-circuits and used for outputting the test enable signals according to the at least two test pre-enable signals.
In some embodiments, the second test output sub-circuit further comprises an inverter, one end of the inverter is connected to the other end of the multi-stage flip-flop, and the other end of the inverter is connected to one end of the multi-stage flip-flop for isolating static electricity.
In some embodiments, the test circuit of the chip further comprises a digital logic circuit connected with the output end of the multiplexing control circuit and used for receiving the second time sequence signal in the test mode and outputting the test result.
In order to achieve the above object, an embodiment of a second aspect of the present invention provides a testing method for a chip, where the testing circuit for a chip includes a multiplexing control circuit, a controller, and a test enable detection circuit, and the method includes acquiring a first timing signal output by a testing machine, outputting a test pre-enable signal according to the first timing signal when the multiplexing control circuit is determined to be in a non-testing mode, or prohibiting the outputting of the test pre-enable signal according to the first timing signal, and controlling the chip to enter a testing mode according to the test pre-enable signal, or prohibiting the chip to enter the testing mode according to the test pre-enable signal.
According to the method for testing the chip, the controller is connected with the output end of the multiplexing control circuit, the test enabling detection circuit is connected with the output end of the controller, the first time sequence signal output by the test machine is obtained through the multiplexing control circuit, when the multiplexing control circuit is in a non-test mode, the test pre-enabling signal is output according to the first time sequence signal, or the test pre-enabling signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enabling signal, or the chip is forbidden to enter the test mode according to the test pre-enabling signal, so that the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost are saved.
In order to achieve the above objective, an embodiment of a third aspect of the present invention provides a test system, which includes a test machine for outputting a timing signal, and a test circuit of a chip as claimed in the above embodiment, connected to the test machine through an IO (Input/Output) port, for acquiring the timing signal, and controlling the chip to test according to the timing signal.
According to the test system provided by the embodiment of the invention, when the test circuit of the chip on the system is tested, the test machine is connected with the test circuit of the chip through the IO port, the test machine outputs a time sequence signal, such as a first time sequence signal, the first time sequence signal output by the test machine is obtained through the multiplexing control circuit, when the multiplexing control circuit is in a non-test mode, the test pre-enable signal is output according to the first time sequence signal, or the test pre-enable signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is forbidden to enter the test mode according to the test pre-enable signal, so that the test circuit of the chip controls the chip according to the time sequence signal, the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost is saved.
In order to achieve the above object, an embodiment of a fourth aspect of the present invention proposes a computer-readable storage medium having stored thereon a test circuit program of a chip, which when executed by a processor causes an apparatus having the test circuit program of the chip installed therein to realize the test circuit of the chip described in the above embodiment.
To achieve the above object, an embodiment of a fifth aspect of the present invention proposes a computer program product comprising a computer program which, when executed by a processor, implements the test circuit of the chip described in the above embodiment.
According to the computer program product of the embodiment of the invention, the computer program product runs on a test system, the controller is connected with the output end of the multiplexing control circuit, the test enabling detection circuit is connected with the output end of the controller, the first time sequence signal output by the test machine is obtained through the multiplexing control circuit, when the multiplexing control circuit is in a non-test mode, the test pre-enabling signal is output according to the first time sequence signal, or the test pre-enabling signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enabling signal, or the chip is forbidden to enter the test mode according to the test pre-enabling signal, so that the test circuit of the chip controls the chip test according to the time sequence signal, the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost is saved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a test circuit according to one embodiment of the invention;
FIG. 2 is a schematic diagram of a test circuit of a chip according to one embodiment of the invention;
fig. 3 is a schematic diagram of a multiplexing control circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a controller according to one embodiment of the invention;
FIG. 5 is a schematic waveform diagram according to one embodiment of the invention;
FIG. 6 is a schematic diagram of a test enable detection circuit according to one embodiment of the invention;
FIG. 7 is a flow chart of a method of testing a chip according to one embodiment of the invention;
FIG. 8 is a flow chart of a method of testing a chip according to one embodiment of the invention;
FIG. 9 is a block diagram of a test system according to one embodiment of the invention.
Reference numerals:
a test circuit 11 of the chip;
a testable region 50;
test machine 100, multiplexing control circuit 101, controller 102, digital logic circuit 103, test enable detection circuit 104;
A first multiplexing sub-circuit 200, a second multiplexing sub-circuit 201, a selector 202;
a timing detection sub-circuit 300, a security detection sub-circuit 301, a test command detection sub-circuit 302, a first test output sub-circuit 303, a first flip-flop 304, a second flip-flop 305, a third flip-flop 306, a first and gate 307;
timer 400, second test output subcircuit 401, second AND gate 403, third AND gate 404, inverter 405, flip-flop 406;
the system 10 is tested.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
In the related art, the present millions of design scales of the gate circuits are faced, and the following DFT (Design for Testabi lity) technology can improve the test efficiency and reduce the test cost, and the DFT technology refers to that the test requirement of the chip is considered in the design stage, and specific design elements are added in the hardware design, so that when the chip test is performed subsequently, whether the chip has a manufacturing fault or not can be detected under the condition that the shortest time and the lowest cost are used, and the test mode is mainly used for testing whether the manufacturing problem exists in the manufacturing process of the chip, such as short circuit, open circuit, device damage and the like, so that the chip does not have the capability of normal operation in the mode, and therefore, the chip must be strictly prohibited from entering the test mode in the normal operation process, so that the system generates an unpredictable error.
For example, using JTAG (Joint Test Action Group) or JTAG-like interfaces, the test mode of the chip is entered. However, since JTAG is a standard general test protocol, using JTAG or an interface similar to JTAG to enter a chip test mode may result in guaranteeing the security, such as an attacker may enter the test mode through the interface to read or modify internal data, the test coverage rate of the chip is low, such as the JTAG controller part cannot be tested, the resource utilization rate of the chip is low, and the cost of the chip is high, such as using JTAG-like protocol, the test interface is additionally increased, and the area and packaging cost of the chip are increased.
For another example, a test mode of the chip is entered using a particular chip pin. However, a specific chip pin, i.e., a non-multiplexed pin, is a very precious resource for a chip, and entering a test mode of the chip using a specific chip pin may make the resource utilization of the chip low, and for the pin, a security problem needs to be paid attention to, which may result in high design costs, such as isolation of the test pin, activation of the test pin, power management of the test pin, physical design of the test pin, and the like.
For another example, the timing of a particular hardware is used or it is determined whether a particular register within the chip satisfies a particular value into a test mode of the chip. However, both schemes have a risk of the chip entering the test mode by mistake during normal operation, and the test cannot cover the module used by the scheme, resulting in low test coverage.
Therefore, the test circuit of the chip of the embodiment of the invention is adopted to connect the controller with the output end of the multiplexing control circuit, the test enabling detection circuit is connected with the output end of the controller, the multiplexing control circuit is used for obtaining the first time sequence signal output by the test machine, when the multiplexing control circuit is in a non-test mode, the test pre-enabling signal is output according to the first time sequence signal, or the test pre-enabling signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enabling signal, or the chip is forbidden to enter the test mode according to the test pre-enabling signal, so that the safety of the chip is ensured, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost are saved.
The test circuit of the chip according to the embodiment of the present invention is described below with reference to fig. 1 to 6.
Fig. 1 is a schematic diagram of a test circuit according to an embodiment of the invention. The test machine 100 is used for sending a specific timing signal to enable the chip to correctly enter a test mode from a non-test mode when the chip needs to be tested, and a test data stream of a subsequent chip is also generated by the test machine 100 and sent into the chip, and the test circuit 11 of the chip comprises a multiplexing control circuit 101, a controller 102 and a test enabling detection circuit 104.
As shown in fig. 2, a block diagram of a test circuit of a chip according to an embodiment of the present invention is shown, and a test circuit 11 of a chip according to an embodiment of the present invention includes a multiplexing control circuit 101, a controller 102, and a test enable detection circuit 104.
The multiplexing control circuit 101 is configured to obtain a first timing signal output by the test machine, the controller 102 is connected to an output end of the multiplexing control circuit, and configured to output a test pre-enable signal according to the first timing signal or inhibit outputting the test pre-enable signal according to the first timing signal when the multiplexing control circuit is in a non-test mode, and the test enabling detection circuit 103 is connected to an output end of the controller, and is configured to control the chip to enter a test mode according to the test pre-enable signal or inhibit the chip from entering the test mode according to the test pre-enable signal.
In an embodiment, as shown in fig. 1, an input end of the multiplexing control circuit 101 is connected to an output end of the test machine 100, and in a case where a chip is to be tested, the multiplexing control circuit 101 receives and outputs a first timing signal output by the test machine 100, for example, a timing of a test mode command and a timing of a burn-in mode, so as to implement test pre-enable control according to the first timing signal.
The controller 102 is connected to the output end of the multiplexing control circuit 101, when the multiplexing control circuit 101 is in the non-test mode, the test pre-enable signal is output according to the first timing signal, or the test pre-enable signal is forbidden to be output according to the first timing signal, for example, after the controller 102 receives the first timing signal, for example, the first timing signal, such as the test mode command timing and the burning mode timing, the controller 102 determines the correctness of the received burning mode timing, if the determination result is wrong, the burning mode cannot be entered, and further the test pre-enable signal is forbidden to be output, if the determination result is correct, and if the determination result is also required to determine the correctness of the received test mode command timing, for example, the test pre-enable signal is forbidden to be output if the received 10 test mode command timings are only 1 command error or sequence error, and if the received command and sequence of the 10 test mode command timings are both correct, the controller 102 determines the correctness of the first timing signal, so as to control the output or the test pre-enable signal to be forbidden to be output, so as to control the test pre-enable control, and reduce the risk of the chip entering the test mode.
The test enable detection circuit 104 is connected to the output end of the controller 102, and controls the chip to enter the test mode according to the test pre-enable signal output by the controller 102, or prohibits the chip from entering the test mode according to the test pre-enable signal, for example, starting timing from the power-on of the chip, and if the test enable detection circuit 104 receives the test pre-enable signal output by the controller 102 within a preset time, the chip is controlled to enter the test mode, and if the test enable detection circuit 104 does not receive the test pre-enable signal output by the controller 102 within the preset time, the chip is prohibited from entering the test mode, so that the test mode control is performed, and the risk that the chip enters the test mode by mistake is reduced.
The test enabling detection circuit 104 is an independent circuit module, the module circuit is less, the probability of production failure is low, the module circuit is built in a chip, special pins of the chip can be saved, the safety of the chip is guaranteed, the chip and design cost are saved, the multiplexing control circuit 101 and the controller 102 can perform test coverage except the test enabling detection circuit 104, and the test coverage rate and the resource utilization rate of the chip are improved.
According to the test circuit of the chip, the controller is connected with the output end of the multiplexing control circuit, the test enabling detection circuit is connected with the output end of the controller, the multiplexing control circuit is used for obtaining the first time sequence signal output by the test machine, when the multiplexing control circuit is in the non-test mode, the test pre-enabling signal is output according to the first time sequence signal, or the test pre-enabling signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enabling signal, or the chip is forbidden to enter the test mode according to the test pre-enabling signal, so that the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost are saved.
In some embodiments, as shown in fig. 3, a schematic diagram of a multiplexing control circuit according to an embodiment of the invention is shown. Referring to fig. 1 and 3, the multiplexing control circuit 101 includes a first multiplexing sub-circuit 200, a second multiplexing sub-circuit 201, and a selector 202, where the first multiplexing sub-circuit 200 is connected to an output terminal of the test bench 100 and is used for outputting a first timing signal when in a non-test mode, the first timing signal includes a burn-in mode timing and a test mode command timing, the second multiplexing sub-circuit 201 is connected to an output terminal of the test bench 100 and is used for outputting a second timing signal when in a test mode, the second timing signal includes a digital logic test timing, and the selector 202 is connected to the output terminal of the first multiplexing sub-circuit 200 and the output terminal of the second multiplexing sub-circuit 201, respectively, and is used for selectively outputting the first timing signal or the second timing signal.
In an embodiment, referring to fig. 1 and 3, the selector 202 is a device having a plurality of inputs and an output, and selects the output from the plurality of inputs according to an input selection signal, and the multiplexing control circuit 101 includes a first multiplexing sub-circuit 200, a second multiplexing sub-circuit 201, and the selector 202, where the first multiplexing sub-circuit 200 is connected to an output terminal of the test station 100, the second multiplexing sub-circuit 201 is connected to an output terminal of the test station 100, and the selector 202 is connected to output terminals of the first multiplexing sub-circuit 200 and the second multiplexing sub-circuit 201, respectively.
In the non-test mode, the test machine 100 sends the burning mode time sequence and the test mode command time sequence sent by the input and output pins as first time sequence signals to the first multiplexing sub-circuit 200, in the test mode, the test machine 100 sends the digital logic test time sequence sent by the input and output pins as second time sequence signals to the second multiplexing sub-circuit 201, the first multiplexing sub-circuit 200 and the second multiplexing sub-circuit 201 send the received time sequences to the selector 202 respectively, the selector 202 selects and outputs the first time sequence signals or the second time sequence signals after receiving the corresponding time sequence signals, the selector 202 switches the signal output to the first multiplexing sub-circuit 200 to normally use the multiplexing function in the non-test mode, the selector 202 switches the output signals to the second multiplexing sub-circuit 201 in the test mode, wherein the normal multiplexing function of the first multiplexing sub-circuit 200 is the measurable logic, the second multiplexing sub-circuit 201 tests the multiplexing function and the selector 202 is the non-measurable logic, the test and resource utilization rate of the chip is improved, and the selector 202 selects and outputs the signal to the corresponding time sequence signals to the non-test mode in order mode or prevent the chip from entering the test mode.
In some embodiments, as shown in fig. 4, a schematic structural diagram of a controller according to an embodiment of the present invention is shown. Referring to fig. 1, the controller 102 includes a timing detection sub-circuit 300 and a safety detection sub-circuit 301, where the timing detection sub-circuit 300 is connected to an output terminal of the multiplexing control circuit 101, and is configured to receive a first timing signal, enter a recording mode when determining that a recording mode timing in the first timing signal is correct according to the first timing signal, and output a test mode command timing in the first timing signal, and the safety detection sub-circuit 301 is connected to an output terminal of the timing detection sub-circuit 300, and is configured to output a test pre-enable signal according to the test mode command timing, or disable outputting the test pre-enable signal according to the test mode command timing.
In an embodiment, referring to fig. 1 and 4, the controller 102 includes a timing detection sub-circuit 300 and a safety detection sub-circuit 301, the timing detection sub-circuit 300 is connected to an output terminal of the multiplexing control circuit 101, and the safety detection sub-circuit 301 is connected to an output terminal of the timing detection sub-circuit 300.
The timing detection sub-circuit 300 receives the first timing signal, when determining that the timing of the burning mode in the first timing signal is correct according to the first timing signal, enters the burning mode, outputs the timing of the test mode command in the first timing signal, for example, the timing detection sub-circuit 300 can open the clock and reset of the area of the safety detection sub-circuit 301 after receiving the correct timing of the burning mode, enters the burning mode, outputs the timing of the test mode command in the first timing signal, and after receiving the incorrect timing of the burning mode, the area of the safety detection sub-circuit 301 is in a reset state and cannot enter the burning mode, and cannot output the timing of the test mode command in the first timing signal, thereby avoiding entering the test mode, and reducing the risk of entering the test mode due to incorrect timing.
In some embodiments, as shown in fig. 4, the safety detection sub-circuit 301 includes a test command detection sub-circuit 302 and a first test output sub-circuit 303, where the test command detection sub-circuit 302 is connected to an output terminal of the timing detection sub-circuit and is configured to prohibit outputting a test pre-enable signal when a preset number of test mode commands have timing errors or to output a test enable pre-enable signal when a preset number of test mode commands have timing errors, and the first test output sub-circuit 303 is connected to an output terminal of the test command detection sub-circuit 302 and is configured to output the test pre-enable signal according to the test enable pre-enable signal or prohibit outputting the test pre-enable signal according to the test enable pre-enable signal.
In an embodiment, as shown in fig. 4, the safety detection sub-circuit 301 includes a test command detection sub-circuit 302 and a first test output sub-circuit 303, the test command detection sub-circuit 302 is connected to an output terminal of the timing detection sub-circuit 300, and the first test output sub-circuit 303 is connected to an output terminal of the test command detection sub-circuit 302.
The test command detection sub-circuit 302 is configured to prohibit outputting a test pre-enable signal when a predetermined number of test mode command timing errors occur, or is configured to output a test pre-enable signal when a predetermined number of test mode command timing errors occur, for example, assuming that the predetermined number is 10, the test command detection sub-circuit 302 detects correctness of 10 test mode command timings after receiving a test mode command timing in a first timing signal output by the timing detection sub-circuit 300, prohibits outputting the test pre-enable signal if 1 error or a sequence error occurs in the 10 test mode command timing, the chip cannot enter a test mode, and outputs the test pre-enable signal if both the value and the sequence of the 10 test mode command timing are correct, thereby reducing risk of entering the test mode due to an abnormal timing error, and providing a basis for outputting the test pre-enable signal subsequently, and the first test output sub-circuit 303 outputs the test pre-enable signal according to the test pre-enable signal or prohibits outputting the test pre-enable signal according to the test pre-enable signal, so that the controller can realize test pre-enable control.
In some embodiments, as shown in fig. 4, the first test output sub-circuit 303 includes at least two flip-flops and a first and gate 307, where the at least two flip-flops are connected to an output terminal of the test command detection sub-circuit 302 and are used to receive the test enable pre-enable signal and output at least two trigger output signals, and the first and gate 307 is connected to an output terminal of the at least two flip-flops and is used to prohibit the output of the test pre-enable signal or output the test pre-enable signal according to the at least two trigger output signals.
In an embodiment, as shown in fig. 4, the first test output sub-circuit 303 comprises at least two flip-flops, such as a first flip-flop 304, a second flip-flop 305 and a third flip-flop 306, and a first and gate 307, the at least two flip-flops being connected to the output of the test command detection sub-circuit 302, and the first and gate 307 being connected to the output of the at least two flip-flops.
The method comprises the steps of receiving test enabling pre-starting signals by at least two triggers, outputting at least two trigger output signals, wherein for example, the trigger works normally, if abnormal overturn does not occur, the output trigger output signals are the test enabling pre-starting signals, if abnormal overturn occurs, the output trigger output signals are the forbidden output test pre-enabling signals, the at least two triggers receive the forbidden output test pre-enabling signals, if abnormal overturn does not occur, the output trigger output signals are the forbidden output test pre-enabling signals, if abnormal overturn occurs, the output trigger output signals are the test enabling pre-starting signals, the first AND gate 307 carries out logic AND according to the at least two trigger output signals, outputs the forbidden output test pre-enabling signals or outputs the test pre-enabling signals, and the risk that a chip enters a test mode by mistake due to the severe external working environment, for example, the trigger is caused by electromagnetic pulse or cosmic ray impact and the like is reduced.
In some embodiments, the first test output sub-circuit is specifically configured to prohibit outputting the test pre-enable signal according to the output signals of the remaining flip-flops when the output signal of one of the flip-flops is abnormal.
In an embodiment, when the output signal of one of the flip-flops is abnormal, for example, in the first test output sub-circuit abnormal waveform of the left waveform in fig. 5, the input signal is an output-prohibition test pre-enable signal, the first flip-flop 304, the second flip-flop 305 and the third flip-flop 306 receive the output-prohibition test pre-enable signal, the corresponding waveforms are the first flip-flop, the second flip-flop and the third flip-flop in fig. 5 respectively, wherein the waveform of the first flip-flop 304 is an abnormal waveform, when one and/or two of the three flip-flops generate abnormal flip-flop due to external environment such as electromagnetic pulse or cosmic ray, for example, the first flip-flop 304 generates abnormal flip-flop output signal, the received output-prohibition test pre-enable signal becomes the output test pre-enable signal and is output, and the output-prohibition output test pre-enable signal is generated by the output result of the logic and of the waveforms of the first flip-flop 304, the second flip-flop 305 and the third flip-flop 306 through the first and gate 307, and the correct output result is correct; only when the first flip-flop 304, the second flip-flop 305, and the third flip-flop 306 are all abnormally flipped, that is, the output result of the three flip-flops logically and-ed through the first and gate 307 is the output test pre-enable signal only when the output test pre-enable signal received by all the flip-flops is changed to the output test pre-enable signal and outputted, is the erroneous output result, it is assumed that a single flip-flop is used, in the single flip-flop abnormal waveform of fig. 5, the input signal is the output test pre-enable signal is prohibited, when the flip-flop is abnormally flipped to the output test pre-enable signal, the output result of the flip-flop logically and-ed through the first and gate 307 is the output test pre-enable signal, the chip can enter the test mode by mistake due to the fact that the chip outputs a wrong result, the risk that the chip enters the test mode by mistake due to the severe external working environment is reduced, for example, the trigger is overturned abnormally due to the impact of electromagnetic pulse or cosmic rays and the like, and therefore the probability that the chip enters the test mode by mistake is reduced.
In some embodiments, as shown in fig. 6, a schematic diagram of a test enable detection circuit according to an embodiment of the invention is shown. The test enabling detection circuit comprises a timer 400 and at least two second test output sub-circuits 401, wherein the timer 400 is connected with the output end of the controller 102 and is used for outputting a reset signal when the test enabling detection circuit does not receive a test pre-enabling signal within preset time, and the at least two second test output sub-circuits 401 are connected with the output end of the timer and are used for resetting the second test output sub-circuits 401 when receiving the reset signal or controlling the chip to enter a test mode when receiving the test pre-enabling signal within preset time.
In an embodiment, as shown in fig. 6, the test enable detection circuit 104 includes a timer 400 and at least two second test output subcircuits 401, the timer 400 is connected to the output of the controller 102, the at least two second test output subcircuits 401 are connected to the output of the timer 400, wherein the logic of the two second test output subcircuits 401 is identical, and when laid out, they are placed in two completely different areas in the chip, physically isolated, to reduce the effect of cosmic rays.
The timer 400 starts timing from the chip power-on, receives a test pre-enable signal output by the controller 102 within a preset time, outputs a reset signal when the test pre-enable signal output by the controller 102 is not received by the test enable detection circuit within the preset time, and sends the reset signal to the at least two second test output sub-circuits 401, and resets the second test output sub-circuits when the reset signal is received by the at least two second test output sub-circuits 401, so that the chip cannot enter the test mode, or controls the chip to enter the test mode when the test pre-enable signal output by the controller 102 is received within the preset time, and controls the chip to enter the test mode through the timer and the at least two second test output sub-circuits, thereby reducing the risk of entering the test mode due to abnormal time sequence errors and further reducing the risk of the chip entering the test mode due to the abnormal time sequence errors.
In some embodiments, as shown in fig. 6, the second test output sub-circuit includes a multi-stage flip-flop, a second and gate 403 and a third and gate 404, where the multi-stage flip-flop is connected to an output of the timer and is used to filter out an interference signal in the test pre-enable signal, the second and gate is connected to an output of the multi-stage flip-flop and is used to receive at least two test pre-enable signals, and the third and gate is connected to outputs of the at least two second test output sub-circuits and is used to output the test enable signal according to the at least two test pre-enable signals.
In an embodiment, as shown in fig. 6, the second test output sub-circuit 401 includes a multi-stage flip-flop, a second and gate 403, and a third and gate 404, where the multi-stage flip-flop refers to a cascade of a plurality of flip-flops 406, the multi-stage flip-flop is connected to an output terminal of the timer 400, the second and gate 403 is connected to an output terminal of the multi-stage flip-flop, and the third and gate 404 is connected to output terminals of at least two second test output sub-circuits 401.
The multi-stage flip-flop can filter the interference signal in the test pre-enable signal, the second and gate 403 receives at least two test pre-enable signals, the third and gate 404 outputs the test pre-enable signal according to the at least two test pre-enable signals, for example, the input of the timer is the output prohibition test pre-enable signal, when one of the two second test output sub-circuits 401 generates problems due to factors such as production, packaging, testing and external environment, the output prohibition test pre-enable signal received by one circuit is changed into the output test pre-enable signal through the test output sub-circuit and is output, and when the output prohibition test pre-enable signal received by the other circuit is not changed and is output through the test output sub-circuit, the result of whether the test mode is obtained by the output result of the two test output sub-circuits through the third and gate 404, and the result is still the output prohibition test enable signal after the logic and, so that the risk of entering the test mode due to combination logic burrs and the like is reduced, and the risk of the chip entering the test mode by mistake is reduced.
In some embodiments, the second test output sub-circuit further comprises an inverter, one end of the inverter is connected to the other end of the multi-stage flip-flop, and the other end of the inverter is connected to one end of the multi-stage flip-flop for isolating static electricity.
In an embodiment, as shown in fig. 6, the two test output sub-circuits 401 further include an inverter 405, one end of the inverter 405 is connected to the other end of the multi-stage flip-flop, the multi-stage flip-flop is cascade connected to a plurality of flip-flops 406, the other end of the inverter is connected to one end of the multi-stage flip-flop, the structure of the multi-stage flip-flop and the inverter is used, and the result of combining the output signals is logically and-outputted through the second and gate 403, so that the risk that the chip enters the test mode by mistake is reduced, and the inverter can reduce the damage of static electricity to the chip.
In some embodiments, the test circuit of the chip further includes a digital logic circuit connected to an output terminal of the multiplexing control circuit, for receiving the second timing signal in the test mode and outputting the test result.
In an embodiment, as shown in fig. 1, the test circuit of the chip further includes a digital logic circuit 103 connected to an output end of the multiplexing control circuit 101, the digital logic circuit 103 does not have a normal function in the test mode, and when the hardware circuit is designed, the flip-flops and the combinational logic are required to be grouped and chained into a logic chain based on the original function design, so that the digital logic circuit 103 receives a second time sequence signal, such as a digital logic test time sequence, in the test mode, and outputs a test result to the multiplexing control circuit 101, and the multiplexing control circuit 101 outputs the test result to the outside of the chip, so as to verify the correctness of the digital logic circuit 103, and the design of the logic circuit 103 is independent, so that the test coverage of the part can reach a very high level.
The following describes a flowchart of a test method of a chip according to an embodiment of the second aspect of the present invention.
Fig. 7 is a flowchart of a method for testing a chip according to an embodiment of the invention. The chip testing method at least comprises the steps S1-S3.
Step S1, a first timing signal output by a test machine is obtained;
In an embodiment, as shown in fig. 1, an input end of the multiplexing control circuit 101 is connected to an output end of the test machine 100, and in a case where a chip is to be tested, the multiplexing control circuit 101 receives and outputs a first timing signal of the test machine 100, for example, a test mode command timing and a burn-in mode timing, so as to implement test pre-enable control according to the first timing signal.
Step S2, when the multiplexing control circuit is in a non-test mode, outputting a test pre-enable signal according to the first time sequence signal or prohibiting outputting the test pre-enable signal according to the first time sequence signal.
In an embodiment, as shown in fig. 1, the controller 102 is connected to an output end of the multiplexing control circuit 101, when the multiplexing control circuit 101 is in a non-test mode, the pre-test enable signal is output according to a first timing signal, or the pre-test enable signal is prohibited from being output according to the first timing signal, for example, after the controller 102 receives the first timing signal, for example, the first timing signal, such as the test mode command timing and the recording mode timing, the controller 102 determines the correctness of the received recording mode timing, if the determination result is incorrect, the recording mode cannot be entered, and then the pre-test enable signal is prohibited from being output, if the determination result is correct, and if the determination result is also required to determine the correctness of the received test mode command timing, for example, if the determination result is correct for 1 command or the sequence error for the received 10 test mode command timings, the pre-test enable signal is prohibited from being output, if the commands and the sequence of the received 10 test mode command timings are both correct, and the correctness of the first timing signal is determined by the controller 102, so that the output of the pre-test enable signal is controlled or the pre-test enable signal is prohibited from being output, and the risk of entering the test mode is reduced.
And S3, controlling the chip to enter a test mode according to the test pre-enabling signal, or prohibiting the chip from entering the test mode according to the test pre-enabling signal.
In an embodiment, as shown in fig. 1, the test enable detection circuit 104 is connected to an output end of the controller 102, and controls the chip to enter the test mode according to the test pre-enable signal output by the controller 102, or prohibits the chip from entering the test mode according to the test pre-enable signal, for example, from the start of power-on of the chip, if the test enable detection circuit 104 receives the test pre-enable signal output by the controller 102 within a preset time, the control chip enters the test mode, and if the test enable detection circuit 104 does not receive the test pre-enable signal output by the controller 102 within the preset time, the chip is prohibited from entering the test mode, so as to facilitate the test mode control, and reduce the risk of the chip entering the test mode by mistake.
The test enabling detection circuit 104 is an independent circuit module, the module circuit is less, the probability of production failure is low, the module circuit is built in a chip, special pins of the chip can be saved, the safety of the chip is guaranteed, the chip and design cost are saved, the multiplexing control circuit 101 and the controller 102 can perform test coverage except the test enabling detection circuit 104, and the test coverage rate and the resource utilization rate of the chip are improved.
According to the method for testing the chip, the controller is connected with the output end of the multiplexing control circuit, the test enabling detection circuit is connected with the output end of the controller, the first time sequence signal output by the test machine is obtained through the multiplexing control circuit, when the multiplexing control circuit is in a non-test mode, the test pre-enabling signal is output according to the first time sequence signal, or the test pre-enabling signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enabling signal, or the chip is forbidden to enter the test mode according to the test pre-enabling signal, so that the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost are saved.
The test method of the chip according to the embodiment of the present invention is specifically described below with reference to fig. 8.
Referring to fig. 8, a flowchart of a method for testing a chip according to an embodiment of the invention is shown, where the method for testing a chip according to the embodiment of the invention at least includes steps S10 to S25.
Step S10, a time sequence signal output by the test machine is obtained.
Step S11, judging that the multiplexing circuit is in a non-test mode. If yes, go to step S12, otherwise go to step S13.
In step S13, the second multiplexing sub-circuit outputs a second timing signal including a digital logic test timing.
In step S14, the selector outputs the second timing signal.
And S15, testing the chip and outputting a test result.
In step S12, the first multiplexing sub-circuit outputs a first timing signal including a programming mode timing and a test mode command timing.
In step S16, the selector outputs the first timing signal.
In step S17, the controller determines whether the timing sequence of the recording mode and the predetermined number of test mode commands is correct. If yes, go to step S18, otherwise go to step S19.
In step S18, a test enable pre-start signal is output.
In step S19, outputting the test pre-enable signal is disabled.
In step S20, the controller determines whether the test enable pre-start signal is correct. If yes, go to step S21, otherwise go to step S22.
Step S21, test the pre-enable signal.
In step S22, the output of the test pre-enable signal is disabled.
In step S23, the test enable detection circuit determines whether a correct test pre-enable signal is received within a preset time. If yes, go to step S24, otherwise go to step S25.
Step S24, the control chip enters a test mode.
Step S25, the chip is prohibited from entering the test mode.
According to the chip testing method provided by the embodiment of the invention, the controller is connected with the output end of the multiplexing control circuit, the test enabling detection circuit is connected with the output end of the controller, the multiplexing control circuit is used for obtaining the first time sequence signal output by the test machine, when the multiplexing control circuit is in the non-test mode, the test pre-enabling signal is output according to the first time sequence signal, or the test pre-enabling signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enabling signal, or the chip is forbidden to enter the test mode according to the test pre-enabling signal, so that the test circuit of the chip controls the chip test according to the time sequence signal, the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost is saved.
A test system according to an embodiment of the present invention is described below with reference to fig. 9.
Referring to fig. 9, a block diagram of a test system according to an embodiment of the present invention includes a test machine 100 and a test circuit 11 of a chip.
The test machine 100 is connected to the test circuit 11 of the chip through the IO port, and is configured to output a timing signal, for example, a first timing signal and a second timing signal, so that the test circuit 11 of the chip controls the chip to test according to the timing signal.
According to the test system of the embodiment of the invention, when the test circuit of the chip on the system is tested, the test machine 100 is connected with the test circuit 11 of the chip through the IO port, the test machine outputs a time sequence signal, such as a first time sequence signal, the first time sequence signal output by the test machine is obtained through the multiplexing control circuit, when the multiplexing control circuit is in a non-test mode, the test pre-enable signal is output according to the first time sequence signal, or the test pre-enable signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is forbidden to enter the test mode according to the test pre-enable signal, so that the test circuit of the chip controls the chip test according to the time sequence signal, the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost is saved.
The computer-readable storage medium of the embodiment of the present invention is described below.
The computer readable storage medium of the embodiment of the invention stores the test circuit program of the chip on the computer readable storage medium, and the test circuit program of the chip, when executed by the processor, causes the device provided with the test circuit program of the chip to realize the test circuit of the chip of the above embodiment.
A computer program product of an embodiment of the invention is described below.
The computer program product of an embodiment of the invention comprises a computer program which, when executed by a processor, implements the test circuit of the chip of the above embodiment.
According to the computer program product of the embodiment of the invention, the computer program product runs on a test system, the controller is connected with the output end of the multiplexing control circuit, the test enabling detection circuit is connected with the output end of the controller, the first time sequence signal output by the test machine is obtained through the multiplexing control circuit, when the multiplexing control circuit is in a non-test mode, the test pre-enabling signal is output according to the first time sequence signal, or the test pre-enabling signal is forbidden to be output according to the first time sequence signal, the chip is controlled to enter the test mode according to the test pre-enabling signal, or the chip is forbidden to enter the test mode according to the test pre-enabling signal, so that the test circuit of the chip controls the chip test according to the time sequence signal, the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters the test mode by mistake is reduced, and the chip and the design cost is saved.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (14)
1. A test circuit for a chip, comprising:
the multiplexing control circuit is used for acquiring a first timing signal output by the test machine;
The controller is connected with the output end of the multiplexing control circuit and is used for outputting a test pre-enabling signal according to the first time sequence signal or forbidding outputting the test pre-enabling signal according to the first time sequence signal when the multiplexing control circuit is in a non-test mode;
And the test enabling detection circuit is connected with the output end of the controller and is used for controlling the chip to enter a test mode according to the test pre-enabling signal or prohibiting the chip from entering the test mode according to the test pre-enabling signal.
2. The chip test circuit of claim 1, wherein the multiplexing control circuit comprises:
The first multiplexing sub-circuit is connected with the output end of the test machine and is used for outputting the first timing signal when in the non-test mode, wherein the first timing signal comprises a burning mode timing sequence and a test mode command timing sequence;
the second multiplexing sub-circuit is connected with the output end of the test machine and is used for outputting a second time sequence signal when in a test mode, and the second time sequence signal comprises a digital logic test time sequence;
And the selector is respectively connected with the output end of the first multiplexing sub-circuit and the output end of the second multiplexing sub-circuit and is used for selecting and outputting the first time sequence signal or the second time sequence signal.
3. The chip test circuit of claim 1, wherein the controller comprises:
The time sequence detection sub-circuit is connected with the output end of the multiplexing control circuit and is used for receiving the first time sequence signal, entering a burning mode when determining that the time sequence of the burning mode in the first time sequence signal is correct according to the first time sequence signal, and outputting a test mode command time sequence in the first time sequence signal;
And the safety detection sub-circuit is connected with the output end of the time sequence detection sub-circuit and is used for outputting the test pre-enabling signal according to the test mode command time sequence or forbidding outputting the test pre-enabling signal according to the test mode command time sequence.
4. A test circuit for a chip as recited in claim 3, wherein said security detection subcircuit comprises:
The test command detection sub-circuit is connected with the output end of the time sequence detection sub-circuit and is used for prohibiting outputting a test pre-enabling signal when the preset number of test mode commands have time sequence errors or outputting a test pre-enabling signal when the preset number of test mode commands have correct time sequence;
And the first test output sub-circuit is connected with the output end of the test command detection sub-circuit and is used for outputting the test pre-enabling signal according to the test enabling pre-enabling signal or forbidding outputting the test pre-enabling signal according to the test enabling pre-enabling signal.
5. The chip test circuit of claim 4, wherein the first test output sub-circuit comprises:
The at least two triggers are connected with the output end of the test command detection subcircuit and are used for receiving the test enabling pre-starting signal and outputting at least two trigger output signals;
and the first AND gate is connected with the output ends of at least two triggers and is used for prohibiting the output of a test pre-enabling signal or outputting the test pre-enabling signal according to the at least two trigger output signals.
6. The chip test circuit of claim 4, wherein the first test output subcircuit is specifically configured to:
And when the output signal of one of the triggers is abnormal, the output of the test pre-enabling signal is forbidden according to the output signals of the other triggers.
7. The chip test circuit of claim 1, wherein the test enable detection circuit comprises:
The timer is connected with the output end of the controller and is used for outputting a reset signal when the test enabling detection circuit does not receive the test pre-enabling signal within preset time;
And the at least two second test output subcircuits are connected with the output end of the timer and are used for resetting the second test output subcircuits when receiving the reset signal or controlling the chip to enter a test mode when receiving the test pre-enabling signal within the preset time.
8. The chip test circuit of claim 7, wherein the second test output sub-circuit comprises:
The multistage trigger is connected with the output end of the timer and is used for filtering interference signals in the test pre-enabling signals;
the second AND gate is connected with the output end of the multi-stage trigger and is used for receiving at least two test pre-enabling signals;
And the third AND gate is connected with the output ends of the at least two second test output sub-circuits and is used for outputting the test enabling signals according to the at least two test pre-enabling signals.
9. The chip test circuit of claim 8, wherein the second test output sub-circuit further comprises:
and one end of the inverter is connected with the other end of the multi-stage trigger, and the other end of the inverter is connected with one end of the multi-stage trigger and is used for isolating static electricity.
10. The test circuit of the chip of claim 1, wherein the test circuit of the chip further comprises:
And the digital logic circuit is connected with the output end of the multiplexing control circuit and is used for receiving the second time sequence signal in the test mode and outputting a test result.
11. A method of testing a chip, the test circuit for the chip comprising a multiplexing control circuit, a controller, and a test enable detection circuit, the method comprising:
Acquiring a first timing signal output by a test machine;
When the multiplexing control circuit is determined to be in a non-test mode, outputting a test pre-enabling signal according to the first time sequence signal or prohibiting outputting the test pre-enabling signal according to the first time sequence signal;
And controlling the chip to enter a test mode according to the test pre-enabling signal, or prohibiting the chip from entering the test mode according to the test pre-enabling signal.
12. A test system, comprising:
the test machine is used for outputting a time sequence signal;
The chip test circuit according to any one of claims 1-10, connected to the test machine through an IO port, for obtaining the timing signal, and controlling the chip test according to the timing signal.
13. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a test circuit program of a chip, which when executed by a processor causes an apparatus on which the test circuit program of a chip is installed to implement the test circuit of a chip according to any one of claims 1-10.
14. A computer program product, characterized in that the computer program product comprises a computer program which, when executed by a processor, implements the test circuit of the chip according to any of claims 1-10.
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