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CN119847284B - Multi-clock domain burr-free switching method supporting clock dynamic switch - Google Patents

Multi-clock domain burr-free switching method supporting clock dynamic switch

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Publication number
CN119847284B
CN119847284B CN202411967174.5A CN202411967174A CN119847284B CN 119847284 B CN119847284 B CN 119847284B CN 202411967174 A CN202411967174 A CN 202411967174A CN 119847284 B CN119847284 B CN 119847284B
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clock
signal
switching
clk
sel
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CN119847284A (en
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陈卫坤
尹康
郝明
韩文俊
何国强
李世平
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Jiangsu Huachuang Micro System Co ltd
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Jiangsu Huachuang Micro System Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B7/00—Arrangements for obtaining smooth engagement or disengagement of automatic control
    • G05B7/02—Arrangements for obtaining smooth engagement or disengagement of automatic control electric
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/13—Modifications for switching at zero crossing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Automation & Control Theory (AREA)
  • Electronic Switches (AREA)

Abstract

The invention discloses a multi-clock domain burr-free switching method supporting clock dynamic switching, which comprises the following steps that S1, a MUX multiplexer outputs a normally open clk clock signal according to the switching condition of each clock source and sends the clk clock signal to a corresponding clock switching sub-module, S2, in the clock switching sub-module, a sel clock selection signal corresponding to the clk clock signal is output as a gating signal of the clk clock signal through an AND gate, a three-stage register and a one-stage register, a non-signal of the sel clock selection signal is output as a gating signal of the clock to be switched through the AND gate and the three-stage register, S3, after the clk clock signal is turned off in a falling edge triggering mode, a feedback signal is generated, and after the clock to be switched receives the feedback signal, the clock to be switched is turned on through the gating signal, and switching is completed. The method provided by the invention can be applied to a clock switching system of a low-power MCU, and can realize multi-clock switching.

Description

Multi-clock domain burr-free switching method supporting clock dynamic switch
Technical Field
The invention relates to the technical field of chips, in particular to a multi-clock domain burr-free switching method supporting a clock dynamic switch.
Background
MCU chip, i.e. micro control unit, is a highly integrated semiconductor chip, widely used in modern electronic devices. The system clock source of the MCU chip generally comprises an internal oscillator, an external crystal oscillator and a phase-locked loop, the number of the clock sources can reach 3-5, in order to meet the low power consumption requirement of the MCU, the high-speed clock is switched to the low-speed clock before entering the low power consumption mode, the non-running clock source is closed to reduce the power consumption, the low-speed clock is switched to the high-speed clock before exiting the low power consumption mode to meet the clock frequency requirement of the normal running of the system, the MCU needs to realize the function of mutually switching among multiple paths of clocks, and clock signal burrs can be generated by adopting the implementation mode of the combined logic mux, so that the stability of the system is seriously influenced.
At present, the traditional clock burr-free switching scheme comprises a clock selection signal generating circuit, a synchronizing circuit and a multiplexer, wherein the clock selection signal generating circuit is used for generating a plurality of clock selection signals, the synchronizing circuit is used for synchronously processing the plurality of clock selection signals, the falling edge of the former clock selection signal is aligned with the rising edge of the latter clock selection signal in any two adjacent clock selection signals after processing, the rising edge of each clock selection signal is aligned with the rising edge of the corresponding clock signal, the falling edge of each clock selection signal is aligned with the latter falling edge of the corresponding clock signal, and one path of output is selected from the input plurality of clock signals through the multiplexer.
However, the current clock burr-free switching scheme at least comprises the following three problems:
1) When the clock is switched by the clock burr-free switching scheme, a clock selection signal generating circuit is required to generate a plurality of clock selection signals and a group of corresponding clock signals, so that the system can generate higher power consumption;
2) When the clock switching scheme is used for clock switching, the falling edge of the previous clock selection signal is required to be aligned with the rising edge of the next clock selection signal, and if time delay occurs in the middle, the falling edge of the previous clock selection signal cannot be aligned with the rising edge of the next clock selection signal;
3) The clock burr-free switching scheme can only switch the clock signals corresponding to two adjacent clock selection signals and can not switch any two clock signals.
Disclosure of Invention
Aiming at the three problems, the invention aims to provide a multi-clock domain burr-free switching method supporting clock dynamic switching, which can realize multi-clock switching by cascading a plurality of clock switching submodules, not only solves the requirement of more than two paths of clock switching of an MCU, but also solves the problem that a clock source needs to be closed in a low-power consumption mode, and simultaneously can avoid the problem that the clock source is closed before the clock switching is completed by generating a clock switching completion mark.
The method is realized by the following technical scheme:
S1, generating a plurality of different clock signals through a plurality of clock sources, inputting the clock signals into a MUX multiplexer, outputting a corresponding clk clock signal by the MUX multiplexer according to the switching condition of each clock source, and transmitting the clk clock signal to a corresponding clock switching submodule; S2, after a sel clock selection signal corresponding to a clk clock signal passes through an and gate, a three-stage register and a one-stage register, outputting a non-signal of the sel clock selection signal, taking the non-signal of the sel clock selection signal as a gating signal of the clk clock signal, outputting the non-signal of the sel clock selection signal as the gating signal of the clock signal to be switched through the and gate and the three-stage register, closing the clk clock signal through the gating signal, and switching the clock signal, S3, when the clk clock signal is switched, a feedback signal is generated after the clk clock signal is closed through the gating signal in a falling edge triggering mode, and outputting the feedback signal to the clock to be switched, after the feedback signal is received by the clock to be switched, opening the clock to be switched through the gating signal, so as to finish switching, and meanwhile, each clock switching sub-module increases a corresponding mark signal of opening or closing each clock signal, and when any clock signal is not opened, the corresponding clock enabling signal is in a low level.
The invention provides a multi-clock domain burr-free switching method which is suitable for a low-power consumption MCU and supports clock dynamic switching, multi-clock switching can be realized by cascading a plurality of clock switching submodules, and the MCU is supported to close a non-running clock source after receiving a switching completion mark so as to reduce power consumption.
Preferably, in step S1, each clock source comprises an oscillator, a crystal oscillator and a phase-locked loop, wherein the oscillator and the crystal oscillator are used for generating clock signals, and the phase-locked loop is used for improving stability and precision of the clock signals. A plurality of high-precision, stable clock signals can be generated for the clock switching system by means of a clock source.
Preferably, in step S1, the MUX multiplexer has a plurality of inputs and an output, and selects a corresponding clock signal output from the plurality of input clock signals according to a switching condition of each clock source. The clock switching system selects and outputs a plurality of clock signals by using the MUX multiplexer, so that the output of the plurality of clock signals can be effectively managed, the clock signals entering the clock switching sub-modules are ensured to exist, and each clock switching sub-module can normally finish clock switching.
Preferably, each binary code of the sel clock select signal corresponds to a respective clock signal. The clock switching system can be enabled to work stably and cooperatively by the sel clock selection signal.
Preferably, in step S2, the three-level registers include a data register, a status register, and a control register. Through the three-stage register, the transmission requirements of different clock signals can be met, and the accuracy of clock signal transmission is ensured.
Preferably, in step S2, the gating signal is used to control the output of the clock signal, when the gating signal is at a high level, the corresponding clock signal is output, and when the gating signal is at a low level, the corresponding clock signal is not output. The output of the clock signal can be effectively controlled through the gating signal, so that the clock switching system can normally complete the switching of the clock signal.
Preferably, in step S3, the falling edge trigger is triggered when the clk clock signal changes from high to low, and when triggered, the clk clock signal generates the feedback signal. The feedback signal is generated in a falling edge triggering mode, so that the problem that a clock source needs to be closed in a low power consumption mode is solved, and burrs generated in the switching process of two paths of clocks are avoided.
Preferably, in step S3, the indication of the completion of the switching of the clock signal includes a change in binary encoding of the sel clock select signal and a high level of the gating signal of the clock to be switched. By adding the clock signal switching completion flag, the problem of turning off the clock source before the clock signal switching is completed can be avoided.
Compared with the prior art, the invention has the following beneficial effects:
According to the technical scheme, the multi-clock switching can be realized by cascading the plurality of clock switching sub-modules, so that the requirement of switching more than two paths of clocks of the MCU is met, the problem that the clock source is required to be closed in a low-power consumption mode is solved, burrs are avoided in the switching process of the two paths of clocks, and meanwhile, the problem that the clock source is closed before the clock switching is completed can be avoided through the generated clock switching completion mark.
Drawings
FIG. 1 is a flow chart of a multi-clock domain, burr-free switching method supporting clock dynamic switching;
fig. 2 is a schematic diagram of a clock switching submodule supporting a multi-clock domain burr-free switching method of a clock dynamic switch.
Detailed Description
The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention.
The method comprises the steps of enabling a MUX multiplexer to output clk clock signals according to the switching conditions of clock sources, sending the clk clock signals to corresponding clock switching sub-modules, enabling sel clock selection signals corresponding to the clk clock signals to be output as gating signals of clk clock signals through an AND gate, a three-stage register and a one-stage register in the clock switching sub-modules, enabling non-signals of the sel clock selection signals to be output as gating signals of clocks to be switched through the AND gate and the three-stage register, enabling the clk clock signals to be turned off in a falling edge triggering mode, generating a feedback signal, enabling the clocks to be switched to be turned on through the gating signals after the clocks to be switched receive the feedback signals, and completing clock switching.
The method specifically comprises the following steps:
S1, generating a plurality of different clock signals through a plurality of clock sources, inputting the plurality of clock signals into a MUX multiplexer, wherein the MUX multiplexer is provided with a plurality of input ends and an output end, selecting a corresponding clock signal from the plurality of input clock signals to output according to a sel clock selection signal formed by switching signals of the clock sources, respectively corresponding to a corresponding clock signal by each binary code of the sel clock selection signal, and then transmitting the output clk clock signal to a corresponding clock switching submodule. The clock source comprises an oscillator, a crystal oscillator and a phase-locked loop, wherein the oscillator and the crystal oscillator are used for generating clock signals, the difference of the oscillator and the crystal oscillator is that the oscillator is an on-chip clock, the frequency precision and stability of the generated clock signals are relatively low, the crystal oscillator is an off-chip clock, the clock signals with high precision and high stability can be generated, and the phase-locked loop is used for improving the stability and precision of the clock signals. The MUX Multiplexer, i.e., multiplexer, is a logic circuit for selecting one of a plurality of input signals as an output signal, and in the present invention, it decides an output clock signal according to binary encoding of the sel clock selection signal.
In the method of the present invention, a plurality of high-precision and stable clock signals can be generated for the clock switching system through the clock source, the clock switching system uses the MUX multiplexer to select and output the plurality of clock signals, the output of the plurality of clock signals can be effectively managed, the plurality of clock signals can be ensured to be transmitted through a single output channel, meanwhile, the clock switching system can stably and coordinately work through the sel clock selection signal, the clock signals entering the clock switching submodule are ensured to exist, and therefore, each clock switching submodule can normally complete clock switching.
S2, in the clock switching submodule, after a sel clock selection signal corresponding to a clk clock signal passes through an and gate, a three-stage register and a one-stage register, outputting a non-signal of the sel clock selection signal, taking the non-signal of the sel clock selection signal as a gating signal of the clk clock signal, outputting the non-signal of the sel clock selection signal as a gating signal of a clock to be switched through the and gate and the three-stage register, and closing the clk clock signal through the gating signal to switch the clock signal. The three-stage register comprises a data register, a state register and a control register, wherein clk clock signals sequentially pass through the control register, the state register and the data register when transmitted.
In the embodiment, the three-stage register applied in the invention can meet the transmission requirements of different clock signals and ensure the accuracy and stability of clock signal transmission. The gating signal is used for controlling the output of the clock signal, when the gating signal is at a high level, the corresponding clock signal is output, and when the gating signal is at a low level, the corresponding clock signal is not output, and the output of the clock signal can be effectively controlled through the gating signal, so that the clock switching system can normally finish the switching of the clock signal.
And S3, when clock signal switching is carried out, the clk clock signal is turned off in a falling edge triggering mode through the gating signal, a feedback signal is generated, the feedback signal is output to the clock to be switched, the clock to be switched is turned on through the gating signal after receiving the feedback signal, switching is completed, meanwhile, each clock switching submodule is added with a corresponding signal for turning on or off each clock signal, and when any clock signal is not turned on, the corresponding clock enabling signal is in a low level. Wherein the falling edge trigger is triggered when the clk clock signal changes from high to low, and when triggered, the clk clock signal generates a feedback signal. The feedback signal is generated in a falling edge triggering mode, so that the problem that a clock source needs to be closed in a low power consumption mode is solved, and burrs generated in the switching process of two paths of clocks are avoided.
In this embodiment, the switching of a plurality of clock signals can be realized by cascading a plurality of clock switching sub-modules. Each clock switching sub-module can realize the switching of two paths of clock signals, and the gating signal of each clock signal is controlled by a feedback signal generated by the falling edge of the other clock signal. The gating signal is controlled by the other clock to ensure the isolation of the two clock signals in design, so that the running clock signal is closed by the gating signal when the clock signals are switched.
As shown in fig. 2, a schematic diagram of a clock switching submodule supporting a multi-clock domain non-burr switching method of a clock dynamic switch is shown, in which two clock switching submodules are cascaded, each clock switching submodule is composed of an and gate, an or gate and a three-stage register R, and includes a switching circuit clk_a_switch of clk_a, a switching circuit clk_b_switch of clk_b, a switching circuit clk_o_switch of clk_o, and a switching circuit clk_c_switch of clk_c. Taking three clock sources as an example in the figure, clk_a, clk_b and clk_c are three different clock signals generated by the three clock sources, the generated clock signals are input into the MUX multiplexer, and the clk clock signals are selected and output by sel [1:0] clock selection signals. The clock signal selects clk_a when the sel [1:0] clock selection signal is 2' b00, clk_b when the sel [1:0] clock selection signal is 2' b01, and clk_c when the sel [1:0] clock selection signal is 2' b 10. The clock switching system consists of two clock switching submodules, wherein the submodule 1 selects clk_a and clk_b according to the value of sel [0] and outputs clk_o, the circuit formula of the submodule can be simplified into clk_o= (. Sel [0] & clk_a) | (sel [0] & clk_b), when sel [0] is 0, clk_a is selected, when sel [0] is 1, clk_b is selected, the submodule 2 selects clk_o and clk_c according to the value of sel [1], and outputs clk_out, the circuit formula of the submodule can be simplified into clk_out= (. Sel [1] & clk_o) | (sel [1] & clk_c), when sel [1] is 0, clk_o is selected, and when sel [1] is 1, clk_c is selected. At the same time, the two clock switching submodules are added with sign signals for turning on or turning off clock signals, including clk_a_on, clk_b_on and clk_c_on, and when the corresponding clock signals are not turned on, the corresponding enabling signals are low.
In this embodiment, in order to avoid the wrong operation of turning off the clock source when the clock signal switching is not completed, a clock signal switching completion flag is added. The indication of the completion of the switching of the clock signal includes that the binary encoding of the sel clock select signal is changed and that the gating signal of the clock to be switched goes high. By adding the clock signal switching completion flag, the problem of turning off the clock source before the clock signal switching is completed can be avoided.
In summary, the invention can realize multi-clock switching by cascading a plurality of clock switching sub-modules, thereby not only solving the requirement of switching more than two paths of clocks of MCU, but also solving the problem of closing clock sources in a low power consumption mode, avoiding the generation of burrs in the switching process of two paths of clocks, and simultaneously avoiding the problem of closing the clock sources before the completion of clock switching by the generated clock switching completion mark, and having remarkable progress.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.

Claims (8)

1.一种支持时钟动态开关的多时钟域无毛刺切换方法，其特征在于，所述方法包括如下步骤：1. A method for glitch-free switching of multiple clock domains supporting dynamic clock switching, characterized in that the method comprises the following steps: S1、通过多个时钟源产生多个不同的时钟信号，并将多个时钟信号输入到MUX多路复用器中，MUX多路复用器根据每个时钟源的开关情况，输出一个相应的clk时钟信号，并将输出的这个clk时钟信号发送到对应的时钟切换子模块中；S1. Generate multiple different clock signals through multiple clock sources and input the multiple clock signals into the MUX multiplexer. The MUX multiplexer outputs a corresponding clk clock signal according to the switching status of each clock source and sends the output clk clock signal to the corresponding clock switching submodule; S2、在时钟切换子模块中，clk时钟信号对应的sel时钟选择信号经过and门、三级寄存器和一级寄存器后，输出sel时钟选择信号的非信号，并将sel时钟选择信号的非信号作为clk时钟信号的门控信号，然后将sel时钟选择信号的非信号再经过and门和三级寄存器输出为待切换时钟的门控信号；通过门控信号关闭clk时钟信号，进行时钟信号切换；S2. In the clock switching submodule, the sel clock selection signal corresponding to the clk clock signal passes through the AND gate, the three-stage register, and the first-stage register, and then outputs the negation signal of the sel clock selection signal, and uses the negation signal of the sel clock selection signal as the gating signal of the clk clock signal. The negation signal of the sel clock selection signal then passes through the AND gate and the three-stage register to output the gating signal of the clock to be switched; the clk clock signal is turned off by the gating signal to perform clock signal switching; 其中，级联了两个时钟切换子模块，且每个时钟切换子模块均由and门、or门和三级寄存器R组成，且包含了clk_a的切换电路clk_a_switch，clk_b的切换电路clk_b_switch，clk_o的切换电路clk_o_switch，以及clk_c的切换电路clk_c_switch；子模块1根据sel[0]值选择clk_a和clk_b，输出clk_o，子模块2根据sel[1]值选择clk_o和clk_c，输出clk_out；Among them, two clock switching sub-modules are cascaded, and each clock switching sub-module consists of an AND gate, an OR gate and a three-level register R, and includes the switching circuit clk_a_switch of clk_a, the switching circuit clk_b_switch of clk_b, the switching circuit clk_o_switch of clk_o, and the switching circuit clk_c_switch of clk_c; sub-module 1 selects clk_a and clk_b according to the value of sel[0] and outputs clk_o, and sub-module 2 selects clk_o and clk_c according to the value of sel[1] and outputs clk_out; S3、进行时钟信号切换时，clk时钟信号采用下降沿触发的方式通过门控信号被关闭后，产生一个反馈信号，并将反馈信号输出至待切换时钟，待切换时钟接收到反馈信号后，通过门控信号打开待切换时钟，完成切换；同时，每一个时钟切换子模块均增加了其对应的每一个时钟信号打开或关闭的标志信号，当任意时钟信号未打开时，其相应的时钟使能信号为低电平。S3. When switching the clock signal, the clk clock signal is turned off by the gating signal in a falling-edge triggered manner, and a feedback signal is generated. The feedback signal is output to the clock to be switched. After the clock to be switched receives the feedback signal, it turns on the clock to be switched through the gating signal to complete the switching. At the same time, each clock switching sub-module adds a flag signal for turning on or off each corresponding clock signal. When any clock signal is not turned on, its corresponding clock enable signal is low. 2.根据权利要求1所述的一种支持时钟动态开关的多时钟域无毛刺切换方法，其特征在于，步骤S1中，每个时钟源均包含：振荡器、晶振和锁相环；其中，振荡器和晶振均用于产生时钟信号，锁相环用于提高时钟信号的稳定性和精度。2. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 1 is characterized in that, in step S1, each clock source includes: an oscillator, a crystal oscillator and a phase-locked loop; wherein the oscillator and the crystal oscillator are both used to generate clock signals, and the phase-locked loop is used to improve the stability and accuracy of the clock signal. 3.根据权利要求1所述的一种支持时钟动态开关的多时钟域无毛刺切换方法，其特征在于，步骤S1中，MUX多路复用器具有多个输入端和一个输出端，它根据每个时钟源的开关情况从多个输入的时钟信号中选择一个相应的时钟信号输出。3. A multi-clock domain glitch-free switching method supporting dynamic clock switching according to claim 1, characterized in that in step S1, the MUX multiplexer has multiple input terminals and one output terminal, and it selects a corresponding clock signal from multiple input clock signals for output according to the switching status of each clock source. 4.根据权利要求3所述的一种支持时钟动态开关的多时钟域无毛刺切换方法，其特征在于，sel时钟选择信号的每一个二进制编码分别对应一个相应的时钟信号。4. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 3, wherein each binary code of the sel clock selection signal corresponds to a corresponding clock signal. 5.根据权利要求1所述的一种支持时钟动态开关的多时钟域无毛刺切换方法，其特征在于，步骤S2中，三级寄存器包括：数据寄存器、状态寄存器和控制寄存器。5. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 1, wherein in step S2, the three-level registers include: a data register, a status register, and a control register. 6.根据权利要求1所述的一种支持时钟动态开关的多时钟域无毛刺切换方法，其特征在于，步骤S2中，门控信号用于控制时钟信号的输出，当门控信号为高电平时，对应的时钟信号输出，门控信号为低电平时，对应的时钟信号不输出。6. A multi-clock domain glitch-free switching method supporting dynamic clock switching according to claim 1, characterized in that in step S2, a gating signal is used to control the output of the clock signal, when the gating signal is high, the corresponding clock signal is output, and when the gating signal is low, the corresponding clock signal is not output. 7.根据权利要求1所述的一种支持时钟动态开关的多时钟域无毛刺切换方法，其特征在于，步骤S3中，下降沿触发是在clk时钟信号由高电平变为低电平时触发，并且在触发时，clk时钟信号产生反馈信号。7. A multi-clock domain glitch-free switching method supporting dynamic clock switching according to claim 1, characterized in that in step S3, the falling edge trigger is triggered when the clk clock signal changes from a high level to a low level, and when triggered, the clk clock signal generates a feedback signal. 8.根据权利要求1所述的一种支持时钟动态开关的多时钟域无毛刺切换方法，其特征在于，步骤S3中，时钟信号切换完成的标志包括：sel时钟选择信号的二进制编码发生变化和待切换时钟的门控信号变为高电平。8. A glitch-free multi-clock domain switching method supporting dynamic clock switching according to claim 1, characterized in that in step S3, the sign of the completion of clock signal switching includes: the binary code of the sel clock selection signal changes and the gating signal of the clock to be switched becomes a high level.
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CN118011939A (en) * 2024-03-11 2024-05-10 江苏华创微系统有限公司 Low-power consumption management system of multi-power-domain MCU

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