CN119886004A

CN119886004A - Method, device, equipment and medium for adjusting holding time

Info

Publication number: CN119886004A
Application number: CN202411661331.XA
Authority: CN
Inventors: 叶艺聪; 李水军; 蒋华利; 李介民; 张善从
Original assignee: Xiamen Guoke Anxin Technology Co ltd
Current assignee: Xiamen Guoke Anxin Technology Co ltd
Priority date: 2024-11-20
Filing date: 2024-11-20
Publication date: 2025-04-25

Abstract

The disclosed embodiments relate to a method, device, equipment and medium for adjusting the hold time, the method comprising: obtaining timing analysis information of a circuit to be processed; wherein the timing analysis information comprises an abnormal endpoint identifier and hold time abnormality information corresponding to the abnormal endpoint identifier; determining a target number of delay adjustment units according to the hold time abnormality information; in the circuit to be processed, determining an abnormal path endpoint corresponding to the abnormal endpoint identifier, and inserting a target number of delay adjustment units at adjacent positions before the abnormal path endpoint to obtain an adjustment circuit. The disclosed embodiments reduce the error caused by the reconnection of interconnection lines, and reduce the influence of the delay adjustment unit on other paths, realize precise delay control of a specific path endpoint from multiple dimensions, and reduce the difficulty of achieving timing convergence.

Description

Method, device, equipment and medium for adjusting holding time

Technical Field

The disclosure relates to the field of computer technology, and in particular, to a method, a device, equipment and a medium for adjusting retention time.

Background

With the rapid development of the semiconductor industry, the feature size of the chip technology is smaller and smaller, the integration level of a single chip is increased, and the design difficulty of the chip is increased. The timing sequence convergence link in the physical design of the digital integrated circuit (INTEGRATED CIRCUIT, IC) is also due to factors such as higher chip main frequency, more complex internal data interaction, increased process angle and the like, and the difficulty is continuously improved.

In the related art, circuit adjustment is performed on an original chip according to a timing analysis result to achieve timing convergence. However, in the process of achieving timing sequence convergence, more interconnection lines are led in to be rewound, so that larger errors are caused, paths without timing sequence violations are affected, and difficulty in achieving timing sequence convergence is increased.

Disclosure of Invention

In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a method, an apparatus, a device, and a medium for adjusting a holding time.

The embodiment of the disclosure provides a method for adjusting retention time, which comprises the following steps:

Acquiring time sequence analysis information of a circuit to be processed, wherein the time sequence analysis information comprises an abnormal end point identifier and holding time abnormal information corresponding to the abnormal end point identifier;

Determining a target number of delay adjustment units according to the holding time abnormality information;

And in the circuit to be processed, determining an abnormal path end point corresponding to the abnormal end point mark, and inserting the delay adjusting units with the target number at the adjacent positions before the abnormal path end point to obtain an adjusting circuit.

The embodiment of the disclosure also provides a device for adjusting the holding time, which comprises:

The acquisition module is used for acquiring time sequence analysis information of the circuit to be processed, wherein the time sequence analysis information comprises an abnormal end point identifier and holding time abnormal information corresponding to the abnormal end point identifier;

A first determining module, configured to determine a target number of delay adjustment units according to the hold time anomaly information;

And the adjusting module is used for determining an abnormal path end point corresponding to the abnormal end point mark in the circuit to be processed, and inserting the delay adjusting units with the target number into the adjacent positions before the abnormal path end point to obtain an adjusting circuit.

The embodiment of the disclosure also provides electronic equipment, which comprises a processor, a memory for storing executable instructions of the processor, and the processor, wherein the processor is used for reading the executable instructions from the memory and executing the instructions to realize the method for adjusting the holding time provided by the embodiment of the disclosure.

The present disclosure also provides a computer-readable storage medium storing a computer program for executing the method of adjusting a retention time as provided by the embodiments of the present disclosure.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the advantages that the method comprises the steps of obtaining time sequence analysis information of a circuit to be processed, wherein the time sequence analysis information comprises abnormal end point identifiers and retention time abnormal information corresponding to the abnormal end point identifiers, determining the target number of delay adjustment units according to the retention time abnormal information, determining abnormal path end points corresponding to the abnormal end point identifiers in the circuit to be processed, and inserting the delay adjustment units of the target number at adjacent positions in front of the abnormal path end points to obtain the adjustment circuit. By adopting the technical scheme, the abnormal end point identification of the circuit to be processed and the corresponding maintenance time abnormal information thereof are acquired, the number of delay adjustment units is determined according to the maintenance time abnormal information, and the corresponding number of delay adjustment units are inserted into adjacent positions before the abnormal path end point corresponding to the abnormal end point identification, so that the adjustment circuit is obtained.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a flowchart illustrating a method for adjusting a retention time according to an embodiment of the disclosure;

FIG. 2 is a flowchart illustrating another method for adjusting retention time according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of an adjusting circuit according to an embodiment of the disclosure;

FIG. 4 is a flowchart illustrating another method for adjusting retention time according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a method for adjusting retention time according to an embodiment of the disclosure;

fig. 6 is a schematic structural diagram of a device for adjusting retention time according to an embodiment of the disclosure;

fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein, and it is apparent that the embodiments in the specification are only some, rather than all, of the embodiments of the present disclosure.

With the rapid development of the semiconductor industry, the characteristic size of the chip technology is smaller and smaller, the integration level of a single chip is increased, and the design and production difficulty of the chip are increased. The timing sequence convergence link in the physical design of the digital integrated circuit (INTEGRATED CIRCUIT, IC) is also due to factors such as higher chip main frequency, more complex internal data interaction, increased process angle and the like, and the difficulty is continuously improved. Therefore, in some projects that are urgent for the production of streaming chips but have timing convergence difficulties, it is often possible to choose to sacrifice a part of functions or reduce the dominant frequency to achieve the timing convergence goal.

Timing closure may be achieved by timing analysis, which may be implemented using a static timing analysis (STATIC TIMING ANALYSIS, STA) method, and checking in an electronic design automation (Electronic Design Automation, EDA) tool whether the Setup (Setup) time and Hold (Hold) time of the chip data path meet the requirements according to the definition in the constraint file.

In the related art, in order to achieve timing convergence, in an electronic design automation tool, according to an analysis result obtained in a timing analysis stage, the electronic design automation tool automatically achieves convergence of setup time and hold time by increasing a mode that a unit driver and the like do not change a logic function of a circuit, and finally outputs a timing convergence script. The timing closure script includes adjustments to the circuit by an electronic design automation tool during the closure timing.

In the related art, there are two problems, firstly, that there is a large error caused by reconnection of the interconnect line. Because parasitic parameters generated by reconnecting the real interconnection lines of the adjusted circuit cannot be simulated in the time convergence process of the time sequence analysis tool, larger errors can exist between the parasitic parameters and the real results, and therefore, the time sequence convergence under the real scene needs to be realized through multiple iterations. Second, new timing misconvergence may be introduced. When the timing sequence is converged through the electronic design automation tool, the timing sequence may be adjusted on some common paths, which eventually causes the timing sequence of other timing paths to be not converged, and increases the iteration times and convergence difficulty of the circuit.

In the related art, in the process of realizing timing sequence convergence, more interconnection lines are introduced to be reconnected to cause larger errors, and paths without timing violations originally exist are influenced, so that the difficulty of realizing the timing sequence convergence is increased.

In order to solve the above-mentioned problems, the embodiments of the present disclosure provide a method for adjusting a retention time, which is described below with reference to specific embodiments.

Fig. 1 is a flowchart of a method for adjusting a holding time according to an embodiment of the present disclosure, where the method for adjusting a holding time may be applied to an apparatus for adjusting a holding time. The means for adjusting the holding time may be implemented in software and/or hardware, which may generally be integrated in the electronic device. As shown in fig. 1, the method for adjusting the holding time includes:

and step 101, acquiring time sequence analysis information of a circuit to be processed, wherein the time sequence analysis information comprises an abnormal end point identifier and holding time abnormal information corresponding to the abnormal end point identifier.

The circuit to be processed may be a circuit in which the holding time corresponding to the component does not converge. The hold time may be the time after which the data signal actually remains stable after the trigger edge of the clock signal has arrived. The non-convergence of the hold time may be understood as the hold time being less than the hold time threshold, i.e. the time the data signal remains stable after the arrival of the trigger edge of the clock signal is too short. The hold time threshold may be a minimum time that the data signal needs to remain stable after the arrival of the trigger edge of the clock signal, and is not limited in this embodiment. The timing analysis information may be the result of analysis of the signal in the circuit to be processed over time.

The abnormal end point identification may be used to mark the abnormal path end point. The abnormal path end point may be a timing path end point at which the corresponding hold time does not converge. The timing path end may be a data end corresponding to when the data is loaded along a time edge after passing through the combinational logic, for example, the timing path end may include a data input of a register or a flip-flop. The holding time abnormality information may be used to characterize the case of the holding time corresponding to the abnormal path end point, and the present embodiment does not limit the holding time abnormality information, for example, the holding time abnormality information may include a specific value of the holding time, or the holding time abnormality information may include a holding time difference value, which may be a difference value between the current holding time of the abnormal path end point and a holding time threshold value.

In the embodiment of the disclosure, the device for adjusting the holding time may perform timing analysis on the circuit to be processed through a timing analysis tool and the like to obtain timing analysis information, where an abnormal endpoint identifier and holding time abnormal information corresponding to the abnormal endpoint identifier are recorded in the timing analysis information.

Step 102, determining the target number of the delay adjusting units according to the holding time abnormality information.

The delay adjustment unit may be an adjustment unit acting on the abnormal path end point, and may be used to repair a hold time violation of the abnormal path end point. The adjusting unit is also called a delay unit or a buffer unit, and can be used for adjusting the arrival time of the signals so that the related signals can meet the time sequence requirement of the circuit. The target number may be the number of delay adjustment units inserted into the circuit to be processed.

In the embodiment of the present disclosure, the holding time adjusting device may determine, according to the holding time abnormality information, the target number of delay adjusting units that delay the path abnormality end point. Or the holding time adjusting means may determine the target number of delay adjusting units for performing delay processing on the path abnormality end point based on the holding time abnormality information and the end point constraint condition. Wherein the endpoint constraint may set factors of the delay adjustment unit for influences in other dimensions than the hold time. The present embodiment does not limit the end constraint, and for example, the end constraint may include at least one of a margin of a hold time set in advance, a size of a remaining space around the path abnormality end point, and a setup time margin.

Specifically, the margin of the hold time may be used to adjust the hold time threshold, which may be a positive or negative number, for example, 6 ns if the hold time threshold is 5 ns and 1 ns, and 4 ns if the hold time threshold is 5 ns and 1 ns. The size of the remaining space around the path abnormality end point may be used to characterize the space currently available for the arrangement of delay adjustment units for the path abnormality end point, and it is understood that the space required for arranging the target number of delay adjustment units in the adjustment circuit needs to be contained in the remaining space.

The setup time margin may be a difference between a current setup time of the path anomaly endpoint and a setup time threshold. The setup time may be the time that the data signal actually remains stable until the arrival of the trigger edge of the clock signal. The non-convergence of the settling time may be understood as the settling time being less than the settling time threshold, i.e. the time for which the data signal remains stable is too short before the arrival of the triggering edge of the clock signal. The time threshold may be established as the minimum time that the data signal needs to remain substantially stable before the trigger edge of the clock signal arrives. It will be appreciated that the data signal arrives in advance or after delay, the effect on the hold time and the setup time check is opposite, and by setting the margin of the setup time, a prompt message of the setup time may be issued if the change value of the setup time exceeds the margin of the setup time after inserting the target number of delay adjustment units. Therefore, the normal implementation of the function is ensured by converging the holding time, and the user is prompted to carry out subsequent adjustment on the establishing time.

In the scheme, the flexible configuration of the method for adjusting the holding time is realized by setting the end constraint condition, so that the method for adjusting the holding time can be suitable for different application scenes, and the application range of the method is enlarged.

Fig. 2 is a flowchart of another method for adjusting a holding time according to an embodiment of the present disclosure, as shown in fig. 2, in some embodiments of the present disclosure, before determining a target number of delay adjustment units according to holding time anomaly information, the method for adjusting a holding time further includes:

Step 201, performing time sequence analysis on the serial delay chain through a time sequence analysis tool to obtain serial delay duration of the serial delay chain, wherein the serial delay chain comprises a preset number of serial adjustment units to be measured of the same type.

The time sequence analysis tool is a software tool for performing time sequence analysis on the circuit, and the time sequence analysis tool can have a static time sequence analysis function. The number of the series delay chains is not limited, and if the number of the series delay chains is multiple, measurement of the unit delay time lengths of the multiple types of the to-be-measured adjustment units can be realized. The series delay duration may be the delay duration of the series delay chain as a whole. The unit delay time may be the delay time of a single unit to be adjusted. The preset number may be a preset number of to-be-measured adjustment units connected in series in the series delay chain, and the preset number is not limited in this embodiment, and may be, for example, 5 or 7. Because the error of the series connection determining unit delay time length is mainly generated by two measuring and adjusting units positioned at two ends, the error of the unit delay time length can be reduced by increasing the preset quantity.

The to-be-measured adjusting units can be adjusting units for measuring the unit delay time length, and the unit delay time lengths corresponding to the same type of to-be-measured adjusting units are the same. The adjustment unit to be measured may comprise a delay adjustment unit and/or a candidate adjustment unit. Optionally, a preset delay time length of the to-be-measured adjusting unit may be recorded in a preset document, and the adjusting device of the holding time may select and determine the delay adjusting unit based on the preset delay time length and the holding time abnormality information, and then determine a unit delay time length with higher accuracy of the delay adjusting unit through a timing analysis tool.

In this embodiment, the holding time adjusting device may perform analog multistage serial connection on a preset number of to-be-measured adjusting units of the same type, to obtain a serial delay chain corresponding to the to-be-measured adjusting units of the same type. Further, the serial delay time length of the serial delay chain is obtained by carrying out time sequence analysis on the serial delay chain through a time sequence analysis tool.

Step 202, determining the unit delay duration of a single unit to be adjusted according to the series delay duration and the preset number.

In this embodiment, the holding time adjusting device may divide the serial delay time length by a preset number, and use the divided result as the unit delay time length of the single to-be-measured adjusting unit. If the number of the series delay chains is multiple, the above processing can be performed on the multiple series delay chains respectively, so as to obtain the unit delay time lengths of different types of to-be-measured adjustment units corresponding to each series delay chain.

In the scheme, after the plurality of to-be-measured adjusting units are connected in series, the length of time is prolonged as a whole, so that the error influence caused by the to-be-measured adjusting units at two ends is reduced, and the accuracy of the unit delay time of the finally determined single to-be-measured adjusting unit is improved.

In some embodiments of the present disclosure, the delay adjustment unit is a predetermined single type of adjustment unit, and the adjustment unit to be measured includes the delay adjustment unit. In this embodiment, the delay time length of the delay adjustment unit is recorded in the preset document, where the accuracy of the delay time length is low, but the delay time length may be used as a basis for selecting the adjustment unit, the adjustment device for the holding time may determine the delay adjustment unit according to the delay time length recorded in the preset document and the abnormal information of the holding time, connect a preset number of delay adjustment units in series to obtain a serial delay chain, determine the serial delay time length of the serial delay chain by using a timing analysis tool, and determine the unit delay time length of a single delay adjustment unit according to the serial delay time length and the preset number.

Correspondingly, determining the target number of the delay adjusting units according to the holding time abnormality information comprises dividing the holding time difference value and the unit delay time length of the delay adjusting units and rounding up to obtain the target number, wherein the holding time difference value is determined according to the holding time abnormality information.

In this embodiment, if the holding time abnormality information is a specific value of the holding time, the holding time adjustment device may subtract the holding time abnormality information from the holding time threshold value to obtain the holding time difference value. If the holding time abnormality information is a holding time difference value, the holding time adjusting device may use the holding time abnormality information as the holding time difference value. Further, the holding time adjusting device may divide the holding time difference by the unit delay time length of the currently selected delay adjusting unit and round up the unit delay time length to obtain the target number. For example, if the holding time difference is 5 ns, the unit delay period is 2 ns, and the target number is 3.

In the scheme, the delay adjusting unit is of a single type, the error between the delay time length realized by the single type delay adjusting unit in an actual circuit and the delay time length calculated based on the unit delay time length is small, and the accurate adjustment of the delay time length is realized.

In some embodiments of the present disclosure, the delay adjustment unit is an adjustment unit obtained by screening based on a plurality of types of candidate adjustment units, and the adjustment unit to be measured includes the candidate adjustment unit. The candidate adjustment unit may be an alternative adjustment unit, and the candidate adjustment unit may be of a plurality of types. In this embodiment, a plurality of candidate adjustment units are predetermined, and the adjustment device for the holding time may take each candidate adjustment unit as an adjustment unit to be measured, connect a preset number of the candidate adjustment units in series to obtain a serial delay chain, determine a serial delay duration of the serial delay chain through a timing analysis tool, and determine a unit delay duration of a single candidate adjustment unit according to the serial delay duration and the preset number. Obtaining the unit delay time lengths corresponding to different types of candidate adjustment units.

Accordingly, determining the target number of delay adjustment units according to the hold time anomaly information includes:

The method comprises the steps of sequentially determining unit delay time as current delay time and a holding time difference value as a current dividend according to the sequence of unit delay time from big to small, dividing the current dividend and the current delay time to obtain a quotient and a remainder, determining a candidate adjustment unit corresponding to the current delay time as a delay adjustment unit and determining the quotient as a target number of the delay adjustment units if the quotient is not smaller than 1, determining the next unit delay time as a new current delay time if the remainder is not smaller than the minimum unit delay time, determining the remainder as a new current dividend, and returning to determine a new quotient and a new remainder until the new remainder is smaller than the minimum unit delay time.

The current delay time may be a unit delay time currently being a divisor. The current dividend may be a delay duration for which the delay adjustment unit to be currently allocated is delay-implemented. The quotient may be an integer portion of the quotient. The minimum unit delay period may be a minimum value of a plurality of unit delay periods.

In this embodiment, after determining the unit delay duration corresponding to each candidate adjustment unit, the adjustment device for the holding time may sequentially determine each unit delay duration as the current delay duration according to the order of the unit delay duration values from large to small. And, the hold time difference is determined to be the first current dividend.

Further, for each current delay period, the holding time adjusting means may divide the current dividend by the current delay period, take the integer part of the quotient as the quotient, and take the part which cannot be divided as the remainder. Further, whether the quotient is smaller than 1 is judged, if yes, the next unit delay time length is determined to be the new current delay time length, the remainder is determined to be the new current dividend, and the new quotient and the new remainder are determined in a returning mode until the new remainder is smaller than the minimum unit delay time length.

And if the quotient is not less than 1, determining the candidate adjustment unit corresponding to the current delay time length as a delay adjustment unit, and determining the quotient as the target number corresponding to the delay adjustment unit. Further, whether the remainder is smaller than the minimum unit delay time length is judged, if the remainder is not smaller than the minimum unit delay time length, the next unit delay time length sequenced after the current delay time length according to the size is determined to be a new current delay time length, the remainder is determined to be a new current dividend, and the new quotient and the new remainder are returned to be determined until the new remainder is smaller than the minimum unit delay time length. If the remainder is smaller than the minimum unit delay time length, the iteration process of determining the delay adjustment units is terminated, and the target number of the delay adjustment units corresponding to the current delay time length is accumulated by 1, or the candidate adjustment units corresponding to the minimum unit delay time length are determined as the delay adjustment units, and the target number of the delay adjustment units corresponding to the minimum unit delay time length is accumulated by 1. For example, taking the remainder of the last iteration determination as 0 as an example, if the holding time difference is 5 ns, the unit delay time of the candidate adjustment unit includes 4 ns, 3 ns, 2 ns, and 1 ns, and the delay adjustment unit includes 1 adjustment unit having a unit delay time of 4 ns and 1 adjustment unit having a unit delay time of 1 ns.

In the scheme, the delay adjusting units with higher coverage degree of the holding time difference and the target number of the delay adjusting units are determined, and the candidate adjusting units with larger delay time length of the units are preferentially selected as the delay adjusting units, so that the occupied space of the delay adjusting units is reduced.

And step 103, determining an abnormal path end point corresponding to the abnormal end point mark in the circuit to be processed, and inserting delay adjusting units with target quantity at adjacent positions before the abnormal path end point to obtain an adjusting circuit.

In the embodiment of the disclosure, the adjusting device for the holding time may determine an abnormal path end point in the circuit to be processed according to the abnormal end point identifier, and insert a target number of delay adjusting units into a position of the circuit to be processed, which is located before the abnormal path end point and is adjacent to the abnormal path end point, to obtain an adjusting circuit after the circuit to be processed is adjusted. The adjacent position may be a position where the timing is before the end point of the abnormal path, and does not pass through the common path and does not pass through other components. Fig. 3 is a schematic diagram of an adjusting circuit according to an embodiment of the disclosure, as shown in fig. 3, including a data terminal of the flip-flop 2 and a data terminal of the flip-flop 3 at an abnormal path end point. In the adjustment circuit, a delay adjustment unit is inserted before the data terminal of the flip-flop 2, and a delay adjustment unit is inserted before the data terminal of the flip-flop 3.

In some embodiments of the present disclosure, inserting a target number of delay adjustment units at positions adjacent to before an end point of an abnormal path to obtain an adjustment circuit includes:

And if the timing analysis tool determines that the intermediate circuit meets the timing convergence condition, determining the intermediate circuit as an adjusting circuit.

The timing convergence condition may be a preset condition for implementing timing convergence by using a characterization circuit, and the embodiment does not limit the timing convergence condition, for example, the timing convergence condition may include a hold time not greater than a hold time threshold, and the timing convergence condition may further include a setup time not greater than a setup time threshold.

In this embodiment, the hold time adjusting device may insert the target number of delay adjusting units into the position before and adjacent to the end point of the abnormal path by the time series analyzing tool, to obtain the intermediate circuit. The timing analysis tool does not re-route the delay adjustment unit after it is inserted into the circuit to be processed, and thus the intermediate circuit does not take into account parasitic parameters of the interconnect lines newly added by the circuit to be processed due to the insertion of the delay adjustment unit. Further, the adjustment device of the holding time can determine whether the intermediate circuit meets the convergence condition through a time sequence analysis tool, and if so, the intermediate circuit is determined to be an adjustment circuit.

In some embodiments of the present disclosure, determining, by a timing analysis tool, that an intermediate circuit satisfies a timing closure condition includes:

And if the establishment time is not less than the establishment time threshold and the holding time is not less than the holding time threshold, determining that the intermediate circuit meets the timing sequence convergence condition.

In this embodiment, the device for adjusting the holding time may perform a time sequence analysis on the intermediate circuit by using a time sequence analysis tool, so as to obtain the setup time and the holding time of each time sequence path end point in the intermediate circuit. Judging whether the establishing time is smaller than the establishing time threshold value, if at least one establishing time is smaller than the establishing time threshold value, indicating that the establishing time corresponding to the corresponding time sequence path end point is not converged, and determining that the intermediate circuit does not meet the time sequence convergence condition. If all the setup times are not less than the setup time threshold, the intermediate circuit is indicated to meet the timing sequence convergence condition of the setup time dimension.

And judging whether the holding time is smaller than a holding time threshold value, if at least one holding time is smaller than the holding time threshold value, indicating that the holding time corresponding to the corresponding time sequence path end point is not converged, and determining that the intermediate circuit does not meet a time sequence convergence condition. If all the holding times are not smaller than the holding time threshold value, the intermediate circuit is indicated to meet the timing convergence condition of the holding time dimension. If the intermediate circuit meets the timing closure condition, determining that the intermediate circuit meets the timing closure condition.

Based on the calculation principle of the time sequence analysis method, the data path can be the time spent in the combination logic, the shorter the data path is, the easier the establishment time threshold is met, the harder the retention time threshold is met, and the longer the data path is, the opposite is. In terms of clock frequency, the higher the clock frequency is, the harder the establishment time threshold is met, the higher the clock frequency is, the higher the hold time is, but the higher the frequency requires a shorter data path to meet the establishment time threshold, on the basis, the higher the clock frequency is, the opposite influence of the data path on the establishment time and the hold time is combined, and the hold time convergence difficulty is also indirectly improved. Based on the above analysis, it can be determined that, in this embodiment, the delay adjustment units that are adjacent to each other and added with the target number before the end of the abnormal path have an influence on not only the hold time of the circuit but also the setup time of the circuit, so that both the setup time and the hold time are verified, so that the finally determined adjustment circuit converges in both dimensions of the setup time and the hold time.

The method for adjusting the holding time comprises the steps of obtaining time sequence analysis information of a circuit to be processed, wherein the time sequence analysis information comprises an abnormal end point identifier and holding time abnormal information corresponding to the abnormal end point identifier, determining the target number of delay adjustment units according to the holding time abnormal information, determining an abnormal path end point corresponding to the abnormal end point identifier in the circuit to be processed, and inserting the delay adjustment units of the target number at adjacent positions in front of the abnormal path end point to obtain an adjustment circuit. By adopting the technical scheme, the abnormal end point identification of the circuit to be processed and the corresponding maintenance time abnormal information thereof are acquired, the number of delay adjustment units is determined according to the maintenance time abnormal information, and the corresponding number of delay adjustment units are inserted into adjacent positions before the abnormal path end point corresponding to the abnormal end point identification, so that the adjustment circuit is obtained.

Fig. 4 is a flowchart of another method for adjusting a holding time according to an embodiment of the disclosure, as shown in fig. 4, in some embodiments of the disclosure, the method further includes:

in step 401, a physical design tool is used to perform physical implementation processing on the adjustment circuit, so as to obtain a physical circuit.

The physical design tool may be a tool for physical design and Place and Route (PR) of a circuit, among other things. After the target number of delay adjustment units are inserted into the adjustment units through the physical design tool, layout wiring related to the delay adjustment units is carried out, and the parasitic parameters of the newly added interconnection lines are considered by the circuit determined by the physical design tool, wherein the parasitic parameters comprise one or more of parasitic capacitance, parasitic resistance and parasitic inductance. The physical circuit may be a circuit obtained through physical design, layout and wiring, etc., and may represent an actual physical structure of the circuit.

In this embodiment, the tool for performing physical implementation and the tool for performing timing analysis in the digital back-end flow may be different electronic design automation tools. Therefore, after the adjusting circuit is obtained, the adjusting device of the holding time can output a circuit script which is adjusted by the circuit to be processed to obtain the adjusting circuit, the circuit script is led into a physical design tool, the physical design tool is used for carrying out component arrangement, winding and the like on the adjusted part of the circuit again, and then the extraction of interconnection lines and parasitic parameters is carried out, so that the physical circuit is obtained.

In step 402, if the physical circuit satisfies the timing convergence condition, the physical circuit is determined as the target circuit.

The target circuit may be a circuit which satisfies a timing convergence condition and is physically completed.

In this embodiment, the device for adjusting the holding time may perform a time sequence analysis on the physical circuit by using a time sequence analysis tool, so as to obtain the setup time and the holding time of each time sequence path end point in the physical circuit. Judging whether the establishment time is smaller than an establishment time threshold value, if at least one establishment time is smaller than the establishment time threshold value, indicating that the establishment time corresponding to the corresponding time sequence path end point is not converged, and determining that the physical circuit does not meet the time sequence convergence condition. If all the setup times are not less than the setup time threshold, the physical circuit is indicated to meet the timing convergence condition of the setup time dimension.

And judging whether the holding time is smaller than a holding time threshold value, if at least one holding time is smaller than the holding time threshold value, indicating that the holding time corresponding to the corresponding time sequence path end point is not converged, and determining that the physical circuit does not meet the time sequence convergence condition. If all the holding times are not smaller than the holding time threshold, the physical circuit is indicated to meet the timing convergence condition of the holding time dimension. If the time dimension and the hold time dimension are established, the physical circuit meets the timing convergence condition, the physical circuit is determined to meet the timing convergence condition, and the physical circuit is determined to be a target circuit.

And step 403, if the physical circuit does not meet the timing convergence condition in the retention time dimension, using the physical circuit as a new circuit to be processed, and determining a new physical circuit corresponding to the new circuit to be processed until the new physical circuit meets the timing convergence condition.

In this embodiment, if at least one holding time of the physical circuit is less than the holding time threshold, which indicates that the holding time corresponding to the end point of the corresponding timing path is not converged, it is determined that the physical circuit does not satisfy the timing convergence condition in the holding time dimension. The method comprises the steps of taking a physical circuit as a new circuit to be processed, returning to acquire new time sequence analysis information of the new circuit to be processed, determining new target number of delay adjustment units according to new holding time abnormality information, determining new abnormal path end points corresponding to new abnormal end point identifiers in the new circuit to be processed, and inserting new delay adjustment units of the new target number at adjacent positions before the new abnormal path end points to obtain a new adjustment circuit. Further, the new adjusting circuit is subjected to physical implementation treatment through a physical design tool to obtain a new physical circuit until the new physical circuit meets a timing sequence convergence condition or until the iteration times of the physical circuit are determined to reach a preset iteration threshold.

Optionally, the method for adjusting the holding time further comprises generating and sending setup time prompt information to prompt a user to optimize the prompt information of the physical circuit if the physical circuit does not meet the timing convergence condition in the setup time dimension.

In the above scheme, after the delay adjustment unit is connected in series in a single or multiple stages, the delay adjustment unit is disposed near the abnormal path end point after being processed by a physical implementation tool before being inserted into the abnormal path end point, and the interconnection line between the delay adjustment unit and the abnormal path end point is extremely short, so that the delay generated by reconnecting the interconnection line is extremely small. Therefore, after the timing analysis tool is reintroduced, the obtained judgment result of timing convergence has higher consistency with the judgment result obtained by the previous calculation, and the iteration times and the iteration time of the timing convergence can be effectively reduced.

Next, a method for adjusting a retention time in an embodiment of the present disclosure will be further described by way of a specific example, and fig. 5 is a schematic diagram of a method for adjusting a retention time according to an embodiment of the present disclosure, as shown in fig. 5:

Firstly, carrying out time sequence analysis on a circuit to be processed through a time sequence analysis tool to acquire an abnormal end point identifier and holding time abnormal information. The abnormal end point identifier corresponds to a time sequence abnormal end point, which can be a data input end of a trigger, and the holding time abnormal information can be a difference value between the holding time corresponding to the time sequence abnormal end point and a holding time threshold value. Further, a delay adjustment unit is selected and a unit delay time of the delay adjustment unit is determined. The delay adjusting unit may be of a type that the unit delay time length is a unit delay time length of each unit adjusting unit when a plurality of delay adjusting units are connected in series in a multistage manner by analog calculation in the timing analysis tool.

Further, the target number of delay adjustment units is determined based on the hold time difference and the unit delay time length. Specifically, the holding time adjusting device may divide the holding time difference by the unit delay time length and round up the holding time difference to obtain the target number of delay adjusting units to be inserted at the end point of the abnormal path. Further, the delay adjusting units with the target number are inserted into adjacent positions before the end point of the abnormal path through a time sequence analyzing tool, so that an adjusting circuit is obtained, and time sequence convergence verification is carried out on the adjusting circuit. Thus, it is determined whether the hold time converges, and it is determined whether the insertion of the delay adjusting unit causes the non-convergence of the setup time. Further, the circuit script is imported into a physical implementation tool. Specifically, the device for adjusting the retention time may output a circuit script for implementing timing closure, import the circuit script into a physical implementation tool, determine a physical circuit through the physical implementation tool, and determine whether the physical circuit meets a timing closure condition.

In the above-described scheme, the delay adjustment unit is inserted at the end point of the abnormal path (for example, the data input terminal of the register). And the delay adjusting units are connected in series to integrally determine the series delay time length, and the unit delay time length of a single delay adjusting unit is determined based on the series delay time length, so that the accuracy of the unit delay time length is improved.

And, the non-convergence of other timing path end points is not caused. Specifically, delay adjustment units are inserted adjacent to the end point of the abnormal path so that the delay adjustment units affect only the timing of the end point of the abnormal path. Errors caused by reconnection of the interconnection lines are reduced. Specifically, since the delay adjusting units are connected in series in single or multiple stages, before the direct adjacent delay adjusting units are inserted into the abnormal sequence path end points, the delay adjusting units can be placed nearby at the positions close to the abnormal path end points in physical implementation dimension, and the interconnection lines between the trigger and the delay adjusting units are extremely short, and the delay is extremely small, when the physical circuit is led into the time sequence analyzing tool, the obtained time sequence analyzing result has higher consistency with the time sequence analyzing result of the adjusting circuit, and the iteration times and the iteration time of time sequence convergence can be effectively reduced.

And, flexible configuration is realized. Specifically, different delay adjustment units may be selected according to the holding time difference, the end point constraint condition, and the like. For example, the endpoint constraint may include a margin for the hold time by which the hold time threshold may be flexibly adjusted to achieve different hold time convergence results. The determination of the target number of delay adjustment units may additionally incorporate a setup time difference, which may be the difference between the current setup time of the abnormal path end point and a setup time threshold. Optionally, the method for adjusting the holding time can be executed in the electronic design automation tool through a command line, so that the method for adjusting the holding time is more convenient to execute.

The method for adjusting the holding time can quickly and effectively converge the holding time, meanwhile, the influence on other time sequence path end points is avoided, the iteration time is shortened, and the convergence process is accelerated.

Fig. 6 is a schematic structural diagram of a device for adjusting a retention time according to an embodiment of the present disclosure, where the device may be implemented by software and/or hardware, and the device may be integrated into an electronic device.

As shown in fig. 6, the holding time adjustment device includes:

The acquisition module 601 is configured to acquire timing analysis information of a circuit to be processed, where the timing analysis information includes an abnormal endpoint identifier and retention time abnormal information corresponding to the abnormal endpoint identifier;

a first determining module 602, configured to determine a target number of delay adjustment units according to the hold time anomaly information;

And the adjusting module 603 is configured to determine, in the circuit to be processed, an abnormal path end point corresponding to the abnormal end point identifier, and insert the target number of delay adjusting units at positions adjacent to the abnormal path end point, to obtain an adjusting circuit.

Optionally, the device for adjusting the holding time further includes:

the time sequence analysis module is used for carrying out time sequence analysis on the serial delay chain by a time sequence analysis tool before the target number of the delay adjustment units is determined according to the holding time abnormality information to obtain the serial delay time length of the serial delay chain, wherein the serial delay chain comprises a preset number of the same type of adjustment units to be measured which are connected in series;

And the second determining module is used for determining the unit delay duration of the single to-be-measured adjusting unit according to the serial delay duration and the preset quantity.

Optionally, the delay adjusting unit is a predetermined single type of adjusting unit, and the adjusting unit to be measured includes the delay adjusting unit;

Accordingly, the first determining module 602 is configured to:

Dividing the holding time difference value and the unit delay time length of the delay adjusting unit and rounding up to obtain the target number, wherein the holding time difference value is determined according to the holding time abnormality information.

Optionally, the delay adjusting unit is an adjusting unit obtained by screening based on a plurality of types of candidate adjusting units, and the to-be-measured adjusting unit comprises the candidate adjusting unit;

Accordingly, the first determining module 602 is configured to:

sequentially determining the unit delay time length as the current delay time length and the holding time difference value as the current dividend according to the sequence of the unit delay time length from big to small, wherein the holding time difference value is determined according to the holding time abnormality information;

Dividing the current dividend and the current delay time length to obtain a quotient and a remainder, if the quotient is not less than 1, determining the candidate adjustment unit corresponding to the current delay time length as the delay adjustment unit, and determining the quotient as the target number of the delay adjustment unit;

And if the remainder is not smaller than the minimum unit delay time, determining the next unit delay time as a new current delay time, determining the remainder as a new current dividend, and returning to determining a new quotient and a new remainder until the remainder is smaller than the minimum unit delay time.

Optionally, the inserting the target number of the delay adjustment units at positions adjacent to the position before the end point of the abnormal path, to obtain an adjustment circuit, includes:

inserting the target number of delay adjustment units adjacently before the end point of the abnormal path through a time sequence analysis tool to obtain an intermediate circuit;

and if the timing analysis tool determines that the intermediate circuit meets the timing convergence condition, determining the intermediate circuit as the adjusting circuit.

Optionally, the determining, by the timing analysis tool, that the intermediate circuit meets a timing convergence condition includes:

performing time sequence analysis on the intermediate circuit through the time sequence analysis tool to obtain the establishment time and the holding time corresponding to each time sequence path end point in the intermediate circuit;

and if the establishing time is not less than the establishing time threshold and the maintaining time is not less than the maintaining time threshold, determining that the intermediate circuit meets the timing sequence convergence condition.

Optionally, the device for adjusting the holding time further includes:

The physical description is used for carrying out physical realization processing on the adjusting circuit through a physical design tool to obtain a physical circuit;

And a third determining module, configured to, if the physical circuit does not meet the timing sequence convergence condition in the retention time dimension, determine a new physical circuit corresponding to the new to-be-processed circuit by using the physical circuit as the new to-be-processed circuit until the new physical circuit meets the timing sequence convergence condition.

It should be noted that, the apparatus 600 for adjusting a retention time shown in fig. 6 may perform the steps in the foregoing embodiment of the method for adjusting a retention time, and implement the processes and effects in the foregoing embodiment of the method for adjusting a retention time, which are not described herein.

Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. As shown in fig. 7, an electronic device 700 includes one or more processors 701 and memory 702.

The processor 701 may be a Central Processing Unit (CPU) or other form of processing unit having hold time adjustment capability and/or instruction execution capability, and may control other components in the electronic device 700 to perform desired functions.

Memory 702 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program instructions may be stored on the computer readable storage medium that can be executed by the processor 701 to implement the methods of adjusting the retention time and/or other desired functions of the embodiments of the present disclosure described above. Various contents such as an input signal, a signal component, a noise component, and the like may also be stored in the computer-readable storage medium.

In one example, the electronic device 700 may also include an input device 703 and an output device 704, which are interconnected by a bus system and/or other form of connection mechanism (not shown).

In addition, the input device 703 may also include, for example, a keyboard, a mouse, and the like.

The output device 704 may output various information to the outside, including the determined distance information, direction information, and the like. The output device 704 may include, for example, a display, speakers, a printer, and a communication network and remote output apparatus connected thereto, etc.

Of course, only some of the components of the electronic device 700 that are relevant to the present disclosure are shown in fig. 7 for simplicity, components such as buses, input/output interfaces, etc. are omitted. In addition, the electronic device 700 may include any other suitable components depending on the particular application.

In addition to the methods and apparatus described above, embodiments of the present disclosure may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the method of adjusting the hold time provided by the embodiments of the present disclosure.

The computer program product may write program code for performing the operations of embodiments of the present disclosure in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Further, embodiments of the present disclosure may also be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the method of adjusting the retention time provided by the embodiments of the present disclosure.

The computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of a readable storage medium include an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of adjusting a retention time, comprising:

2. The method according to claim 1, wherein before the determining of the target number of delay adjustment units from the hold time abnormality information, the method further comprises:

Performing time sequence analysis on a serial delay chain through a time sequence analysis tool to obtain serial delay time length of the serial delay chain, wherein the serial delay chain comprises a preset number of serial adjustment units to be tested in the same type;

and determining the unit delay duration of the single to-be-measured adjusting unit according to the serial delay duration and the preset quantity.

3. The method according to claim 2, wherein the delay adjustment unit is a predetermined single type of adjustment unit, the adjustment unit to be measured comprising the delay adjustment unit;

correspondingly, the determining the target number of the delay adjusting units according to the holding time abnormality information comprises the following steps:

4. The method according to claim 2, wherein the delay adjustment unit is an adjustment unit obtained by screening based on a plurality of types of candidate adjustment units, and the adjustment unit to be measured includes the candidate adjustment unit;

And if the remainder is not smaller than the minimum unit delay time, determining the next unit delay time as a new current delay time, determining the remainder as a new current dividend, and returning to determining a new quotient and a new remainder until the new remainder is smaller than the minimum unit delay time.

5. The method according to claim 1, wherein the inserting the target number of the delay adjustment units at the positions adjacent before the abnormal path end point, to obtain an adjustment circuit, includes:

6. The method of claim 5, wherein the determining, by the timing analysis tool, that the intermediate circuit satisfies a timing closure condition comprises:

7. The method of claim 5, wherein the method further comprises:

Performing physical implementation treatment on the adjusting circuit through a physical design tool to obtain a physical circuit;

And if the physical circuit does not meet the time sequence convergence condition in the retention time dimension, taking the physical circuit as a new circuit to be processed, and determining a new physical circuit corresponding to the new circuit to be processed until the new physical circuit meets the time sequence convergence condition.

8. A holding time adjustment device, comprising:

9. An electronic device, the electronic device comprising:

A processor;

A memory for storing the processor-executable instructions;

The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for adjusting a retention time according to any one of the preceding claims 1-7.

10. A computer-readable storage medium, characterized in that the storage medium stores a computer program for executing the method of adjusting the holding time according to any one of the preceding claims 1-7.