CN119889202A - Signal transmitting circuit, chip and electronic device - Google Patents

Abstract

The application discloses a signal transmitting circuit, a chip and electronic equipment, and belongs to the technical field of display. The signal transmission circuit comprises a first signal driving circuit and a second signal driving circuit, wherein the first signal driving circuit is used for transmitting an output differential signal in a CML driving mode according to a first input differential signal when the first signal driving circuit is disconnected from the second signal driving circuit, the second signal driving circuit does not work, and the first signal driving circuit and the second signal driving circuit are used for transmitting an output differential signal in an LVDS driving mode according to the first input differential signal when the first signal driving circuit is communicated with the second signal driving circuit. The signal transmitting circuit can support switching of two driving modes, namely an LVDS driving mode and a CML driving mode, so that the signal transmitting circuit can be compatible with electrical interface standards in different driving modes, and the flexibility of the signal transmitting circuit is improved.

Description

Signal transmitting circuit, chip and electronic device

Technical Field

The present application relates to the field of display technologies, and in particular, to a signal transmitting circuit, a chip, and an electronic device.

Background

In SerDes (Serializer-Deserializer), the signal transmitting circuit of the SerDes transmitting Terminal (TX) typically only supports a single drive mode. Thus, in the case where another driving mode is required, the signal transmission circuit needs to be redesigned.

Disclosure of Invention

The application provides a signal transmitting circuit, a chip and an electronic device, which can support two driving modes.

In a first aspect, a signal transmission circuit is provided, the signal transmission circuit including a first signal driving circuit and a second signal driving circuit;

when the first signal driving circuit is disconnected from the second signal driving circuit, the first signal driving circuit is configured to send an output differential signal in a CML (Current Mode Logic ) driving mode according to a first input differential signal, and the second signal driving circuit does not operate;

The first signal driving circuit and the second signal driving circuit are configured to transmit an output differential signal in an LVDS (Low Voltage differential signaling) driving mode according to the first input differential signal, in a case where the first signal driving circuit is in communication with the second signal driving circuit.

In one possible implementation manner, the signal sending circuit further comprises a first control circuit and a second control circuit, wherein the first control circuit is used for controlling an input signal of the second signal driving circuit, the second control circuit is used for controlling a connection mode of the first signal driving circuit, the first signal driving circuit is disconnected from the second signal driving circuit when the input signal of the second signal driving circuit is a first level and the connection mode of the first signal driving circuit is a first connection mode, and the first signal driving circuit is communicated with the second signal driving circuit when the input signal of the second signal driving circuit is the first input differential signal and the connection mode of the first signal driving circuit is a second connection mode.

In one possible implementation manner, the first control circuit comprises a signal generating circuit, a first switch and a second switch, wherein the signal generating circuit is used for generating the signal of the first level, the first switch is used for controlling the connection and disconnection of the second signal driving circuit and the signal end of the first input differential signal, and the second switch is used for controlling the connection and disconnection of the second signal driving circuit and the signal generating circuit.

In one possible implementation manner, the first input differential signal includes a first input positive signal and a first input negative signal, the first signal driving circuit includes a first negative signal driving circuit and a first positive signal driving circuit, the first negative signal driving circuit is connected with a signal end of the first input negative signal, the first positive signal driving circuit is connected with a signal end of the first input positive signal, the first connection manner is that the first negative signal driving circuit and the first positive signal driving circuit are both connected with a ground end, and the second connection manner is that the first negative signal driving circuit and the first positive signal driving circuit are connected.

In one possible implementation manner, the first input differential signal comprises a first input positive signal and a first input negative signal, the second signal driving circuit comprises a second negative signal driving circuit and a second positive signal driving circuit, the first switch comprises a first sub-switch and a second sub-switch, the first sub-switch is used for controlling the connection and disconnection of the second negative signal driving circuit and a signal end of the first input negative signal, and the second sub-switch is used for controlling the connection and disconnection of the second positive signal driving circuit and a signal end of the first input positive signal.

In one possible implementation, the signal transmitting circuit further comprises a pre-emphasis circuit, wherein the pre-emphasis circuit is used for increasing the high-frequency component of the output differential signal according to a second input differential signal to compensate the attenuation of the high-frequency component in the transmission process, and the second input differential signal is a differential signal delayed by one clock period after the first input differential signal. In one possible implementation manner, the second input differential signal includes a second input positive signal and a second input negative signal, the pre-emphasis circuit includes a negative signal pre-emphasis circuit and a positive signal pre-emphasis circuit, the negative signal pre-emphasis circuit is connected with a signal end of the second input negative signal, and the positive signal pre-emphasis circuit is connected with a signal end of the second input positive signal.

In one possible implementation manner, the signal sending circuit further comprises a voltage conversion circuit, wherein the voltage conversion circuit is used for receiving an initial differential signal, the voltage amplitude of the initial differential signal is smaller than a voltage threshold value, and the voltage conversion is carried out on the initial differential signal to obtain the first input differential signal, and the voltage amplitude of the first input differential signal is larger than or equal to the voltage threshold value.

In one possible implementation manner, the initial differential signal comprises an initial positive signal and an initial negative signal, the first input differential signal comprises a first input positive signal and a first input negative signal, the voltage conversion circuit comprises a first conversion circuit and a second conversion circuit, the first conversion circuit is used for converting the initial positive signal into the first input positive signal, and the second conversion circuit is used for converting the initial negative signal into the first input negative signal.

In another aspect, a chip is provided, the chip comprising the signal transmitting circuit as described in the above aspect.

In a further aspect, an electronic device is provided, the electronic device comprising a signal transmitting circuit as described in the above aspect.

In summary, the beneficial effects brought by the technical scheme provided by the application at least include:

According to the signal sending circuit, the connection relation between the first signal driving circuit and the second signal driving circuit is controlled, so that the signal sending circuit can be flexibly switched between the LVDS driving mode and the CML driving mode, and can be compatible with electrical interface standards in different driving modes, further can be compatible with application scenes of different signal transmission protocols, and the flexibility of the signal sending circuit is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a signal transmitting circuit according to an embodiment of the present application;

fig. 2 is a schematic diagram of another signal transmitting circuit according to an embodiment of the present application;

Fig. 3 is a schematic diagram of a first voltage conversion circuit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a second voltage conversion circuit according to an embodiment of the present application;

fig. 5 is a schematic diagram of another signal transmission circuit according to an embodiment of the present application;

fig. 6 is a schematic diagram of another signal transmitting circuit according to an embodiment of the present application;

fig. 7 is a schematic diagram of another signal transmission circuit according to an embodiment of the present application;

Fig. 8 is a schematic diagram of another signal transmission circuit according to an embodiment of the present application;

fig. 9 is a schematic diagram of another signal transmitting circuit according to an embodiment of the present application;

fig. 10 is a schematic diagram of another signal transmitting circuit according to an embodiment of the present application;

Fig. 11 is a schematic diagram of another signal transmission circuit according to an embodiment of the present application;

fig. 12 is a schematic diagram of another signal transmission circuit according to an embodiment of the present application;

Fig. 13 is a schematic diagram of a third voltage conversion circuit and a fourth voltage conversion circuit according to an embodiment of the present application;

Fig. 14 is a schematic diagram of another signal transmission circuit according to an embodiment of the present application;

Fig. 15 is a schematic diagram of a structure of another signal transmitting circuit according to an embodiment of the present application;

FIG. 16 is a schematic diagram of a CML driving mode according to an embodiment of the present application;

FIG. 17 is a schematic diagram of another embodiment of the present application in CML driving mode;

FIG. 18 is a schematic diagram of another embodiment of the present application in CML driving mode;

FIG. 19 is a schematic waveform diagram of a CML driving mode according to an embodiment of the present application;

Fig. 20 is a schematic diagram of driving in LVDS driving mode according to an embodiment of the application;

Fig. 21 is a schematic diagram of driving in another LVDS driving mode according to an embodiment of the application;

fig. 22 is a schematic diagram of driving in another LVDS driving mode according to an embodiment of the application;

Fig. 23 is a schematic waveform diagram of an LVDS driving mode according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

In high-speed serial communication systems, especially in applications such as large data centers, high-performance computing, high-definition video transmission, and telecommunications, serDes (Serializer-Deserializer) plays a vital role. The Serializer is used to convert parallel data into serial data, and the Deserializer is used to convert serial data into parallel data. However, with the continuous increase of data transmission rate and the increase of transmission distance, the signal transmitting circuit of the SerDes transmitting Terminal (TX) faces challenges in terms of signal integrity, power consumption, compatibility, and flexibility.

The signal transmitting circuit of the SerDes TX may be simply referred to as a SerDes TX circuit, and is mainly used for converting parallel data into a high-speed serial signal, and transmitting the parallel data in the form of a differential signal, so as to transmit the parallel data in a high-speed serial communication link. For example, in a high-speed communication system, such as a high-speed ethernet, optical fiber communication, a high-speed backplane, etc., the SerDes TX circuit can perform serialization processing on multiple paths of low-speed parallel data (usually from a parallel bus inside a chip), so as to realize high-speed data transmission, and solve the problems of difficult wiring, large crosstalk between signals, complex synchronization, etc. existing in parallel transmission.

The working flow of the SerDes TX circuit comprises that firstly, parallel data enter a data coding module of the SerDes TX circuit from each functional module (such as a processor, a memory controller and the like) in the system through a parallel data input port, the parallel data are coded through the data coding module to ensure the reliability and clock synchronization performance of the data, the coded parallel data are combined into serial data by a multiplexer according to the bit sequence, the serial data are optimized through a pre-emphasis and equalization module to reduce distortion in the transmission process, and finally, the optimized signal is amplified to the required power level through a driving circuit and is sent out through an electrical interface.

The pre-emphasis is a signal processing mode for compensating high-frequency components of signals at a transmitting end. As the high frequency components decay more rapidly than the low frequency components during transmission through the transmission medium (e.g., printed circuit board traces, cables, etc.), signal distortion results. The pre-emphasis technology enhances the high-frequency part of the signal at the transmitting end to compensate the excessive attenuation of the high-frequency component in the transmission process, so that the receiving end can receive the waveform which is closer to the original signal, and the signal integrity and the transmission distance are improved.

In the related art, serDes TX circuits typically support a single electrical interface standard, such as the LVDS interface standard. The electrical interface standard defines the physical connection between devices and the electrical characteristics of the physical layer, including voltage range, current range, impedance matching, transmission rate and distance limits of the signals, etc., to ensure interoperability and security between devices.

The LVDS interface standard transmits data in the form of a low voltage differential signal, and the data is represented by a voltage difference between two signal lines (a positive signal and a negative signal), so that the LVDS interface standard has the advantages of low power consumption, low noise and good anti-interference capability. The differential signal refers to two signals with equal amplitude and opposite polarity transmitted through two wires, and the receiving end restores data by comparing the difference value of the two signals. For example, a logic "1" is represented when the voltage on the positive signal line is higher than the voltage on the negative signal line, whereas a logic "0" is represented when the voltage on the positive signal line is lower than the voltage on the negative signal line.

However, with the development of communication technology and the change of application requirements, only supporting a single LVDS interface standard cannot meet the diversified scene requirements. Illustratively, in TCON (Timing Controller, timing control) applications supporting P2P (point to point) transmission protocols, the P2P interface standard needs to be supported, or in long-distance transmission scenarios supporting VBO (Video by One) transmission protocols, the VBO interface standard needs to be supported.

As different electrical interface standards differ in terms of signal level, driving mode, transmission rate, etc. For example, under the LVDS interface standard, the LVDS driving mode is adopted, the driving current is relatively small, the power consumption is low, and the LVDS interface standard works in a rate range from 155Mbps (megabits per second megabits per second) to 1.25Gbps (gigabits per second gigabits per second), and is suitable for medium-high speed transmission. Under the P2P interface standard or the VBO interface standard, the CML driving mode is adopted, the driving current is relatively large, the power consumption is high, the stable operation can be realized within the speed range of 600Mbps to 10Gbps and above, the noise immunity is high, and the high-speed anti-noise power transmission device is suitable for higher-speed transmission.

Thus, if the SerDes TX circuit is to be compatible with multiple electrical interface standards such as P2P/LVDS/BVO, the SerDes TX circuit needs to support both LVDS driving mode and CML driving mode.

The embodiment of the application provides a signal transmitting circuit which can support an LVDS driving mode and a CML driving mode. Referring to fig. 1, fig. 1 is a schematic structural diagram of a signal transmitting circuit according to an embodiment of the present application, and the signal transmitting circuit 00 includes a first signal driving circuit 11 and a second signal driving circuit 12.

The first signal driving circuit 11 is configured to transmit the output differential signal in the CML driving mode according to the first input differential signal in the case where the first signal driving circuit 11 is disconnected from the second signal driving circuit 12, and the second signal driving circuit 12 is configured to transmit the output differential signal in the LVDS driving mode according to the first input differential signal in the case where the first signal driving circuit 11 is connected to the second signal driving circuit 12, and the first signal driving circuit 11 and the second signal driving circuit 12 are not operated. Wherein, the transmission frequency of the output differential signal in the CML driving mode is larger than that in the LVDS driving mode.

In the embodiment of the present application, the first signal driving circuit 11 corresponds to a driving circuit in the CML driving mode, and the combination of the first signal driving circuit 11 and the second signal driving circuit 12 corresponds to a driving circuit in the LVDS driving mode. Therefore, in the embodiment of the application, two driving circuits corresponding to two driving modes are combined in the same signal transmission circuit 00, and the signal transmission circuit 00 can flexibly switch the two driving modes by controlling the connection relation between the first signal driving circuit 11 and the second signal driving circuit 12, so that the signal transmission circuit 00 can be flexibly applicable to electrical interface standards in different driving modes.

In a possible implementation manner, the signal sending circuit further comprises a voltage conversion circuit 16, the voltage conversion circuit 16 is used for receiving an initial differential signal, the voltage amplitude of the initial differential signal is smaller than a voltage threshold value, and the voltage conversion is performed on the initial differential signal to obtain a first input differential signal, wherein the voltage amplitude of the first input differential signal is larger than or equal to the voltage threshold value. The voltage threshold is a minimum voltage for driving the first signal driving circuit 11 or the second signal driving circuit 12.

Optionally, the initial differential signal is a differential signal in the SerDes circuit after parallel data is converted into serial data, belongs to a digital domain, has small voltage amplitude, and is difficult to drive devices in a subsequent signal driving circuit. The embodiment of the application converts the initial differential signal in the digital domain into the first input differential signal in the analog domain by the voltage conversion circuit 16, and the voltage amplitude of the signal in the digital domain is larger. For example, the voltage of the initial differential signal ranges from 0-0.9V (volts) and the voltage of the first input differential signal ranges from 0.45-1.35V. The differential signal in the Digital domain may be a specific analog voltage that is output after an Digital signal is input to a Digital-to-Analog Conversion (DAC) in a binary form.

Thereby, the differential signals input to the first signal driving circuit 11 and the second signal driving circuit 12 can be matched with the requirements of the first signal driving circuit 11 and the second signal driving circuit 12 by the voltage converting circuit 16. In the embodiment of the application, the differential signal comprises two signals, namely a positive signal and a negative signal, and the first input differential signal comprises a first input positive signal and a first input negative signal, the output differential signal comprises an output positive signal and an output negative signal, and the initial differential signal comprises an initial positive signal and an initial negative signal.

Alternatively, referring to the signal transmission circuit 00 shown in fig. 2, the voltage conversion circuit 16 includes a first conversion circuit 161 and a second conversion circuit 162. The first conversion circuit 161 for converting an initial positive signal into a first input positive signal, and the second conversion circuit 162 for converting an initial negative signal into a first input negative signal. Thus, voltage conversion of two signals in the differential signal is achieved by two independent conversion circuits, respectively.

In one possible implementation, the first conversion circuit 161 includes a first capacitor and a first bias circuit, one end of the first capacitor is connected to the first signal terminal, the other end of the first capacitor is connected to the second signal terminal through the first node, and the first bias circuit is connected to the first node. The first capacitor is used for controlling the second signal end to output a first input positive signal according to an initial positive signal input by the first signal end, and the voltage range of the first input positive signal floats up and down at the first common mode voltage.

In the embodiment of the application, the floating distance of the first input positive signal is the same as the floating distance of the initial positive signal. For example, the voltage range of the initial differential signal is 0-0.9V, the initial differential signal floats up and down at 0.45V, the floating distance is 0.45V, the voltage range of the first input differential signal is 0.45-1.35V, the first input differential signal floats up and down at 0.9V, the floating distance is 0.45V, and the first common mode voltage is 0.9V. The circuit structure of the second conversion circuit 162 may refer to the circuit of the first conversion circuit 161, and will not be described herein.

Alternatively, the first bias circuit may include a first bias impedance having one end connected to the power supply terminal and the other end connected to the first node, and a second bias impedance having one end connected to the ground terminal and the other end connected to the first node. The voltage of the power supply terminal is set to be twice the voltage of the first common mode voltage, for example, 1.8V, and the impedance magnitudes of the first bias impedance and the second bias impedance are set to be equal, so that the first bias impedance and the second bias impedance can generate the same voltage drop, and then the voltage of the first node between the first bias impedance and the second bias impedance is half the voltage of the power supply terminal, for example, 0.9V.

The first bias impedance and the second bias impedance can be realized through devices such as a PMOS tube and an NMOS tube. The PMOS tube refers to a P (Positive) MOS tube, and the working principle is that when a signal received by the grid electrode is a high-level signal, the source electrode and the drain electrode of the PMOS tube are not conducted, and when the signal received by the grid electrode is a low-level signal, the source electrode and the drain electrode of the PMOS tube are conducted. The NMOS transistor is an N (Negative) MOS transistor, and the working principle is that when the signal received by the grid electrode is a high-level signal, the source electrode and the drain electrode of the NMOS transistor are conducted, and when the signal received by the grid electrode is a low-level signal, the source electrode and the drain electrode of the NMOS transistor are not conducted. The MOS transistor is an abbreviation of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide semiconductor field effect transistor), abbreviated as a Metal Oxide semiconductor field effect transistor or a field effect transistor.

Illustratively, the circuit structure of the first conversion circuit 161 may be as shown in fig. 3, in being a first signal terminal for inputting an initial positive signal, OUTP being a second signal terminal for outputting a first input positive signal. VDD is the power supply terminal, VSS is the ground terminal, C1 is the first capacitor, and X1 is the first node. MN3 and MN4 are two NMOS tubes, and MP5 and MP6 are two PMOS tubes. Wherein MP5 and MN3, MP6 and MN4 are respectively set with corresponding bias voltages, such as V2, V3, V4 and V5 in fig. 3. Bias Voltage (Bias Voltage), also known as Bias Voltage or Bias Voltage, refers to a dc Voltage that is applied in addition to a circuit in order to operate a transistor or other active device in a specific region.

Therefore, MP5 and MN3 form a first bias impedance, MP6 and MN4 form a second bias impedance, and the first bias impedance and the second bias impedance are equal in magnitude, so that X1 is a static working point of the first common mode voltage. Similarly, the circuit structure of the second conversion circuit 162 may be as shown in fig. 4, where INN is a third signal terminal for inputting the initial negative signal, and OUTN is a fourth signal terminal for outputting the first input negative signal.

In one possible embodiment, referring to fig. 5, the signal transmission circuit 00 further includes a first control circuit 13 and a second control circuit 14, the first control circuit 13 is configured to control an input signal of the second signal driving circuit 12, the second control circuit 14 is configured to control a connection mode of the first signal driving circuit 11, the first signal driving circuit 11 is disconnected from the second signal driving circuit 12 when the input signal of the second signal driving circuit 12 is a first level and the connection mode of the first signal driving circuit 11 is a first connection mode, and the first signal driving circuit 11 is connected to the second signal driving circuit 12 when the input signal of the second signal driving circuit 12 is a first input differential signal and the connection mode of the first signal driving circuit 11 is a second connection mode.

The embodiment of the present application is not limited to the manner in which the first control circuit 13 controls the input signal of the second signal driving circuit 12. Alternatively, referring to fig. 6, the first control circuit 13 includes a signal generating circuit 131, a first switch 132 and a second switch 133, the signal generating circuit 131 being configured to generate a signal of a first level, the first switch 132 being configured to control on and off of the second signal driving circuit 12 and a signal terminal of the first input differential signal, and the second switch 133 being configured to control on and off of the second signal driving circuit 12 and the signal generating circuit.

Since the first input differential signal includes the first input positive signal and the first input negative signal, and the output differential signal includes the output positive signal and the output negative signal, the first signal driving circuit 11 and the second signal driving circuit 12 also correspond to driving circuits including positive and negative two portions. As shown in fig. 7, the first signal driving circuit 11 includes a first negative signal driving circuit 111 and a first positive signal driving circuit 112, the first negative signal driving circuit 111 is connected to a signal terminal of a first input negative signal, and the first positive signal driving circuit 112 is connected to a signal terminal of a first input positive signal. In this embodiment, the first connection mode is that the first negative signal driving circuit 111 and the first positive signal driving circuit 112 are both connected to the ground, and the second connection mode is that the first negative signal driving circuit 111 and the first positive signal driving circuit 112 are connected. The second control circuit 14 is located between the first negative signal driving circuit 111 and the first positive signal driving circuit 112, and is connected to the first negative signal driving circuit 111 and the first positive signal driving circuit 112, respectively.

Illustratively, referring to fig. 8, the first negative signal driving circuit 111 includes a first transistor and a first impedance, and the first positive signal driving circuit 112 includes a second transistor and a second impedance. The grid electrode of the first transistor is input with a first input negative signal, the source electrode of the first transistor is connected with a first positive current source, the drain electrode of the first transistor is connected with one end of a first impedance through a first output end, the first output end is used for transmitting and outputting positive signals, the grid electrode of the second transistor is input with the first input positive signal, the source electrode of the second transistor is connected with one end of a second impedance through a second output end, the drain electrode of the second transistor is used for transmitting and outputting negative signals, and the second control circuit 14 is respectively connected with the other end of the first impedance and the other end of the second impedance and used for controlling the connection mode between the first impedance and the second impedance. In this mode, the first connection mode is that the first impedance and the second impedance are both connected to the ground, and the second connection mode is that the first impedance and the second impedance are connected.

As shown in fig. 9, the second signal driving circuit 12 includes a second negative signal driving circuit and 121 a second positive signal driving circuit 122, the first switch 132 includes a first sub-switch 1321 and a second sub-switch 1322, the first sub-switch 1321 is used for controlling the on and off of the second negative signal driving circuit and the signal end of the first input negative signal, and the second sub-switch 1322 is used for controlling the on and off of the second positive signal driving circuit and the signal end of the first input positive signal.

Illustratively, referring to fig. 10, the first negative signal driving circuit 111 includes a third transistor and the first positive signal driving circuit 112 includes a fourth transistor. The gate of the third transistor is connected to the first sub-switch 1321, the source of the third transistor is connected to the negative current source, the drain of the third transistor is connected to the first output terminal, the gate of the fourth transistor is connected to the second sub-switch 1322, the source of the fourth transistor is connected to the negative current source, and the drain of the fourth transistor is connected to the second output terminal. Alternatively, the second switch 133 may also include two sub-switches, one for controlling the switching of the signal generating circuit 131 and the third transistor, and the other for controlling the switching of the signal generating circuit 131 and the fourth transistor.

In the embodiment of the application, the first transistor and the second transistor are turned on when the gate input signal is at the first level and turned off when the gate input signal is at the second level, and the third transistor and the fourth transistor are turned off when the gate input signal is at the first level. I.e. the first and second transistors are of a different type than the third and fourth transistors. Illustratively, the first and second transistors are PMOS transistors and the third and fourth transistors are NMOS transistors.

A schematic diagram of the signaling circuit may be illustrated in fig. 11, for example. The first transistor corresponds to MP1, the second transistor corresponds to MP2, MP is the abbreviation of PMOS transistor, the third transistor corresponds to MN1, the fourth transistor corresponds to MN2, MN is the abbreviation of NMOS transistor, the first impedance corresponds to RON1, the second impedance corresponds to RON2, the first output end corresponds to OUT_P, and the second output end corresponds to OUT_N. AVDD represents an analog voltage, for example, AVDD is 1.8v, and avss represents analog ground.

As shown in fig. 11, the second control circuit 14 includes 4 switches SW5, SW6, SW7, and SW8, respectively. RON1 is connected to RON2 with SW5 and SW7 closed, SW6 and SW8 open, and RON1 and RON2 are both connected to AVSS with SW5 and SW7 open, SW6 and SW8 closed. The first switch 132 includes 2 switches SW3 and SW4, respectively, the second switch 133 includes 2 switches SW1 and SW2, respectively, the signal generating circuit 131 includes 2 resistors, which are also connected to the AVSS, respectively, and the resistances of the two resistors may be equal, and are all used to generate the signal of the first level (i.e., the low level). With SW1 and SW2 closed, SW3 and SW4 open, the gate voltages of MN1 and MN2 remain low, and MN1 and MN2 remain open, while with SW1 and SW2 open, SW3 and SW4 closed, the gate input OUTN of MN1, the gate input OUTP of MN2, MN1 and MN2 are turned on or off according to the changes in OUTN and OUTP.

Taking an NMOS transistor as an example, a gate-source Voltage (VGS) of the NMOS transistor needs to be greater than a threshold voltage (Vth) to form a conductive channel, so that the transistor is turned on, and typical values of the threshold voltage of the NMOS transistor are different due to different process and device parameters. For example, when the first input negative signal is input to the gate of MN1, the gate driving voltage, i.e., the voltage of OUTN, is at least greater than the threshold voltage to turn on the MN1 tube. Therefore, the minimum voltage driving the first signal driving circuit 11 is the threshold voltage of the NMOS transistor in the first signal driving circuit 11, and the minimum voltage driving the second signal driving circuit 12 is the threshold voltage of the NMOS transistor in the second signal driving circuit 12.

In a possible embodiment, referring to fig. 12, the signal transmitting circuit further comprises a pre-emphasis circuit 15, the pre-emphasis circuit 15 being configured to increase the high frequency component of the output differential signal according to the second input differential signal to compensate for attenuation of the high frequency component during transmission. The second input differential signal is a differential signal of the first input differential signal delayed by one clock period.

Optionally, in the case that the signal sending circuit further includes the pre-emphasis circuit 15 shown in fig. 12 and the voltage conversion circuit 16 shown in fig. 2, the voltage conversion circuit 16 is further configured to receive the initial differential signal delayed by one clock cycle, and perform voltage conversion on the initial differential signal delayed by one clock cycle to obtain a second input differential signal, where the voltage amplitude of the second input differential signal is greater than or equal to a voltage threshold, where the voltage threshold is a minimum voltage for driving the pre-emphasis circuit 15.

In agreement with the above-described differential signals, the second input differential signal includes a second input positive signal and a second input negative signal, and the voltage conversion circuit 16 optionally includes a third conversion circuit and a fourth conversion circuit in addition to the first conversion circuit 161 and the second conversion circuit 162. The first conversion circuit is used for converting an initial positive signal delayed by one clock cycle into a first input positive signal, and the second conversion circuit is used for converting an initial negative signal delayed by one clock cycle into a second input negative signal.

The structures of the third conversion circuit and the fourth conversion circuit may be referred to the structures of the first conversion circuit 161 and the second conversion circuit 162, and are not described herein. Illustratively, the third conversion circuit may be as shown in (a) of fig. 13, in which inp_em is used to input an initial positive signal delayed by one clock period, and outp_em is used to output a second input positive signal. The fourth conversion circuit may be as shown in (b) of fig. 13, in which inn_em is used to input an initial negative signal delayed by one clock period and outn_em is used to output a second input negative signal.

In one possible implementation, the pre-emphasis circuit 15 includes a negative signal pre-emphasis circuit connected to the signal terminal of the second input negative signal and a positive signal pre-emphasis circuit connected to the signal terminal of the second input positive signal. The negative signal pre-emphasis circuit comprises a fifth transistor, the positive signal pre-emphasis circuit comprises a sixth transistor, a grid electrode of the fifth transistor is input with a second input positive signal, a source electrode of the fifth transistor is connected with a second positive current source, a drain electrode of the fifth transistor is connected with a first output end, the first output end is used for transmitting an output positive signal after increasing high-frequency components, the grid electrode of the sixth transistor is input with a second input negative signal, a source electrode of the sixth transistor is connected with a second positive current source, a drain electrode of the sixth transistor is connected with a second output end, and the second output end is used for transmitting an output negative signal after increasing the high-frequency components.

Illustratively, the circuit configuration after adding the pre-emphasis circuit 15 on the basis of the first signal driving circuit 11 and the second signal driving circuit 12 shown in fig. 11 is shown in fig. 14. Wherein the fifth transistor corresponds to MP3 and the sixth transistor corresponds to MP4.

In the embodiment of the present application, the function of the switch SW in fig. 14 may be implemented by a transistor. In this case, as shown in fig. 15, SW3 and SW4 may be implemented by two parallel transistors, in which the gates and sources of the transistors are both connected with bias voltages, so that the two parallel transistors implement the switching function. SW1 and SW2 may be implemented by a transistor, and the function of the switch is implemented by switching in corresponding bias voltages at the gate and source of the transistor.

Optionally, gates of MP3 and MP4 are also connected to SW9 and SW10, and whether the pre-emphasis circuit 15 is operated is controlled by SW9 and SW 10. As shown in fig. 15, SW9 and SW10 may be implemented by one transistor to which a bias voltage is applied. The bias voltages applied in the embodiments of the present application are not limited, and the embodiments of the present application can implement the corresponding switching functions, and the bias voltages applied when implementing different switching functions may be the same or different.

Taking the schematic structure of the signal driving circuit shown in fig. 15 as an example, the operation mode of the signal driving circuit provided by the embodiment of the application is illustrated. In the CML driving mode, the first stage is shown in fig. 16, MP2, MP3, SW1, SW2, SW6, SW8 are on, MP1, MP4, MN1, MN2, SW3, SW4, SW5, SW7 are off, and the current flow path is shown in fig. 16 by the dotted line, so that the output voltage V (out_p-out_n) =i_eme_ron1-i_main_ron2 in the first stage. Wherein, I_MAIN is the current value of the first positive current source, I_EME is the current value of the second positive current source, RON1 and RON2 are impedance matching resistance values.

Impedance matching is required to achieve maximum power transfer or to reduce signal reflection when a signal is transferred from one circuit portion to another. Taking the transmission of high-speed digital signals in a PCB (printed circuit board) wiring as an example, if the characteristic impedance of the PCB wiring is designed to be 100 omega (ohm) and the input impedance of a connected chip is also 100 omega, impedance matching is realized, signals can be effectively transmitted from the wiring to the chip, and signal distortion and interference caused by reflection are reduced.

In the second stage, as shown in fig. 17, MP1, MP3, SW1, SW2, SW6, SW8 are turned on, MP2, MP4, MN1, MN2, SW3, SW4, SW5, SW7 are turned off, and the current flow path is shown by the dotted line in fig. 17, so that the output voltage V (out_p-out_n) =i_main_ron1+i_eme_ron1 in the second stage. In the third stage, as shown in fig. 18, MP1, MP4, SW1, SW2, SW6, SW8 are on, MP2, MP3, MN1, MN2, SW3, SW4, SW5, SW7 are off, and the current flow path is shown by the dotted line in fig. 18, so that the output voltage V (out_p-out_n) =i_main_ron1_i_eme_ron2 in the third stage.

Fig. 19 is a waveform diagram of an output differential signal transmitted in the CML driving mode, by way of example. The upper half of fig. 19 shows the output differential signals in the CML driving mode, the thin curve represents the output positive signal in the output differential signals, the thick curve represents the output negative signal in the output differential signals, and the lower half of fig. 19 shows the output signal converted based on the output differential signals, wherein the output signal is the difference between the output positive signal and the output negative signal. For example, in the first stage of fig. 19, the voltage value of the output positive signal is about 0.8 v, the voltage value of the output negative signal is about 0.5 v, and the voltage value of the output signal is about 0.3 v.

In an embodiment of the application, the pre-emphasis circuit achieves signal enhancement by adjusting the drive current. Specifically, for a high-speed digital signal to be transmitted, an additional driving current is added at the rising and falling edges of the signal (i.e., the portions where high frequency components are concentrated), so that the signal amplitude is enhanced. For example, when a high-speed pulse train is transmitted, the amplitude of the pulses is normally fixed, but in the pre-emphasis mode the rising and falling edges of each pulse will be higher in amplitude than the middle part.

In the LVDS driving mode, as shown in fig. 20, the output voltages V (out_p-out_n) = -i_main (ron1+ron2) of the first stage are shown in the first stage, wherein MP2, MP3, MN1, SW3, SW4, SW5, SW7 are turned on, and MP1, MP4, MN2, SW1, SW2, SW6, SW8 are turned off. In the second stage, as shown in fig. 21, MP1, MP3, MN2, SW3, SW4, SW5, SW7 are turned on, MP2, MP4, MN1, SW2, SW6, SW8 are turned off, and the output voltage V (out_p-out_n) = (i_main+i_eme) (ron1+ron2) in the second stage. In the third stage, as shown in fig. 22, MP1, MP4, MN2, SW3, SW4, SW5, SW7 are turned on, MP2, MP3, MN1, SW2, SW6, SW8 are turned off, and V (out_p-out_n) = (i_main) = (ron1+ron2).

Fig. 23 is a waveform diagram of an output differential signal transmitted in the LVDS driving mode. The upper half of fig. 23 shows the output differential signals in the LVDS driving mode, the thin curve represents the output positive signal in the output differential signals, the thick curve represents the output negative signal in the output differential signals, and the lower half of fig. 23 shows the output signals converted based on the output differential signals, the output signals being the difference between the output positive signal and the output negative signal. For example, taking the first stage of fig. 23 as an example, the voltage value of the output positive signal is about 1 volt, the voltage value of the output negative signal is about 1.4 volts, and the voltage value of the output signal is about-0.4 volts.

The signal transmitting circuit provided by the embodiment of the application can be a SerDes TX circuit. To sum up, the SerDes TX circuit in the related art relies on a single electrical interface, and fails to fully utilize the convenience of the P2P interface, the low power consumption advantage of the LVDS interface, and the electrical characteristics of the VBO interface. Aiming at the technical bottleneck, the embodiment of the application provides a SerDes TX circuit which is compatible with a P2P/LVDS interface to ensure low power consumption and stable data transmission, integrates adaptability to VBO electrical characteristics and realizes the capability of seamless switching between different scenes. And the optimal solution of the area is realized through the adjustment of the architecture and the unique voltage conversion design, so that the method can be compatible with most of application scenes of emission protocols in the market.

The chip provided by the embodiment of the application comprises any one of the signal sending circuits. Therefore, the chip can support switching of two driving modes, namely an LVDS driving mode and a CML driving mode, and further can be compatible with electrical interface standards in different driving modes.

Alternatively, the chip may be an interface chip, for example, a high definition multimedia interface (High Definition Multimedia Interface, HDMI) chip, (DisplayPort, DP) or a mobile industry processor interface (Mobile Industry Processor Interface, MIPI) chip, etc.

The embodiment of the application provides electronic equipment, which comprises any one of the signal sending circuits. Optionally, the electronic device includes the chip, and the chip includes any one of the signal transmitting circuits described above.

It is to be understood that the terminology used in the description of the embodiments of the disclosure is for the purpose of describing the embodiments of the disclosure only and is not intended to be limiting of the disclosure. Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

As used in the specification and claims of this application, the terms "first," "second," or "third," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"Upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed. "connected" or "coupled" refers to electrical connections.

"And/or" means that there may be three relationships, e.g., A and/or B, and that there may be three cases where A alone exists, while A and B exist, and B alone exists. The character "/" generally indicates that the context-dependent object is an "or" relationship.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working processes of the gate driving circuit, the shift register unit, each circuit and each sub-circuit described above may refer to corresponding processes in the method embodiments, and are not described herein again.

The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims (11)

1. A signal transmission circuit, characterized in that the signal transmission circuit comprises a first signal driving circuit and a second signal driving circuit;

When the first signal driving circuit is disconnected from the second signal driving circuit, the first signal driving circuit is used for sending an output differential signal in a current mode logic CML driving mode according to a first input differential signal, and the second signal driving circuit does not work;

And under the condition that the first signal driving circuit is communicated with the second signal driving circuit, the first signal driving circuit and the second signal driving circuit are used for sending output differential signals in a low-voltage differential signaling (LVDS) driving mode according to the first input differential signals.

2. The signal transmission circuit according to claim 1, further comprising a first control circuit for controlling an input signal of the second signal driving circuit and a second control circuit for controlling a connection mode of the first signal driving circuit;

When the input signal of the second signal driving circuit is at a first level and the connection mode of the first signal driving circuit is a first connection mode, the first signal driving circuit is disconnected from the second signal driving circuit;

And when the input signal of the second signal driving circuit is the first input differential signal and the connection mode of the first signal driving circuit is the second connection mode, the first signal driving circuit is communicated with the second signal driving circuit.

3. The signal transmission circuit according to claim 2, wherein the first control circuit includes a signal generation circuit, a first switch, and a second switch;

the signal generating circuit is used for generating the signal of the first level;

the first switch is used for controlling the connection and disconnection of the second signal driving circuit and the signal end of the first input differential signal;

the second switch is used for controlling the connection and disconnection of the second signal driving circuit and the signal generating circuit.

4. The signal transmission circuit according to claim 2, wherein the first input differential signal includes a first input positive signal and a first input negative signal, the first signal driving circuit includes a first negative signal driving circuit and a first positive signal driving circuit, the first negative signal driving circuit is connected to a signal terminal of the first input negative signal, and the first positive signal driving circuit is connected to a signal terminal of the first input positive signal;

the first connection mode is that the first negative signal driving circuit and the first positive signal driving circuit are both connected with the ground terminal, and the second connection mode is that the first negative signal driving circuit and the first positive signal driving circuit are connected.

5. The signal transmission circuit of claim 3, wherein the first input differential signal comprises a first input positive signal and a first input negative signal, the second signal driving circuit comprises a second negative signal driving circuit and a second positive signal driving circuit, and the first switch comprises a first sub-switch and a second sub-switch;

The first sub-switch is used for controlling the connection and disconnection of the second negative signal driving circuit and the signal end of the first input negative signal;

The second sub-switch is used for controlling the connection and disconnection of the second positive signal driving circuit and the signal end of the first input positive signal.

6. The signaling circuit of any of claims 1-5, wherein the signaling circuit further comprises a pre-emphasis circuit;

The pre-emphasis circuit is used for increasing the high-frequency component of the output differential signal according to a second input differential signal so as to compensate the attenuation of the high-frequency component in the transmission process, wherein the second input differential signal is a differential signal of which the first input differential signal is delayed by one clock period.

7. The signal transmission circuit of claim 6, wherein the second input differential signal comprises a second input positive signal and a second input negative signal, the pre-emphasis circuit comprises a negative signal pre-emphasis circuit and a positive signal pre-emphasis circuit, the negative signal pre-emphasis circuit is connected to a signal terminal of the second input negative signal, and the positive signal pre-emphasis circuit is connected to a signal terminal of the second input positive signal.

8. The signal transmission circuit according to any one of claims 1 to 5, wherein the signal transmission circuit further comprises a voltage conversion circuit;

The voltage conversion circuit is used for receiving an initial differential signal, the voltage amplitude of the initial differential signal is smaller than a voltage threshold value, and the voltage conversion is carried out on the initial differential signal to obtain a first input differential signal, wherein the voltage amplitude of the first input differential signal is larger than or equal to the voltage threshold value.

9. The signal transmission circuit of claim 8, wherein the initial differential signal comprises an initial positive signal and an initial negative signal, the first input differential signal comprises a first input positive signal and a first input negative signal, and the voltage conversion circuit comprises a first conversion circuit and a second conversion circuit;

The first conversion circuit is used for converting the initial positive signal into the first input positive signal;

the second conversion circuit is configured to convert the initial negative signal into the first input negative signal.

10. A chip comprising a signal transmission circuit as claimed in any one of claims 1 to 9.

11. An electronic device comprising a signalling circuit as claimed in any one of claims 1 to 9.