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CN119882510A - Electronic device and control method of electronic device - Google Patents

Electronic device and control method of electronic device Download PDF

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Publication number
CN119882510A
CN119882510A CN202411745392.4A CN202411745392A CN119882510A CN 119882510 A CN119882510 A CN 119882510A CN 202411745392 A CN202411745392 A CN 202411745392A CN 119882510 A CN119882510 A CN 119882510A
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CN
China
Prior art keywords
circuit
state
bus interface
single bus
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202411745392.4A
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Chinese (zh)
Inventor
顾锦华
赵庚强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lenovo Beijing Ltd
Original Assignee
Lenovo Beijing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lenovo Beijing Ltd filed Critical Lenovo Beijing Ltd
Priority to CN202411745392.4A priority Critical patent/CN119882510A/en
Publication of CN119882510A publication Critical patent/CN119882510A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40019—Details regarding a bus master
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25257—Microcontroller

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Sources (AREA)

Abstract

The disclosure provides electronic equipment and a control method of the electronic equipment, wherein the electronic equipment comprises a single bus interface, a communication unit and a first circuit, one end of the first circuit is connected with the ground, the other end of the first circuit is connected with the single bus interface, the first circuit comprises a first state and a second state, when the first circuit is in the first state, the first circuit is in a passage state and is used for detecting the connection state of the electronic equipment and the host equipment by the host equipment, and when the first circuit is in the second state, the first circuit is in an open circuit state so as to reduce leakage current.

Description

Electronic device and control method of electronic device
Technical Field
The disclosure relates to the field of communications, and in particular, to an electronic device and a control method of the electronic device.
Background
The current host electronic device is connected and communicated with external electronic devices through 3 lines POGO Pin, and the 3 lines are respectively power supply, data and ground. The data line is essentially a half duplex serial module, which is a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), and includes a transmitting end uart_tx and a receiving end uart_rx.
When the host electronic equipment is dormant, the auxiliary electronic equipment is dormant, and meanwhile, the bus level is maintained to be high for the functions of connection state detection between the host electronic equipment and the auxiliary electronic equipment, host awakening and the like, but the problems of mistaken awakening of the host electronic equipment and larger leakage current of the whole system exist.
Disclosure of Invention
The disclosure provides an electronic device and a control method of the electronic device.
According to a first aspect of the present disclosure, there is provided an electronic device, comprising a single bus interface,
A communication unit that communicates with a host device through the single bus interface;
one end of the first circuit is connected with the ground, and the other end of the first circuit is connected with the single bus interface;
Wherein the first circuit comprises a first state and a second state,
When the first circuit is in a first state, the first circuit is in a channel state and is used for detecting the connection state of the electronic equipment and the host equipment by the host equipment;
when the first circuit is in the second state, the first circuit is in an open state so as to reduce leakage current.
In one embodiment of the present application, the device further comprises a second circuit, one end of which is connected to the single bus interface, and the other end of which is connected to the first circuit, and the second circuit controls the state of the first circuit based on the supply voltage of the host device obtained from the single bus interface.
In one embodiment of the present application, the first circuit includes a first resistor and a first switch connected in series, and the second circuit is connected to the first switch of the first circuit, where, in response to the electronic device being connected to the host device, the second circuit obtains a supply voltage of the host device through the single bus interface to control the first switch to switch from a first state to a second state.
In one implementation of the application, the circuit further comprises a third circuit, one end of the third circuit is connected with a power supply, and the other end of the third circuit is connected with the single bus interface, wherein when the first circuit is in the second state, the third circuit is configured to be in a conducting state so as to reduce the leakage current.
In an embodiment of the present application, the control unit is configured to configure the at least two third circuits to be in a conductive state according to a sleep command sent by the host device and received from the single bus interface, so as to reduce the leakage current.
According to a second aspect of the present disclosure, there is provided an electronic device control method, applied to an electronic device, the electronic device including a single bus interface,
A communication unit that communicates with a host device through the single bus interface;
one end of the first circuit is connected with the ground, and the other end of the first circuit is connected with the single bus interface;
Responding to the connection of the host equipment and the electronic equipment through the single bus interface, and controlling the first circuit to switch from a first state to a second state;
When the first circuit is in a first state, the first circuit is in a channel state and is used for detecting the connection state of the electronic equipment and the host equipment through the single bus interface by the host equipment;
when the first circuit is in the second state, the first circuit is in an open state so as to reduce leakage current.
In an embodiment of the present application, the electronic device further includes a second circuit having one end connected to the single bus interface and the other end connected to the first circuit, and the method includes controlling the state of the first circuit based on the supply voltage of the host device obtained from the single bus interface in response to the host device being connected to the electronic device through the single bus interface.
In an implementation of the present application, the electronic device further includes a third circuit, one end of the third circuit is connected to the power supply, and the other end of the third circuit is connected to the single bus interface;
the method further includes configuring the third circuit to be in a conductive state when the first circuit is in a second state to reduce the leakage current.
In an embodiment of the present application, the electronic device includes a plurality of third circuits connected in parallel, and the method further includes configuring the at least two third circuits to be in a conductive state based on a sleep instruction sent by the host device and received by the communication unit from the single bus interface, so as to reduce the leakage current.
In one embodiment of the present application, the method further includes, in response to receiving a key command, configuring the third circuit to be turned off and configuring the communication unit to be turned on with the single bus interface when the electronic device processes the sleep state, so as to send a wake-up command to the host device through the communication unit, so that the host device responds to the key command.
According to a third aspect of the present disclosure, there is provided an electronic device control apparatus including:
The control module is used for responding to the connection of the host equipment and the electronic equipment through the single bus interface and controlling the first circuit to be switched from a first state to a second state, wherein when the first circuit is in the first state, the first circuit is in a passage state and is used for detecting the connection state of the electronic equipment and the host equipment through the single bus interface;
when the first circuit is in the second state, the first circuit is in an open state so as to reduce leakage current.
In an embodiment of the present application, the control module is specifically configured to control, in response to the host device and the electronic device being connected through the single bus interface, a state of the first circuit based on a supply voltage obtained from the single bus interface for the host device.
In an embodiment of the present application, the control module is specifically configured to configure the third circuit in a conductive state when the first circuit is in the second state, so as to reduce the leakage current.
In an embodiment of the present application, the control module is specifically configured to configure the at least two third circuits to be in a conductive state based on a sleep command sent by the host device and received by the communication unit from the single bus interface, so as to reduce the leakage current.
In an implementation of the present application, the control module is further specifically configured to, in response to receiving a key command when the electronic device processes the sleep state, configure the third circuit to be disconnected, and configure the communication unit to be connected to the single bus interface, so as to send a wake-up command to the host device through the communication unit, so that the host device responds to the key command.
According to a fourth aspect of the present disclosure, there is provided an electronic device comprising:
at least one processor, and
A memory communicatively coupled to the at least one processor, wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the present disclosure.
According to a fifth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of the present disclosure.
The electronic equipment comprises a single bus interface, a communication unit, a first circuit and a second circuit, wherein the communication unit is communicated with the host equipment through the single bus interface, one end of the first circuit is connected with the ground, the other end of the first circuit is connected with the single bus interface, the first circuit comprises a first state and a second state, when the first circuit is in the first state, the first circuit is in a passage state and is used for detecting the connection state of the electronic equipment and the host equipment by the host equipment, and when the first circuit is in the second state, the first circuit is in an open-circuit state so as to reduce leakage current.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
Fig. 1 is a schematic structural diagram of an electronic device and host device connection according to an embodiment of the present disclosure;
fig. 2 illustrates a second structural schematic diagram of an electronic device and host device connection provided in an embodiment of the present disclosure;
Fig. 3 illustrates a third schematic structural diagram of an electronic device and host device connection provided in an embodiment of the present disclosure;
fig. 4 shows a fourth schematic structural diagram of an electronic device and host device connection according to an embodiment of the present disclosure;
fig. 5 illustrates a fifth structural diagram of an electronic device and host device connection provided in an embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating an exemplary connection between an electronic device and a host device according to an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating an exemplary keyboard and host device connection provided by an embodiment of the present application;
Fig. 8 is a schematic diagram showing the constitution of an apparatus according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.
Fig. 1 is a schematic structural diagram of an electronic device and host device connection according to an embodiment of the present application.
In the embodiment of the present disclosure, the electronic device 100 and the host device 200 of the embodiment of the present application are connected through the single bus interface 110. The electronic device 100 includes a single bus interface 110, a communication unit 120, and a first circuit 130. The first circuit 130, one end of which is connected with the ground, and the other end of which is connected with the single bus interface 110;
The first circuit 130 includes a first state and a second state, when the first circuit 130 is in the first state, the first circuit 130 is in a path state, and is used for the host device 200 to detect a connection state of the electronic device 100 and the host device 200, and when the first circuit 130 is in the second state, the first circuit 130 is in an open state, so as to reduce leakage current.
The electronic device in this embodiment may be auxiliary devices such as a keyboard, a mouse, a camera, a scanner, a light pen, a handwriting input board, a joystick, a voice input device, and the host device may be devices such as a notebook computer, a computer, and a tablet computer. The communication unit may be configured to satisfy a serial communication interface protocol, and may include, for example, universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), although embodiments of the application are not limited to a particular serial communication interface protocol.
For example, in case the communication unit is configured to meet UART, the communication unit may include a UART receiving port (UARTRx) and a UART transmitting port (UARTTx). Wherein UARTRx is a receiving port of UART. When the electronic device receives data, the data will be transmitted to the electronic device through UARTRx pins. In communication UARTRx is used to receive data from the host device, UARTTx is a transmit port of the UART for transmitting data to the host device. When the electronic device is to send data, the data will be transmitted to the host device over UARTTx pins.
The first circuit in this embodiment may be in the first state or the second state. When the first circuit is in a channel state, the host device, the first circuit and the ground are connected to form a channel, so that the host device can detect the connection state of the electronic device through level change, and the power supply requirement or instruction control of the electronic device is met. After the host device detects the connection state of the electronic device, the host device can enter a normal working mode, and in the working mode, if the first circuit is controlled to be in an off state, the electronic device in the first circuit can be prevented from flowing in current, so that leakage current is reduced, and unnecessary power consumption is avoided.
According to the embodiment, the first circuit is changed into the first state or the second state, so that the host device can normally detect the connection state of the electronic device, and the state of the first circuit can be changed after the access of the electronic device is detected, and leakage current is reduced.
Fig. 2 shows a second schematic structural diagram of connection between an electronic device and a host device according to an embodiment of the present application. As shown in fig. 2, a second circuit 140 is further included, one end of which is connected to the single bus interface 110, and the other end of which is connected to the first circuit 130, and the second circuit 140 controls the state of the first circuit 130 based on the supply voltage obtained from the single bus interface 110 to the host device 200.
In this embodiment, the second circuit may be configured, and the second circuit is not limited to a specific device composition, as long as the state of the first circuit can be controlled by a voltage. In one embodiment, when the device host determines that there is a connection to the electronic device, a supply voltage may be provided to the electronic device, so that the second circuit may directly obtain the supply voltage provided by the host device, and control the first circuit to switch from the first state to the second state due to the voltage increase.
Fig. 3 shows a third schematic structural diagram of connection between an electronic device and a host device according to an embodiment of the present application. As shown in fig. 3, the first circuit 130 includes a first switch 1310 and a first resistor 1320 connected in series, and the second circuit 140 is connected to the first switch 1310 of the first circuit 130, where, in response to the electronic device 100 being connected to the host device 200, the second circuit 140 obtains a supply voltage of the host device 200 through the single bus interface 110 to control the first switch 1310 to switch from a first state to a second state.
Wherein the first switch is a switch capable of controlling its open and closed states by a voltage.
Specifically, the present embodiment exemplarily provides an internal circuit composition structure of a first circuit, including a first switch and a first resistor. When the first circuit is in the first state, the first switch is closed, the first switch and the first resistor are in a passage state, and when the first circuit is in the second state, the first switch is opened, and the first switch and the first resistor are in an open state. The second circuit may be directly connected to the first switch for controlling the first switch by the supply voltage to switch its different states.
Fig. 4 shows a schematic structural diagram of an electronic device and host device connection according to an embodiment of the present application. As shown in fig. 4, the circuit further includes a third circuit 150, one end of the third circuit 150 is connected to a power supply, and the other end is connected to the single bus interface 110, where the third circuit is configured to be in a conductive state when the first circuit is in the second state, so as to reduce the leakage current.
Specifically, the present embodiment may be configured with a third circuit, in which a controllable switch may be provided, so that when the first circuit is in an off state, that is, after the host device is connected to the auxiliary device and is in an operating mode, the third circuit is configured to be in an on state, and as a group of electronic devices is added, the total resistance of the circuit is reduced, thereby further reducing the leakage current.
Fig. 5 shows a fifth structural diagram of connection between an electronic device and a host device according to an embodiment of the present application. As shown in fig. 5, the device further includes a plurality of third circuits 150 connected in parallel and a control unit 160, where the control unit 160 is configured to configure the at least two third circuits 150 to be in a conductive state according to a sleep instruction sent by the host device and received from the single bus interface 110, so as to reduce the leakage current.
The sleep instruction may be that the host device is in a standby and power-saving sleep mode, and may cause the electronic device connected with the host device to enter the standby and power-saving sleep mode. The control unit is used for controlling whether the third circuit is in a conducting state.
Specifically, the present embodiment may be configured with a plurality of third circuits, and when the host device sends the sleep instruction, not only the host device is in the standby and power-saving sleep mode, but also the electronic device connected with the host device is in the standby and power-saving sleep mode. In this embodiment, the plurality of third circuits may be configured to be in a conductive state in the sleep mode, so that the total resistance is reduced, thereby further reducing the leakage current. In addition, the communication unit can be set to be in a closed mode, so that power consumption caused by excessive device operation is avoided.
Fig. 6 is a schematic structural diagram of an exemplary connection between an electronic device and a host device according to an embodiment of the present application. As shown in fig. 6, the first switch is configured as a MOS transistor. The MOS transistor has a drain connected to a first resistor R1 for forming a first circuit with the first resistor R1, a gate connected to a power supply for forming a second circuit, and a source connected to a single bus interface for forming a circuit with the resistor R3 in the host device due to the conduction between the drain and the source when the electronic device is physically connected to the host device, and the host device is capable of determining the physical connection state of the electronic device according to the decrease of the bus level, and then sending a power supply command, so that the second circuit responds to the power supply command to obtain the power supply voltage to turn the drain and the source off due to the increase of the gate voltage, and then blocks the power supply with the first resistor R1, and the state of the first circuit is switched from the first state to the second state.
As shown in fig. 6, the third circuit may further include a resistor R2, where the control unit MCU is configured to configure the circuit where R2 is located to be in a conductive state, so as to reduce leakage current.
In this embodiment, by adding a mos tube and using the power supply time sequence of the hot plug of the electronic device, that is, the features of first detecting and then supplying power, the circuit features that the pull-down resistor R1 is just inserted and not pulled down after supplying power are ensured to be effective.
In addition, the embodiment of the application provides a control method of electronic equipment, which is applied to the electronic equipment, wherein the electronic equipment comprises a single bus interface, a communication unit, a first circuit, a second circuit and a control unit, wherein the single bus interface is used for communicating with host equipment, one end of the first circuit is connected with the ground, and the other end of the first circuit is connected with the single bus interface, and the method comprises the following steps:
and responding to the connection of the host equipment and the electronic equipment through the single bus interface, and controlling the first circuit to switch from a first state to a second state.
The first circuit is in a channel state when in a first state and is used for detecting the connection state of the electronic equipment and the host equipment through the single bus interface, and is in an open circuit state when in a second state so as to reduce leakage current.
Specifically, in this embodiment, when the electronic device and the host device are physically connected, the voltage drop may be detected by the single bus in the host device through the path state of the first circuit, so as to determine that the electronic device and the host device enter a connection state. After entering the connection state, the embodiment can control the first circuit to switch from the first state to the second state and switch to the disconnection state through the control unit, and can also control the first circuit to switch to the second state through the voltage change by supplying power through the VCC power supply so as to switch to the disconnection state.
The configuration of the first circuit in this embodiment can provide different functions when the electronic device is in different states, so that the host device can detect physical access of the electronic device, and leakage current can be reduced by changing the first circuit to an off state after the physical access is detected.
In an embodiment of the present application, the electronic device further includes a second circuit having one end connected to the single bus interface and the other end connected to the first circuit, and the method includes controlling the state of the first circuit based on the supply voltage of the host device obtained from the single bus interface in response to the host device being connected to the electronic device through the single bus interface.
In one embodiment of the present application, the electronic device further includes a third circuit, one end of the third circuit is connected to the power supply, and the other end of the third circuit is connected to the single bus interface, and the method further includes, when the first circuit is in the second state, configuring the third circuit to be in a conductive state so as to reduce the leakage current.
In an embodiment of the present application, the electronic device includes a plurality of third circuits connected in parallel, and the method further includes configuring the at least two third circuits to be in a conductive state based on a sleep instruction sent by the host device and received by the communication unit from the single bus interface, so as to reduce the leakage current.
The present embodiment is described by taking an electronic device as an example of a keyboard. Fig. 7 is a schematic diagram of an exemplary keyboard and host device connection according to an embodiment of the present application. The first circuit comprises a circuit formed by a drain electrode, a source electrode and a first resistor R2 of a first switch Pmos tube, the communication unit comprises a UART receiving port (UARTRx) and a UART transmitting port (UARTTx), the second circuit comprises a circuit formed by a grid electrode and a power supply of the Pmos tube, the third circuit comprises a circuit formed by switches S1 and R_ Internal pull-up 1 or a circuit formed by switches S2 and R_ Internal pull-up 2, and the control unit is a Controller module.
Specifically, in this embodiment, when the keyboard is physically connected to the host device, since the drain electrode and the source electrode of the PMOS transistor are turned on, the resistor R1 in the host device and R2 can form a circuit, and the host device can determine the physical connection state of the electronic device according to the decrease of the bus level, and then send a power supply command, so that the second circuit responds to the power supply command to obtain the power supply voltage to increase the gate voltage of the PMOS transistor, so that the drain electrode and the source electrode are turned off and blocked from R2, and the state of the first circuit is switched from the first state to the second state.
In this embodiment, during the whole keyboard connection period, because VCC is always powered, the PMOS transistor is equivalent to cutting off the pull-down resistor R2, so the pull-down resistor R2 will not be divided or generate leakage current all the time, and therefore the power consumption will be lower. And because there is no voltage division of the pull-down resistor R2, the voltage on Data is higher during sleep, and is less likely to be mistakenly identified as a low signal.
Specifically, when the host device requests the keyboard to sleep, the host device sends a signal of a sleep instruction to the keyboard through the Data line, the MCU on the keyboard receives the signal on the UART module, specifically, the UART_Rx submodule perceives that the signal is received, and the signal is transferred to the CPU, and the CPU knows that the signal is the sleep instruction after translating the signal, so that the Controller is informed to carry out sleep control on each submodule of the system. For example, the controller will switch the Data signal line from uart_tx to the internal pull-up resistor to ensure that this line is still high, i.e. the control unit controls switch S1 to connect to r_ Internal pull-up 1, and the third circuit forms a pass state. In addition, the controller cuts the Data signal line from the connection of UART_Rx to the internal pull-up resistor, so as to ensure stronger pull-up capability, namely, the control unit controls the switch S2 to be connected with R_ Internal pull-up 2, the second and third circuits also form a channel state, and simultaneously, the UART_Tx/UART_Rx is put into a dormant state so as to save power consumption.
In one embodiment of the present application, the method further includes, in response to receiving a key command, configuring the third circuit to be turned off and configuring the communication unit to be turned on with the single bus interface when the electronic device processes the sleep state, so as to send a wake-up command to the host device through the communication unit, so that the host device responds to the key command.
Specifically, the keyboard of this embodiment further includes a scanning module, configured to detect whether a key core of the keyboard has a key command, and after the key command is scanned, the processor CPU receives the key command and configures the third circuit to be disconnected, specifically, the controller controls the switch S1 and the r_ Internal pull-up 1 to be disconnected so as to be connected to uart_rx, and the controller controls the switch S2 and the r_ Internal pull-up 2 to be disconnected so as to be connected to uart_tx, where the third circuit forms an open circuit state, and the communication unit is connected to the single bus interface. Then, the CPU of the present embodiment transmits a wake-up command to the host device via the communication unit, such as uart_tx, so that the host device responds to the key command.
According to the embodiment, on the premise that the original keyboard function is not affected, the first circuit and the second circuit formed by the PMOS tube are designed on the premise that normal dormancy and awakening can be achieved, different functions can be exerted by the PMOS tube under different modes of the keyboard and the host equipment, physical access of the keyboard can be detected, and overall leakage current can be further reduced.
In addition, an embodiment of the present application provides an electronic device control apparatus, which is applied to an electronic device, including:
The control module is used for responding to the connection of the host equipment and the electronic equipment through the single bus interface and controlling the first circuit to be switched from a first state to a second state, wherein when the first circuit is in the first state, the first circuit is in a passage state and is used for detecting the connection state of the electronic equipment and the host equipment through the single bus interface;
when the first circuit is in the second state, the first circuit is in an open state so as to reduce leakage current.
In an embodiment of the present application, the control module is specifically configured to control, in response to the host device and the electronic device being connected through the single bus interface, a state of the first circuit based on a supply voltage obtained from the single bus interface for the host device.
In an embodiment of the present application, the control module is specifically configured to configure the third circuit in a conductive state when the first circuit is in the second state, so as to reduce the leakage current.
In an embodiment of the present application, the control module is specifically configured to configure the at least two third circuits to be in a conductive state based on a sleep command sent by the host device and received by the communication unit from the single bus interface, so as to reduce the leakage current.
In an implementation of the present application, the control module is further specifically configured to, in response to receiving a key command when the electronic device processes the sleep state, configure the third circuit to be disconnected, and configure the communication unit to be connected to the single bus interface, so as to send a wake-up command to the host device through the communication unit, so that the host device responds to the key command.
According to embodiments of the present disclosure, the present disclosure also provides an apparatus and a readable storage medium.
Fig. 8 shows a schematic block diagram of an example device 800 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 8, the apparatus 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.
Various components in the device 800 are connected to the I/O interface 805, including an input unit 806, such as a keyboard, a mouse, etc., an output unit 807, such as various types of displays, speakers, etc., a storage unit 808, such as a magnetic disk, optical disk, etc., and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the respective methods and processes described above, for example, a control method of an electronic apparatus. For example, in some embodiments, the control method of the electronic device may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 800 via ROM 802 and/or communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the control method of the electronic device described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the control method of the electronic device by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), integrated Systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include being implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be a special or general purpose programmable processor, operable to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user, for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback), and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. An electronic device includes a single bus interface,
A communication unit that communicates with a host device through the single bus interface;
one end of the first circuit is connected with the ground, and the other end of the first circuit is connected with the single bus interface;
Wherein the first circuit comprises a first state and a second state,
When the first circuit is in a first state, the first circuit is in a channel state and is used for detecting the connection state of the electronic equipment and the host equipment by the host equipment;
when the first circuit is in the second state, the first circuit is in an open state so as to reduce leakage current.
2. The electronic device of claim 1, further comprising:
A second circuit, one end of which is connected with the single bus interface, and the other end of which is connected with the first circuit,
The second circuit controls a state of the first circuit based on a supply voltage obtained from the single bus interface for the host device.
3. The electronic device of claim 2, the first circuit comprising a first resistor and a first switch in series, the second circuit being connected with the first switch of the first circuit;
And the second circuit obtains the power supply voltage of the host device through the single bus interface to control the first switch to be switched from a first state to a second state in response to the connection of the electronic device and the host device.
4. The electronic device of any of claims 1-3, further comprising a third circuit having one end connected to a power source and the other end connected to the single bus interface;
And when the first circuit is in the second state, the third circuit is configured to be in a conducting state so as to reduce the leakage current.
5. The electronic device of claim 1, comprising a plurality of third circuits connected in parallel and a control unit configured to configure the at least two third circuits to be in a conductive state according to a sleep instruction sent by a host device received from the single bus interface, so as to reduce the leakage current.
6. An electronic device control method is applied to an electronic device, the electronic device comprises a single bus interface,
A communication unit that communicates with a host device through the single bus interface;
one end of the first circuit is connected with the ground, and the other end of the first circuit is connected with the single bus interface;
Responding to the connection of the host equipment and the electronic equipment through the single bus interface, and controlling the first circuit to switch from a first state to a second state;
When the first circuit is in a first state, the first circuit is in a channel state and is used for detecting the connection state of the electronic equipment and the host equipment through the single bus interface by the host equipment;
when the first circuit is in the second state, the first circuit is in an open state so as to reduce leakage current.
7. The electronic device further comprises a second circuit, one end of which is connected with the single bus interface, and the other end of which is connected with the first circuit, the method comprises responding to the connection of the host device and the electronic device through the single bus interface, and the second circuit controls the state of the first circuit based on the power supply voltage of the host device obtained from the single bus interface.
8. The electronic equipment further comprises a third circuit, one end of the third circuit is connected with a power supply, and the other end of the third circuit is connected with the single bus interface;
the method further includes configuring the third circuit to be in a conductive state when the first circuit is in a second state to reduce the leakage current.
9. The electronic device comprises a plurality of third circuits connected in parallel, and the method further comprises configuring the at least two third circuits to be in a conducting state based on a sleep instruction sent by the host device and received by the communication unit from the single bus interface, so as to reduce the leakage current.
10. The method of claim 9, further comprising:
And under the condition that the electronic equipment processes the dormant state, responding to receiving a key instruction, configuring the third circuit to be disconnected, and configuring the communication unit to be conducted with the single bus interface so as to send a wake-up instruction to the host equipment through the communication unit, so that the host equipment responds to the key instruction.
CN202411745392.4A 2024-11-29 2024-11-29 Electronic device and control method of electronic device Pending CN119882510A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202411745392.4A CN119882510A (en) 2024-11-29 2024-11-29 Electronic device and control method of electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202411745392.4A CN119882510A (en) 2024-11-29 2024-11-29 Electronic device and control method of electronic device

Publications (1)

Publication Number Publication Date
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