CN119920279A - A wireless passive ferroelectric memory - Google Patents

Abstract

The present application discloses a wireless passive ferroelectric memory. The wireless passive ferroelectric memory includes: an antenna, a radio frequency analog front end, a digital baseband and a ferroelectric random access memory; the antenna is configured to receive signals and transmit signals; the radio frequency analog front end is configured to convert digital signals into radio frequency signals; the digital baseband is connected between the radio frequency analog front end and the ferroelectric random access memory, and is configured to cooperate with the radio frequency analog front end to store external data in the ferroelectric random access memory or output the data stored in the ferroelectric random access memory to the outside. In this way, the wireless passive ferroelectric memory uses the unique advantages of low write voltage, low power consumption, high storage density and large storage capacity of the ferroelectric random access memory to solve the problems of high power consumption, small capacity and slow writing of traditional memory, and provides an efficient, reliable and flexible storage solution for radio frequency identification technology.

Description

Wireless passive ferroelectric memory

Technical Field

The application relates to the field of storage, in particular to a wireless passive ferroelectric memory.

Background

Conventional rfid technology is increasingly limited in terms of power consumption, storage capacity, and data persistence.

Specifically, for example, the conventional rfid technology adopts a charged erasable programmable read-only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY, EEPROM) memory array, and the write voltage is up to 15V, so that an additional high-voltage charge pump circuit is required to be designed, which seriously increases the overall power consumption of the chip, and simultaneously causes the overall size of the memory array not to exceed 8MB at present, and has a certain capacity limitation. In addition, the writing speed of the common EEPROM is slower, the writing bandwidth is not high, and the problem of limited data transmission efficiency exists.

Therefore, how to develop a wireless memory chip with low power consumption, large capacity and high security is a current problem to be solved.

Disclosure of Invention

An advantage of the present application is to provide a wireless passive ferroelectric memory, wherein the wireless passive ferroelectric memory fully utilizes the unique advantages of the nonvolatile memory of the ferroelectric random access memory, can be designed to significantly reduce power consumption while guaranteeing reading performance, and prolong the service life of the device, thereby being expected to meet the urgent demands for large data storage in the future.

According to one aspect of the application, a wireless passive ferroelectric memory is provided, comprising an antenna configured to receive signals and transmit signals, a ferroelectric random access memory, a radio frequency analog front end connected to the antenna and configured to convert digital signals into radio frequency signals, and a digital baseband connected between the radio frequency analog front end and the ferroelectric random access memory and configured to interact with the radio frequency analog front end to store external data to the ferroelectric random access memory or to output data stored in the ferroelectric random access memory to the outside, wherein the radio frequency analog front end comprises an impedance matching network, a rectifying circuit, a voltage stabilizing circuit, a reference circuit and a modem, the impedance matching network is coupled to the antenna, the rectifying circuit and the voltage stabilizing circuit are connected between the impedance matching network and the digital baseband and configured to convert radio frequency signals into global power supply to provide working voltages for the wireless passive ferroelectric memory, one end of the reference circuit is connected to the rectifying circuit and the other end is connected to the modem, the reference circuit is configured to read out data from the reference circuit and the digital baseband is configured to verify the data from the external to the digital baseband and read-write data from the reference circuit and the digital baseband.

In an embodiment of the wireless passive ferroelectric memory according to the present application, the radio frequency analog front end further includes a power-on reset circuit, the power-on reset circuit is connected to the rectifying circuit and configured to generate a reset signal by detecting the rectified voltage, and the digital baseband further includes an initialization module. The initialization module is configured to initialize the wireless passive ferroelectric memory.

In one embodiment of the wireless passive ferroelectric memory according to the present application, the radio frequency analog front end further comprises a clock circuit connected to the digital baseband and configured to generate a clock signal required by the digital baseband.

In one embodiment of the wireless passive ferroelectric memory according to the present application, the clock circuit includes an oscillator, a temperature sensor and a temperature compensation circuit, the temperature sensor and the temperature compensation circuit are connected to the oscillator, the temperature sensor is configured to detect an operating temperature of the clock circuit, and the temperature compensation circuit adjusts a parameter of the oscillator based on the operating temperature of the clock circuit.

In one embodiment of the wireless passive ferroelectric memory according to the present application, the digital baseband further comprises a clock control module configured to generate, distribute and manage clock signals of the wireless passive ferroelectric memory.

In an embodiment of the wireless passive ferroelectric memory according to the present application, the digital baseband further comprises an encoding module, a decoding module, a command processing module and a pseudo-random number module, wherein the command processing module is used for processing a command signal, the encoding module is configured to encode a received signal and convert an analog signal into a digital signal, the decoding module is configured to decode the baseband signal, and the pseudo-random number module is configured to generate a unique random number by using the pseudo-random number.

In one embodiment of the wireless passive ferroelectric memory according to the present application, the ferroelectric random access memory comprises a cell array, a control signal module and a sense amplifier buffer, wherein the control signal module and the sense amplifier buffer are connected to the cell array, the cell array comprises a plurality of memory cells, the control signal module is configured to generate an interaction signal for controlling the memory cells so as to control the read-write state of each memory cell, and the sense amplifier buffer comprises a sense amplifier and an input-output buffer.

In one embodiment of the wireless passive ferroelectric memory according to the present application, the ferroelectric random access memory further comprises a plurality of pre-charge transistors, each group of the pre-charge transistors corresponds to at least one of the memory cells, and each group of the pre-charge transistors comprises at least one of the pre-charge transistors connected to a preset signal line.

In one embodiment of the wireless passive ferroelectric memory according to the present application, each of the memory cells is connected to one bit line, the ferroelectric random access memory further comprises a reference level generating module configured to generate a reference level, and comprises a first reference cell connected to a bit line, a second reference cell connected to another bit line, and a control transistor connected between the two bit lines.

In one embodiment of the wireless passive ferroelectric memory according to the present application, the first reference cell includes a first reference transistor, a first reference ferroelectric capacitor, and a first write-back transistor, the first reference transistor has a parameter that is completely identical to a parameter of a gate transistor of the memory cell, the first reference ferroelectric capacitor has a parameter that is completely identical to a parameter of a ferroelectric capacitor of the memory cell, the second reference cell includes a second reference transistor, a second reference ferroelectric capacitor, and a second write-back transistor, the second reference transistor has a parameter that is completely identical to a parameter of a gate transistor of the memory cell, and the second reference ferroelectric capacitor has a parameter that is completely identical to a parameter of a ferroelectric capacitor of the memory cell.

Further objects and advantages of the present application will become fully apparent from the following description and the accompanying drawings.

These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the appended claims.

Drawings

The above and other objects, features and advantages of the present application will become more apparent by describing embodiments of the present application in more detail with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, and not constitute a limitation to the application. In the drawings, like reference numerals generally refer to like parts or steps.

Fig. 1 illustrates a schematic block diagram of a wireless passive ferroelectric memory according to an embodiment of the present application.

Fig. 2 illustrates a schematic block diagram of a wireless passive ferroelectric memory ferroelectric random access memory according to an embodiment of the present application.

Fig. 3 illustrates a partial circuit schematic diagram of a wireless passive ferroelectric memory ferroelectric random access memory according to an embodiment of the present application.

Fig. 4 illustrates a timing diagram schematic diagram of a wireless passive ferroelectric memory ferroelectric random access memory according to an embodiment of the present application.

Detailed Description

Hereinafter, exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application and not all embodiments of the present application, and it should be understood that the present application is not limited by the example embodiments described herein.

It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number. "plurality" means two or more.

Although ordinal numbers of "first," "second," etc., for example, will be used to describe various components, those components are not limited herein. The term is used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component, without departing from the teachings of the present inventive concept. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, operations, elements, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, operations, elements, or groups thereof.

As shown in fig. 1 to 4, a wireless passive ferroelectric memory according to an embodiment of the present application is illustrated. Considering that the ferroelectric random access memory 40 (Ferroelectric Random Access MemoryRandom Access Memory, FRAM) has non-volatility, the application adopts FRAM as a storage medium of the radio frequency identification technology, and provides a new idea for the design and optimization of the radio frequency identification technology by the unique advantages of low writing voltage, low power consumption, high storage density and large storage capacity.

The wireless passive ferroelectric memory does not need an external power supply to supply power, can acquire energy through a wireless energy acquisition technology (such as radio frequency energy acquisition) to realize internal power supply, and transmits and stores data through wireless signals. The ferroelectric random access memory 40 has a nonvolatile property, and data can be stored for a long period of time even if a wireless signal is interrupted or power is lost.

Specifically, as shown in fig. 1, the wireless passive ferroelectric memory includes an antenna 10, a radio frequency analog front end 20, a digital baseband 30, and a ferroelectric random access memory 40. The antenna 10 is configured to receive signals and transmit signals for wireless signal transmission, in particular to convert radio frequency signals from electromagnetic waves to electrical signals during reception of signals and to convert electrical signals to electromagnetic waves during transmission of signals. The radio frequency analog front end 20 is connected between the antenna 10 and the digital baseband 30 and is configured to convert digital signals from the digital baseband 30 into radio frequency signals. The digital baseband 30 is connected between the rf analog front end 20 and the ferroelectric random access memory 40, and is configured to cooperate with the rf analog front end 20 to store external data to the ferroelectric random access memory 40 or to output data stored in the ferroelectric random access memory 40 to the outside.

More specifically, the radio frequency analog front end 20 includes an impedance matching network 21, a rectifying circuit 22, a voltage stabilizing circuit 23, a reference circuit 24, and a modem 25. The impedance matching network 21 is coupled to the antenna 10, and is mainly used for ensuring impedance matching between the antenna 10 and the rf front-end circuit, so as to maximize energy transmission efficiency and meet the wavelength band required by the protocol. The rectifying circuit 22 and the voltage stabilizing circuit 23 are connected between the impedance matching network 21 and the digital baseband 30, and are configured to convert a radio frequency signal into a global power supply, and provide a power supply working voltage VDD for the wireless passive ferroelectric memory, so as to realize power supply under the condition of no external power supply. The voltage stabilizing circuit 23 is connected to the digital baseband 30, and the rectifying circuit 22 is connected between the impedance matching network 21 and the voltage stabilizing circuit 23. The reference circuit 24 has one end connected to the rectifying circuit 22 and the other end connected to the voltage stabilizing circuit 23 and the modem 25. The reference circuit 24 is configured to provide a global reference voltage Vref and a reference current Ibias. The modem 25 is connected between the impedance matching network 21 and the digital baseband 30, and is configured to receive data transmitted from an external reader/writer, demodulate fundamental command (Commond) signals, and transmit data from the digital baseband 30 to an external reader/writer. The modem 25 uses the principle of backscatter modulation to enable an external reader to receive data from the digital baseband 30.

In an embodiment of the present application, the rf analog front end 20 further includes a power-on reset circuit. The power-on reset circuit is connected to the rectifying circuit 22 and is configured to generate a reset (Rst) signal by detecting a rectified voltage Vrect in radio frequency identification (Radio Frequency Identification, RFID) to enable initialization when the wireless passive ferroelectric memory is powered on.

In one embodiment of the present application, the RF analog front end 20 further includes a clock circuit 26. The clock circuit 26 is coupled to the digital baseband 30 and is configured to generate a Clock (CLK) signal required by the digital baseband 30.

It is worth mentioning that the clock circuit 26 may be affected by ambient temperature or voltage fluctuations, resulting in unstable clock signals. The application provides that clock stability can be improved by introducing a temperature compensation mechanism into the clock circuit 26, clock drift can be reduced by adopting an oscillator with higher precision, and clock precision can be improved by synchronizing clock signals with external equipment.

Accordingly, in one embodiment of the present application, the clock circuit 26 includes an oscillator (not shown), a temperature sensor (not shown), and a temperature compensation circuit (not shown). The temperature sensor and the temperature compensation circuit are connected to the oscillator. The temperature sensor is configured to detect an operating temperature of the clock circuit 26, and the temperature compensation circuit adjusts a parameter of the oscillator, e.g., a frequency of the oscillator, based on the operating temperature of the clock circuit 26.

In another embodiment of the present application, the oscillator in the clock circuit 26 is an oscillator with higher precision.

In yet another embodiment of the present application, the clock circuit 26 is configured for clock synchronization of an external device.

It will be appreciated that the stability of the clock signal may also be improved by other means, for example by stabilizing the voltage in the clock circuit 26, ageing compensation, improved immunity to interference, the use of a phase-locked loop and a digital phase-locked loop.

When the wireless passive ferroelectric memory detects a valid command signal generated from the outside, data is read out from the ferroelectric random access memory 40 according to the command, and a corresponding Response (Response) signal is generated to the modem 25, transmitted to the external source, or information transmitted from the external source is stored in the ferroelectric random access memory 40.

Accordingly, the digital baseband 30 is further configured to return a Response (Response) signal to the modem 25 based on signals of the radio frequency analog front end 20, e.g., a power supply operating voltage signal, a reset signal, a clock signal, a command signal.

Specifically, the digital baseband 30 includes an encoding module 37, a decoding module 32, and a command processing module 35. The command processing module 35 is configured to process command signals. The encoding module 37 is configured to encode the received signal and to convert the analog signal into a digital signal. The decoding module 32 is configured to decode the baseband signal.

In one embodiment of the present application, the digital baseband 30 further includes a pseudo-random number module 34. The pseudo-random number module 34 is configured to generate a unique random number from the pseudo-random number, wherein the unique random number may be used as an encryption key to ensure the security of data transmission.

In one embodiment of the present application, the digital baseband 30 further includes a clock control module 36. The clock control module 36 is configured to generate, distribute and manage clock signals for the wireless passive ferroelectric memory to ensure that the modules cooperate in accordance with a predetermined cadence.

In an embodiment of the present application, the digital baseband 30 further includes an initialization module 31. The initialization module 31 is configured to initialize the wireless passive ferroelectric memory. Specifically, the initialization module 31 may initialize the wireless passive ferroelectric memory based on the reset signal.

It should be noted that, considering that the performance of the ferroelectric random access memory 40 may be affected by environmental factors (e.g. temperature, radiation) and may cause data damage or read errors, the present application proposes to provide the verification module 33 for verifying the read data of the ferroelectric random access memory 40. Specifically, the check may be performed by a cyclic redundancy check code (Cyclic Redundancy Check, CRC).

The digital baseband 30 communicates with the ferroelectric random access memory 40 via a word line WL (x 64), a bus interface DBI and a data bus DBO, a control signal Read Enable (RE) signal, a Write Enable (WE) signal, a sense amplifier enable (SEN) signal. Word Lines (WL) are used to gate corresponding Bit lines (Bit lines, BL), wherein the Bit Lines (BL) are used to transfer data and Bit.

Fig. 2 shows an exemplary structure of the ferroelectric random access memory 40. The ferroelectric random access memory 40 includes a cell array 41, a control signal block 42, and a sense amplifier buffer 43. The sense amplifier 431 includes an input-output buffer 432 (i.e., an IO buffer) and a sense amplifier 431. The control signal block 42 and the sense amplification buffer 43 are connected to the cell array 41.

The cell array 41 includes a plurality of memory cells 411. The plurality of memory cells 411 are arranged in rows and columns to form the cell array 41. The number of the memory cells 411 is not limited to the present application, and in one example of the present application, the cell array 41 has 64 rows and 16 columns of the memory cells 411, including 64×16 memory cells 411, i.e., 1024 memory cells 411.

The control signal module 42 is configured to receive a Read Enable (RE) signal, a Write Enable (WE) signal, a sense amplifier enable (SEN) signal, and a Word Line (WL) signal, and is further configured to generate an interaction signal for controlling the memory cells 411 based on the Read Enable (RE) signal, the Write Enable (WE) signal, the sense amplifier enable (SEN) signal, and the Word Line (WL) signal, and in particular, may control a read and write state of each of the memory cells 411.

Each of the sense amplification buffers 43 is connected to at least one of the memory cells 411 for outputting read data or inputting data D [15:0] to be written. In one example of the present application, each of the sense amplification buffers 43 is connected to a column of the memory cells 411, and may be disposed at an end of each column of the memory cells 411.

Fig. 3 shows a partial circuit diagram between the cell array 41 and the sense amplification buffer 43. Each of the sense amplifiers 431 is coupled to a Bit Line (BL) and an inverse Bit Line (Bar, BLB), and is connected to a sense amplifier enable (SEN) Line and a Digital Output (DO) signal Line. The inverse Bit Line (BLB) is logically opposite to the Bit Line (BL), e.g., when the bit line expresses a "1", the inverse Bit Line (BLB) expresses a "0". The sense amplifier 431 connected to the Bit Line (BL) and the inverse Bit Line (BLB) may further amplify signals on the Bit Line (BL) and the inverse Bit Line (BLB). The ferroelectric random access memory 40 is connected to a plurality of Bit Lines (BL) and bit Bar Lines (BLB), for example, a first bit line (BL 1) and a first bit bar line (BLB 1), and a second bit line (BL 2) and a second bit bar line (BLB 2).

Each of the memory cells 411 is connected to an inverted Bit Line (BLB), a Word Line (WL), and a plate line (PLATE LINE, PL). The memory cell 411 includes a gating transistor 4111 and a ferroelectric capacitor 4112. One end of the ferroelectric capacitor 4112 is connected to the gate transistor 4111, and the other end is connected to a Plate Line (PL). The Plate Line (PL) can supply a pulse control signal when reading and writing data to and from the ferroelectric capacitor 4112 of the memory cell 411. The gate of the gating transistor 4111 is connected to a Word Line (WL), one of the other two terminals is connected to the ferroelectric capacitor 4112, and the other one of the other two terminals is connected to an inverted Bit Line (BLB).

The memory cell 411 stores data by controlling the polarization state of the ferroelectric capacitor 4112 through signals of a Word Line (WL), a Plate Line (PL), and a bit line ().

The ferroelectric random access memory 40 further includes a plurality of precharge transistors 44 and a reference level generation module. Each set of said pre-charge transistors 44 corresponds to at least one of said memory cells 411, each set of said pre-charge transistors 44 comprising at least one of said pre-charge transistors 44.

In one example of the present application, each set of the precharge transistors 44 includes three of the precharge transistors 44, and each set of the precharge transistors 44 corresponds to a column of the memory cells 411. Of the three PRE-charge transistors 44, a gate of each of the PRE-charge transistors 44 is connected to a Preset (PRE) signal line, wherein one of the other two ends of each of the two PRE-charge transistors 44 is connected to a common ground line, and the other end is connected to the PRE-charge transistor 44 adjacent thereto.

The reference level generation module is configured to generate a reference level including a first reference unit 451, a second reference unit 452, and a control transistor 453. The first reference cell 451 is connected to a Bit Line (BL), for example, a first bit line (BL 1), the second reference cell 452 is connected to another Bit Line (BL), for example, a second bit line (BL 2), and the control transistor 453 is connected between two bits, for example, between the first bit line (BL 1) and the second bit line (BL 2).

The first reference cell 451 includes a first reference transistor 4511, a first reference ferroelectric capacitor 4512, and a first write-back transistor 4513. The parameters of the first reference transistor 4511 and the gate transistor 4111 of the memory cell 411 are identical, and the parameters of the first reference ferroelectric capacitor 4512 and the ferroelectric capacitor 4112 of the memory cell 411 are identical.

The first reference transistor 4511 and the first reference ferroelectric capacitor 4512 are connected. The first write-back transistor 4513 is connected to the first reference ferroelectric capacitor 4512. Specifically, one end of the first reference ferroelectric capacitor 4512 is connected to the first reference transistor 4511 and the first write-back transistor 4513, and the other end is connected to a reference plate line (REFERENCE PLATE LINE, RPL). The gate of the first reference transistor 4511 is connected to a Read Word Line (RWL), one of the other terminals is connected to the first reference ferroelectric capacitor 4512, and the other terminal is connected to one Bit Line (BL), for example, a first bit Line (BL 1). The gate of the first Write-back transistor 4513 is connected to a Write Word Line (WWL), one of the other two ends is connected to the first reference ferroelectric capacitor 4512, and the other of the other two ends is connected to a reference signal (REFERENCE SIGNAL, RS) line. The Reference Signal (RS) line is used to provide a write back control signal. The Reference Plate Line (RPL), the Read Word Line (RWL), and the Write Word Line (WWL) are used to control reading and writing of the first reference cell 451 and the second reference cell 452. The Reference Plate Line (RPL) is used to provide pulse control signals to the first reference cell 451 and the second reference cell 452. The Write Word Line (WWL) is used to control the writing of the first reference cell 451 and the second reference cell 452. The Read Word Line (RWL) is used to control the readout of the first reference cell 451 and the second reference cell 452.

The second reference cell 452 includes a second reference transistor 4521, a second reference ferroelectric capacitor 4522, and a second write-back transistor 4523. The parameters of the second reference transistor 4521 and the gate transistor 4111 of the memory cell 411 are identical, and the parameters of the second reference ferroelectric capacitor 4522 and the ferroelectric capacitor 4112 of the memory cell 411 are identical.

The second reference transistor 4521 and the second reference ferroelectric capacitor 4522 are connected. The second write-back transistor 4523 is connected to the second reference ferroelectric capacitor 4522. Specifically, one end of the second reference ferroelectric capacitor 4522 is connected to the second reference transistor 4521 and the second write-back transistor 4523, and the other end is connected to an RPL line. The gate of the second reference transistor 4521 is connected to the RWL line, one of the other terminals is connected to the second reference ferroelectric capacitor 4522, and the other terminal is connected to another Bit Line (BL), for example, a second bit line (BL 2). The gate of the second write-back transistor 4523 is connected to a Write Word Line (WWL) line, one of the other ends is connected to the second reference ferroelectric capacitor 4522, and the other end is connected to a common ground (VSS) line.

The gate of the control transistor 453 is connected to an Equalization (EQ) line, and the other two ends are connected to two Bit Lines (BL), for example, a first bit line (BL 1) and a second bit line (BL 2), respectively.

The first reference ferroelectric capacitor 4512 is used for storing data "1", the second reference ferroelectric capacitor 4522 is used for storing data "0", and the control transistor 453 is used for connecting two Bit Lines (BL), for example, a first bit line (BL 1) and a second bit line (BL 2), when reading data, to generate a reference level between data 1 and 0.

Fig. 4 shows a timing chart of writing of the cell array 41 described in fig. 3. First, the enable PRE signal turns on the precharge transistor 44, precharging the Bit Line (BL) and the inverted Bit Line (BLB), for example, the first bit line (BL 1) and the second bit line (BL 2), the first inverted bit line (BLB 1) and the second inverted bit line (BLB 2). Then, the Preset (PRE) signal is low and ready to start writing data, the Word Line (WL) and the Read Word Line (RWL) are activated simultaneously, a positive level pulse is given to the Plate Line (PL) and the Reference Plate Line (RPL), the ferroelectric capacitor 4112 data is read out to the bit line BLB, and at the same time, the first reference cell 451 and the second reference cell 452 make at least one Bit Line (BL), for example, the first bit line (BL 1) outputs "1", the level is V1, and at least one Bit Line (BL), for example, the second bit line (BL 2) outputs "0", the level is V0. The Equalization (EQ) signal is then enabled to turn on the control transistor 453, shorting and sharing charge between each two of the Bit Lines (BL), e.g., the first bit line (BL 1) and the second bit line (BL 2), such that a common reference voltage (v0+v1)/2 is generated on each two of the Bit Lines (BL), e.g., the first bit line (BL 1) and the second bit line (BL 2), followed by the sense amplifier enable (SEN) signal activating the sense amplifier 431 to distinguish the voltages on the respective Bit Lines (BL) and read data. Finally, the write back signal is enabled and a positive voltage pulse is given to the refresh Reference Signal (RS) to write back data for the first reference cell 451 and the second reference cell 452.

In summary, the wireless passive ferroelectric memory is elucidated. The application adopts the ferroelectric memory as a storage medium, successfully solves the limitations of the traditional electrified erasable programmable read-only memory in power consumption, capacity and writing speed by utilizing the unique advantages of low writing voltage, low power consumption, high storage density and large storage capacity of the ferroelectric memory, namely, the problems of high power consumption, small capacity, slow writing and the like of the traditional electrified erasable programmable read-only memory, and provides a more efficient, reliable and flexible storage solution for the radio frequency identification technology. The ferroelectric memory is adopted, a high-voltage charge pump is not needed, the power consumption is obviously reduced, the storage density and the writing bandwidth are higher, the limit of the electrified erasable programmable read-only memory is broken through, and the ferroelectric memory has the advantages of high speed, low power consumption, long holding time and the like.

The application and its embodiments have been described above with no limitation, and the actual construction is not limited to the embodiments of the application as shown in the drawings. In summary, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical solution will not be creatively devised without departing from the gist of the present application, and the structural manner and the embodiment are all intended to be within the protection scope of the present application.

Claims (10)

1. A wireless passive ferroelectric memory is characterized by comprising an antenna configured to receive signals and transmit signals; the system comprises a ferroelectric random access memory, a radio frequency analog front end, a digital baseband, a reference circuit, a reference voltage and a reference current, wherein the radio frequency analog front end is connected between the antenna and is configured to convert a digital signal into a radio frequency signal, the digital baseband is connected between the radio frequency analog front end and the ferroelectric random access memory and is configured to be matched with the radio frequency analog front end to store external data into the ferroelectric random access memory or output data stored in the ferroelectric random access memory to the outside, the radio frequency analog front end comprises an impedance matching network, a rectifying circuit, a voltage stabilizing circuit, a reference circuit and a modem, the impedance matching network is coupled between the antenna, the rectifying circuit and the voltage stabilizing circuit are connected between the impedance matching network and the digital baseband and are configured to convert the radio frequency signal into a global power supply to provide working voltage for the wireless passive ferroelectric memory, one end of the reference circuit is connected to the rectifying circuit and the other end of the voltage stabilizing circuit is connected with the modem and is configured to provide global reference voltage and reference current, the modem is connected between the impedance matching network and the impedance matching network, the voltage stabilizing circuit is configured to the reference circuit, the digital baseband is configured to read out of the digital baseband and the digital baseband is configured to read and write data from the external memory, and the digital baseband is configured to read and read data from the external.

2. The wireless passive ferroelectric memory of claim 1, wherein the radio frequency analog front end further comprises a power-on reset circuit coupled to the rectifier circuit configured to generate a reset signal by detecting a rectified voltage, and wherein the digital baseband further comprises an initialization module configured to initialize the wireless passive ferroelectric memory.

3. The wireless passive ferroelectric memory according to claim 2, wherein said radio frequency analog front end further comprises a clock circuit, said clock circuit being coupled to said digital baseband and configured to generate a clock signal required by said digital baseband.

4. The wireless passive ferroelectric memory of claim 3, wherein the clock circuit comprises an oscillator, a temperature sensor and a temperature compensation circuit, the temperature sensor and the temperature compensation circuit being coupled to the oscillator, the temperature sensor being configured to detect an operating temperature of the clock circuit, the temperature compensation circuit adjusting a parameter of the oscillator based on the operating temperature of the clock circuit.

5. The wireless passive ferroelectric memory of claim 3, wherein said digital baseband further comprises a clock control module configured to generate, distribute, and manage clock signals for said wireless passive ferroelectric memory.

6. The wireless passive ferroelectric memory according to claim 5, wherein the digital baseband further comprises an encoding module, a decoding module, a command processing module, and a pseudo-random number module, wherein the command processing module is configured to process a command signal, wherein the encoding module is configured to encode a received signal and to convert an analog signal to a digital signal, wherein the decoding module is configured to decode a baseband signal, wherein the pseudo-random number module is configured to generate a unique random number from a pseudo-random number.

7. The wireless passive ferroelectric memory according to claim 1, wherein the ferroelectric random access memory comprises a cell array, a control signal module and a sense amplifier buffer, wherein the control signal module and the sense amplifier buffer are connected to the cell array, wherein the cell array comprises a plurality of memory cells, wherein the control signal module is configured to generate an interaction signal for controlling the memory cells to control a read-write state of each of the memory cells, and wherein the sense amplifier buffer comprises a sense amplifier and an input-output buffer.

8. The wireless passive ferroelectric memory according to claim 7, further comprising a plurality of precharge transistors, each of said precharge transistors corresponding to at least one of said memory cells, each of said precharge transistors comprising at least one of said precharge transistors connected to a preset signal line.

9. The wireless passive ferroelectric memory according to claim 8, wherein each of the memory cells is connected to an inverted bit line, wherein the ferroelectric random access memory further comprises a reference level generation module configured to generate a reference level, comprising a first reference cell, a second reference cell, and a control transistor, wherein the first reference cell is connected to a bit line, wherein the second reference cell is connected to another bit line, and wherein the control transistor is connected between two bit lines.

10. The wireless passive ferroelectric memory of claim 9, wherein the first reference cell comprises a first reference transistor, a first reference ferroelectric capacitor, and a first write-back transistor, wherein parameters of the first reference transistor are substantially identical to parameters of a gate transistor of the memory cell, wherein parameters of the first reference ferroelectric capacitor and parameters of a ferroelectric capacitor of the memory cell are substantially identical, wherein the second reference cell comprises a second reference transistor, a second reference ferroelectric capacitor, and a second write-back transistor, wherein parameters of the second reference transistor are substantially identical to parameters of a gate transistor of the memory cell, and wherein parameters of the second reference ferroelectric capacitor and parameters of a ferroelectric capacitor of the memory cell are substantially identical.