CN119920289A - Memory operation method, memory and storage system - Google Patents
Memory operation method, memory and storage system Download PDFInfo
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- CN119920289A CN119920289A CN202411998631.7A CN202411998631A CN119920289A CN 119920289 A CN119920289 A CN 119920289A CN 202411998631 A CN202411998631 A CN 202411998631A CN 119920289 A CN119920289 A CN 119920289A
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Abstract
The disclosure provides a memory operation method, a memory and a memory system, and relates to the technical field of memories. The memory comprises a memory cell array, wherein the memory cells in the memory cell array comprise control gates and memory gates which are connected. The method includes applying a first voltage to a control gate of a selected memory cell in the memory cell array, applying a first programming voltage for a first duration to the memory gate of the selected memory cell, then performing a verify operation on the selected memory cell, and applying a second programming voltage for a second duration to the memory gate of the selected memory cell if a result of the verify operation is failed, wherein the second duration is greater than the first duration and/or the second programming voltage is greater than the first programming voltage. The method improves the programming efficiency of the OTP memory cell and reduces the power leakage.
Description
Technical Field
The disclosure relates to the technical field of memories, and in particular relates to a memory operation method, a memory and a memory system.
Background
One-time programmable (OneTimeProgrammable, OTP) memory is a nonvolatile memory supporting one-time programming, and is widely applied to chips of memories such as flash memories and dynamic random access memories. OTP memory can only be programmed once, and the written data cannot be changed, and is typically used to store some important data that does not need modification.
The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and therefore it may include information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The disclosure aims to provide a memory operation method, a memory and a memory system.
Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.
According to one aspect of the disclosure, a memory operation method is provided, the memory comprises a memory cell array, memory cells in the memory cell array comprise a control gate and a memory gate which are connected, the method comprises the steps of applying a first voltage to the control gate of a selected memory cell in the memory cell array, applying a first programming voltage for a first duration to the memory gate of the selected memory cell, performing a verification operation to the selected memory cell, and applying a second programming voltage for a second duration to the memory gate of the selected memory cell in response to the result of the verification operation being failed, wherein the second duration is longer than the first duration, and/or the second programming voltage is longer than the first programming voltage.
According to one embodiment of the disclosure, applying a second programming voltage for a second duration to the memory gate of the selected memory cell in response to the result of the verify operation being failed includes increasing the first duration by a first predetermined step to obtain the second step and/or increasing the first programming voltage by a second predetermined step to obtain the second programming voltage in response to the result of the verify operation being failed.
According to one embodiment of the disclosure, applying a second programming voltage for a second duration to a storage gate of the selected storage unit in response to a result of the verification operation being failed includes obtaining a current programming number of the selected storage unit, determining whether the current programming number of the selected storage unit is less than a preset programming number threshold in response to the result of the verification operation being failed, and applying the second programming voltage for the second duration to the storage gate of the selected storage unit in response to determining that the current programming number of the selected storage unit is less than the preset programming number threshold.
According to one embodiment of the disclosure, applying a first programming voltage for a first duration to a memory gate of the selected memory cell includes obtaining the first programming voltage as a preset programming voltage that is a programming voltage that a preset proportion of memory gates can be successfully programmed through testing in response to determining that a current programming number of the selected memory cell is 0, and applying the first programming voltage for the first duration to the memory gate of the selected memory cell.
According to one embodiment of the disclosure, the memory cell array comprises a memory cell pair with the same logic address, the memory cell pair comprises one memory cell and a redundant memory cell corresponding to the memory cell pair, the method further comprises the steps of applying the first voltage to a control gate of the redundant memory cell corresponding to the selected memory cell, applying the first programming voltage for the first duration to a memory gate of the redundant memory cell, performing the verification operation on the redundant memory cell, and applying the second programming voltage for the second duration to the memory gate of the redundant memory cell in response to determining that the redundant memory cell fails to be programmed according to a result of the verification operation.
According to one embodiment of the disclosure, the control gate of the selected memory cell is connected to a first word line, the gate of the memory gate of the selected memory cell is connected to a second word line, applying a first voltage to the control gate of the selected memory cell in the memory cell array comprises applying the first voltage to the first word line for a first period of time, and applying a first programming voltage to the memory gate of the selected memory cell for a first period of time comprises applying the first programming voltage to the second word line for the first period of time.
According to one embodiment of the disclosure, the memory cells in the memory cell array further comprise a first end connected to the control gate and a second end connected to the memory gate, the control gate and the memory gate being both located between the first end and the second end, the first end of the selected memory cell being connected to a first bit line, the second end of the selected memory cell being floating, a first voltage being applied to the control gate of the selected memory cell in the memory cell array, further comprising applying a ground voltage on the first bit line during the first period.
According to an embodiment of the present disclosure, performing a verify operation on the selected memory cell includes continuing to apply the first voltage on the first word line for a second period of time subsequent to the first period of time, and applying a verify voltage on the second word line for the second period of time.
In accordance with an embodiment of the present disclosure, performing a verify operation on the selected memory cell further includes applying a ground voltage on the first bit line during the second period of time.
According to an embodiment of the present disclosure, applying a second programming voltage for a second duration to the memory gate of the selected memory cell includes continuing to apply the first voltage on the first word line for a third period of time subsequent to the second period of time, and applying the second programming voltage for the second duration on the second word line for the third period of time.
According to an embodiment of the present disclosure, applying a second programming voltage for a second duration to the memory gate of the selected memory cell further includes applying a ground voltage on the first bit line during the third period.
According to an embodiment of the disclosure, control gates of unselected memory cells in the memory cell array are connected to a third word line, and gates of memory gates of the unselected memory cells are connected to a fourth word line, the method further includes applying a second voltage on the third word line during the first period, the second voltage being less than the first voltage, and applying a program inhibit voltage on the fourth word line during the first period.
According to one embodiment of the disclosure, the first terminal of the unselected memory cell is connected to a second bit line, and the second terminal of the unselected memory cell is floating, and the method further includes applying a third voltage on the second bit line during the first period, the third voltage being greater than a ground voltage.
According to yet another aspect of the present disclosure, there is provided a memory including a memory cell array including control gates and memory gates connected, a peripheral circuit coupled to the memory cell array and configured to apply a first voltage to the control gates of selected memory cells of the memory cell array, apply a first programming voltage to the memory gates of the selected memory cells for a first duration, perform a verify operation to the selected memory cells, and apply a second programming voltage to the memory gates of the selected memory cells for a second duration in response to a result of the verify operation being failed, wherein the second duration is greater than the first duration and/or the second programming voltage is greater than the first programming voltage.
According to an embodiment of the disclosure, a control gate of the selected memory cell is connected to a first word line, a gate of the memory gate of the selected memory cell is connected to a second word line, the peripheral circuit comprises a control circuit, a voltage generator, a word line driver and a bit line driver, wherein the voltage generator is configured to generate a first voltage, the control circuit is configured to control the word line driver to apply the first voltage on the first word line for a first period of time, the voltage generator is further configured to generate the first programming voltage, and the control circuit is further configured to control the word line driver to apply the first programming voltage for the first period of time on the second word line for the first period of time.
According to an embodiment of the disclosure, the memory cells in the memory cell array further comprise a first terminal connected to the control gate and a second terminal connected to the memory gate, the control gate and the memory gate being both located between the first terminal and the second terminal, the first terminal of the selected memory cell being connected to a first bit line, the second terminal of the selected memory cell being floating, the control circuit being further configured to control the bit line driver to apply a ground voltage on the first bit line during the first period.
According to an embodiment of the disclosure, the voltage generator is further configured to generate a verification voltage, the control circuit is further configured to control the word line driver to continue applying the first voltage on the first word line for a second period of time subsequent to the first period of time, and the control circuit is further configured to control the word line driver to apply the verification voltage on the second word line for the second period of time.
According to an embodiment of the present disclosure, the control circuit is further configured to control the bit line driver to apply a ground voltage on the first bit line during the second period of time.
According to an embodiment of the present disclosure, the voltage generator is further configured to generate a second programming voltage, the control circuit is further configured to control the word line driver to continue applying the first voltage on the first word line for a third period of time after the second period of time, and the control circuit is further configured to control the word line driver to apply the second programming voltage for the second period of time on the second word line for the third period of time.
According to an embodiment of the present disclosure, the control circuit is further configured to control the bit line driver to apply a ground voltage on the first bit line during the third period.
According to an embodiment of the disclosure, a control gate of an unselected memory cell in the memory cell array is connected to a third word line, a gate of a memory gate of the unselected memory cell is connected to a fourth word line, the voltage generator is further configured to generate a second voltage, which is less than the first voltage, the control circuit is further configured to control the word line driver to apply the second voltage on the third word line during the first period, the voltage generator is further configured to generate a program inhibit voltage, and the control circuit is further configured to control the word line driver to apply the program inhibit voltage on the fourth word line during the first period.
According to an embodiment of the disclosure, the first terminal of the unselected memory cell is connected to a second bit line, the second terminal of the unselected memory cell is floating, the voltage generator is further configured to generate a third voltage, the third voltage being greater than a ground voltage, and the control circuit is further configured to control the bit line driver to apply the third voltage on the second bit line during the first period.
According to an embodiment of the present disclosure, the control circuit is further configured to increase the first time length by a first predetermined step length to obtain the second step length and/or increase the first program voltage by a second predetermined step length to obtain the second program voltage in response to the result of the verifying operation being failed.
According to an embodiment of the disclosure, the control circuit is further configured to obtain a current programming number of the selected memory cell, determine whether the current programming number of the selected memory cell is less than a preset programming number threshold in response to a result of the verification operation being failed, and apply the second programming voltage for the second duration to a memory gate of the selected memory cell in response to determining that the current programming number of the selected memory cell is less than the preset programming number threshold.
According to an embodiment of the disclosure, the control circuit is further configured to obtain the first programming voltage as a preset programming voltage, which is a programming voltage that a preset proportion of storage gates can be successfully programmed by testing, in response to determining that the current programming number of the selected storage unit is 0.
According to one embodiment of the disclosure, the memory cell array comprises a memory cell pair with the same logic address, the memory cell pair comprises one memory cell and a redundant memory cell corresponding to the memory cell pair, the control circuit is further configured to apply the first voltage to a control gate of the redundant memory cell corresponding to the selected memory cell, apply the first programming voltage for the first duration to a memory gate of the redundant memory cell, perform the verification operation to the redundant memory cell, and apply the second programming voltage for the second duration to the memory gate of the redundant memory cell in response to determining that the redundant memory cell fails to program according to a result of the verification operation.
According to yet another aspect of the present disclosure, there is provided a memory comprising a memory cell array, and peripheral circuitry coupled to the memory cell array, the peripheral circuitry comprising trimming circuitry comprising any of the memories described above configured to perform a trimming operation on the memory cell array in accordance with information stored in any of the memories described above.
According to yet another aspect of the present disclosure, there is provided a memory system comprising any of the memories described above and a controller coupled to the memories.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
FIG. 1 illustrates a block diagram of an exemplary system with memory in an embodiment of the present disclosure.
FIG. 2A illustrates a block diagram of a memory system.
FIG. 2B illustrates a block diagram of another memory system.
Fig. 3 is a schematic circuit diagram of a memory 300 including peripheral circuits provided by an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a peripheral circuit according to an embodiment of the disclosure.
Fig. 5 shows a schematic circuit diagram of an exemplary memory 500 including peripheral circuitry, according to an exemplary embodiment.
Fig. 6 is a schematic diagram of a peripheral circuit according to an embodiment of the disclosure.
Fig. 7 is a schematic circuit diagram of an OTP memory 700 including peripheral circuits provided by an embodiment of the disclosure.
Fig. 8 is a schematic diagram of an OTP peripheral circuit according to an embodiment of the disclosure.
FIG. 9 is a flowchart illustrating a method of memory operation, according to an example embodiment.
Fig. 10 is a schematic diagram showing the processing procedure of step S904 shown in fig. 9 in an embodiment.
Fig. 11 is a schematic diagram showing the processing procedure of step S908 shown in fig. 9 in an embodiment.
Fig. 12 is a schematic diagram showing the processing procedure of step S908 shown in fig. 9 in another embodiment.
Fig. 13A illustrates a programming voltage waveform of a stepped pulse width.
Fig. 13B illustrates a programming voltage waveform for stepping the pulse height.
FIG. 14 is a flowchart illustrating another method of memory operation, according to an example embodiment.
Fig. 15 is a schematic diagram of a program-verify operation flow of the memory shown in fig. 9 to 14.
Fig. 16 is a flow chart illustrating a program operation of a selected memory cell for a first period of time according to fig. 9 to 14.
Fig. 17 is a flowchart showing a program inhibit operation for unselected memory cells for a first period of time according to fig. 9 to 14.
Fig. 18 is a voltage waveform diagram of the selected memory cell and the unselected memory cell according to fig. 16 and 17 at a first programming stage.
Fig. 19 is a flow chart showing a verification operation of a selected memory cell for a second period of time after the first period of time according to fig. 9 to 14.
FIG. 20 is a voltage waveform diagram during a verify phase according to the selected and unselected memory cells shown in FIG. 19.
Fig. 21 is a flowchart illustrating a program operation of a selected memory cell for a third period of time after the second period of time according to fig. 9 to 14.
FIG. 22 is a voltage waveform diagram of selected and unselected memory cells shown in FIG. 21, in a second programming stage.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many different forms and should not be construed as limited to the examples set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, apparatus, steps, etc. In other instances, well-known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise. The symbol "/" generally indicates that the context-dependent object is an "or" relationship.
In the present disclosure, unless specifically stated and limited otherwise, terms such as "connected" and the like are to be construed broadly, and may be electrically connected or may communicate with each other, either directly or indirectly, through an intermediary. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
FIG. 1 illustrates a block diagram of an exemplary system with memory in an embodiment of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a pointing device, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, or any other suitable electronic device having memory therein.
As shown in FIG. 1, system 100 may include a host 108 and a memory system 102, memory system 102 having one or more memories 104 and a memory controller 106. Host 108 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an application processor) of an electronic device. Host 108 may be configured to send data to memory 104 or receive data from memory 104.
The memory 104 may be non-volatile memory, or the like. The non-volatile memory may be a NAND flash memory (e.g., a three-dimensional (3D) NAND flash memory). The volatile memory may be dynamic random access memory (Dynamic Random Access Memory, DRAM).
In some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 may manage data stored in memory 104 and communicate with host 108.
In some embodiments, memory controller 106 is configured to send a command to memory 104 to cause memory 104 to read information stored in the OTP memory when executed.
In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium for use in an electronic device such as a personal computer, digital camera, mobile phone, or the like.
In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or embedded multimedia card (eMMC), which may be used as a data storage and enterprise storage array for mobile devices such as smartphones, tablet computers, laptop computers, and the like. The memory controller 106 may be configured to send commands to the memory 104 to cause the memory 104 to perform operations, such as read, erase, and program operations.
The memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the memory 104 including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like.
In some embodiments, the memory controller 106 is further configured to process Error Correction Codes (ECCs) with respect to data read from the memory 104 or written to the memory 104. The memory controller 106 may also perform any other suitable function, such as formatting the memory 104. Memory controller 106 may communicate with external devices (e.g., host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with external devices through at least one of various interface protocols, such as a USB protocol, MMC protocol, peripheral Component Interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small Computer Small Interface (SCSI) protocol, enhanced Small Disk Interface (ESDI) protocol, integrated Drive Electronics (IDE) protocol, firewire protocol, and the like.
The memory controller 106 and the one or more memories 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronics.
FIG. 2A illustrates a block diagram of a memory system. As shown in fig. 2A, the memory controller 106 and the single memory 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, personal computer memory card international association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, mmcmmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in fig. 1).
FIG. 2B illustrates a block diagram of another memory system. As shown in fig. 2B, the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206, and the plurality of memories 104 may include, for example, a plurality of NAND flash memories 1042 and 1 DRAM 1044.SSD 206 can also include SSD connector 208 that couples SSD 206 with a host (e.g., host 108 in FIG. 1). In some embodiments, the storage capacity and/or operating speed of SSD 206 is greater than the storage capacity and/or operating speed of memory card 202.
Fig. 3 is a schematic circuit diagram of a memory 300 including peripheral circuits provided by an embodiment of the present disclosure. Memory 300 may be an example of memory 104 in fig. 1 and 2A, or memory 1042 in fig. 2B. The memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array in which memory cells 306 are provided in the form of an array of memory strings 308 of NAND flash memory, each memory string 308 extending vertically above a substrate (not shown).
In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, e.g., voltage or charge, depending on the number of electrons trapped within the area of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.
In some embodiments, each memory cell 306 may store 1 bit data or 2 bits data or more, i.e., may be a Single level cell (Single-LEVEL CELL, SLC) type, a Multi-level cell (Multi-LEVEL CELL, MLC) type, a three level cell (Triple-LEVEL CELL, TLC) type, a four level cell (Quad-LEVEL CELL, QLC) type, or a higher level type.
As shown in fig. 3, each memory string 308 may include a Source select gate (Source SELECT GATE, SSG) 310 at its Source end and a drain select gate (DRAIN SELECT GATE, DSG) 312 at its drain end. SSG 310 and DSG 312 may be configured to activate a selected memory string 308 during read and program operations.
In some embodiments, the sources of the memory strings 308 in the same block (block) 304 are coupled through the same Source Line (SL) 314 (e.g., common SL). For example, all memory strings 308 in the same block 304 have an array common source (Array Common Source, ACS). As shown in fig. 3, the memory strings 308 may be organized into a plurality of blocks 304, each of the plurality of blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic unit of data for an erase operation, i.e., all memory cells 306 on the same block 304 are erased at the same time.
In some embodiments, the transistors of the DSG 312 of each memory string 308 are coupled to a respective Bit Line (BL) 316, from which data can be read or written via an output bus (not shown). Each memory string 308 may be configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having DSG 312) or a deselect voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and/or by applying a select voltage (e.g., above the threshold voltage of the transistor having SSG 310) or a deselect voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.
As shown in FIG. 3, the memory cells 306 of the memory string 308 may be coupled by a Word Line (WL) 318, the word line 318 selecting which row of memory cells 306 is affected by the read and program operations. Peripheral circuitry 302 may be coupled to memory cell array 301 by bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed signal circuitry for facilitating operation of memory cell array 301 by applying voltage signals and/or current signals to and sensing voltage signals and/or current signals from each targeted memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology.
Fig. 4 is a schematic diagram of a peripheral circuit according to an embodiment of the disclosure. As shown in fig. 4, the peripheral circuit 302 may include a page buffer circuit/sense amplifier 404, a column decoder/BL driver 406, a row decoder/WL driver 408, a voltage generator 410, a control logic unit 412, a register 414, an input/output (I/O) circuit 416, and a data bus 418. It should be appreciated that in some examples, additional peripheral circuitry not shown in fig. 4 may also be included.
In some embodiments, the page buffer circuit/sense amplifier 404 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic unit 412. For example, the page buffer circuit/sense amplifier 404 may store a page of program data (write data) to be programmed into the memory cell array 301. As another example, the page buffer circuit/sense amplifier 404 may also sense a low power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to an identifiable logic level in a read operation. The column decoder/BL driver 406 may be configured to be controlled by the control logic unit 412 and select one or more memory strings 308 by applying the bit line voltage generated from the voltage generator 410.
The row decoder/WL driver 408 may be configured to be controlled by the control logic unit 412 and select/deselect the block 304 of the memory cell array 301 and select/deselect the word line 318 of the block 304. The row decoder/WL driver 408 may also be configured to drive the word lines 318 using the word line voltages generated from the voltage generator 410. In some embodiments, row decoder/WL driver 408 may also select/deselect and drive SSG lines 314 and DSG lines 313. The voltage generator 410 may be configured to be controlled by the control logic unit 412 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, a source line voltage, etc., to be supplied to the memory cell array 301.
Control logic 412 may be coupled to each portion of peripheral circuitry 302 and configured to control the operation of each portion. The registers 414 may be coupled to the control logic unit 412 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The input/output circuit 416 may be coupled to the control logic unit 412 and act as a control buffer to buffer and relay control commands received from a host (not shown in fig. 4) to the control logic unit 412, and to buffer and relay status information received from the control logic unit 412 to the host. The input/output circuitry 416 may also be coupled to the column decoder/bit line drivers 406 via a data bus 418 and acts as a data I/O interface and data buffer to buffer data and relay it to and from the memory cell array 301.
In some embodiments, the peripheral circuitry 302 may include trimming circuitry (not shown in fig. 3) that may be coupled to a particular module in the peripheral circuitry 302 for implementing the trimming function under the control of the control logic unit 412. For example, a trimming circuit may be provided in the voltage generator 410 to trim the generated voltage. For another example, a trimming circuit may be provided in the input/output circuit 416 to trim the input/output signal. Peripheral circuit 302 may also include an OTP memory 420, which OTP memory 420 may be coupled to control logic unit 412 for storing information that does not need to be altered. The control logic unit 412 may perform corresponding trimming operations according to the information stored in the OTP memory 420 to implement the trimming function.
Fig. 5 shows a schematic circuit diagram of an exemplary memory 500 including peripheral circuitry, according to an exemplary embodiment. Memory 500 may be an example of memory 104 in fig. 1 and 2A, or memory 1044 in fig. 2B. The memory 500 may include a memory cell array 501 and peripheral circuitry 502 coupled to the memory cell array 501. The memory cell array 501 may include one or more memory banks 504. Each bank 504 includes a word line 514 (e.g., WL1, WL2, wl3.) WLm.), a bit line 516 (e.g., BL 1.) BL2 bl3...bln) and a cross-point device 508 formed between word line 514 and bit line 516. In some implementations, each cross-point device 508 may include paired transistor and capacitor DRAM cells. To operate each bank 504 of the memory cell array 501, a word line voltage (V WL) may be applied to each word line 514, and a bit line voltage (V BL) may be applied to each bit line 516.
Fig. 6 is a schematic diagram of a peripheral circuit according to an embodiment of the disclosure. As shown in fig. 6, peripheral circuitry 502 may include a row decoder/Word Line (WL) driver 602, a page buffer/sense amplifier 604, a column decoder/Bit Line (BL) driver 606, registers 608, control logic 610, and input/output (I/O) circuitry 612, among others. It should be appreciated that in some embodiments additional peripheral circuitry not shown in fig. 6 may also be included.
The row decoder/Wordline (WL) driver 602 may be configured to be controlled by the control logic unit 610 and the wordlines 514 of the selected bank 504 of the memory cell array 501. The row decoder/word line driver 602 may also be configured to drive the selected word line 514.
The page buffer/sense amplifier 604 may be configured to read data from the memory cell array 501 and program (write) data to the memory cell array 501 according to a control signal from the control logic unit 610. In some embodiments, the page buffer/sense amplifier 604 may store a page of program data (write data) to be programmed to the memory cell array 601. In other embodiments, the page buffer/sense amplifier 604 may perform a program verify operation to ensure that data has been properly programmed into the cross-point device 508 coupled to the selected word line 514. In still other embodiments, the page buffer/sense amplifier 604 may also sense a low power signal from the bit line 516 (which represents the data bit stored in the cross-point device 508) and amplify the small voltage swing to an identifiable logic level in a read operation.
The column decoder/Bit Line (BL) driver 606 may be configured to be controlled by the control logic unit 610 and select one or more cross-point devices 508. Input/output (I/O) circuitry 612 may be coupled to page buffer/sense amplifier 604 and/or column decoder/bit line driver 606 and configured to direct (route) data input from a bus (not shown in fig. 6) to a desired memory cell region (e.g., one or more banks 504 in fig. 6) of memory cell array 501 and to direct (route) data output from the desired memory cell region to the bus.
In some embodiments, the peripheral circuitry 502 may include trimming circuitry (not shown in fig. 5) that may be coupled to a particular module in the peripheral circuitry 502 for implementing the trimming function under the control of the control logic unit 610. For example, trimming circuitry may be coupled to the row decoder/word line driver 602 for trimming control operations on the word lines. For another example, a trimming circuit may be provided in the input/output circuit 610 to trim the input/output signals. Peripheral circuitry 502 may also include an OTP memory 614 coupled to control logic unit 610 for storing information that does not require modification. The control logic unit 610 may perform a corresponding trimming operation according to the information stored in the OTP memory 614 to implement the trimming function.
Fig. 7 is a schematic circuit diagram of an OTP memory 700 including peripheral circuits provided by an embodiment of the disclosure. OTP memory 700 may be an example of OTP memory 420 in fig. 4, OTP memory 614 in fig. 6. OTP memory 700 may include an OTP memory cell array 701 and an OTP peripheral circuit 702 coupled to OTP memory cell array 701. The memory cells 704 in the OTP memory cell array 701 may include a control transistor 7042 and a memory transistor 7044 connected. The gate of the control transistor 7042 is a control gate, and the gate of the storage transistor 7044 is a storage gate. The control gate and the storage gate are respectively connected to word lines (e.g., WL1, wl2.
In some embodiments, OTP peripheral 702 is configured to perform the memory operation methods provided by embodiments of the present disclosure. It is appreciated that the OTP peripheral circuitry 702 may be configured to perform the memory operation methods provided by embodiments of the present disclosure in accordance with received instructions of the memory controller 106.
In some embodiments, the memory cell 704 may further include a first terminal (e.g., may be the drain of the control transistor 7042) connected to the control gate and a second terminal (e.g., may be the source of the memory transistor 7044) connected to the memory gate, both of which are located between the first and second terminals. A first terminal of the memory cell 704 is connected to a bit line (e.g., BL1, BL2. The second terminal of the memory cell 704 is floating. In the case where the first terminal of the memory cell 704 is the drain of the control transistor 7042 and the second terminal of the memory cell 704 is the source of the memory transistor 7044 (this is taken as an example in the embodiment of the disclosure, but not limited thereto), the source of the control transistor 7042 is connected to the drain of the memory transistor 7044.
In some embodiments, there may be a plurality of memory cells each connected to a bit Line and a word Line, each of which may be connected to a Data Line (DL) (not shown in fig. 7), and a ground voltage may be applied to the corresponding DL when performing programming, verifying, and the like on the memory cells.
In some embodiments, the memory gate may be an anti-fuse gate that may be programmed by applying a high voltage across the word line to which the anti-fuse gate is connected to break down the memory transistor of the selected memory cell.
Fig. 8 is a schematic diagram of an OTP peripheral circuit according to an embodiment of the disclosure. As shown in fig. 4, the OTP peripheral circuit 702 may include a page buffer circuit/sense amplifier 804, a column decoder/BL driver 806, a row decoder/WL driver 808, a voltage generator 810, and a control circuit 812. It should be appreciated that in some examples, additional peripheral circuitry not shown in fig. 8 may also be included.
In some embodiments, the page buffer circuit/sense amplifier 804 may be configured to read data from the OTP memory cell array 701 and program (write) data to the OTP memory cell array 701 according to a control signal from the control circuit 812. For example, the page buffer circuit/sense amplifier 804 may store program data (write data) to be programmed into the OTP memory cell array 301. As another example, the page buffer circuit/sense amplifier 804 may also sense low power signals from the bit lines BL1 through BLi in the OTP memory cell array 701 representing the data bits stored in the memory cells 704 and amplify the small voltage swing to an identifiable logic level in a read operation. The column decoder/BL driver 806 may be configured to be controlled by the control circuit 812 and select the corresponding memory cell 704 by applying the bit line voltage generated from the voltage generator 810.
The row decoder/WL driver 808 may be configured to be controlled by the control circuit 812 and select/deselect the word lines (e.g., WL1, WL4, WL5 in the OTP memory cell array 701) of the control transistor 7042 of the memory cell 704. The row decoder/WL driver 808 may also be configured to drive the word lines (e.g., WL2, WL3, WLj in the OTP memory cell array 701) of the memory transistors 7044 of the memory cells 704 using the word line voltages generated from the voltage generator 810. The voltage generator 810 may be configured to be controlled by the control circuit 812 and generate a word line voltage (e.g., a read voltage, a program voltage, a verify voltage, a program inhibit voltage, etc.), a bit line voltage, etc., to be supplied to the OTP memory cell array 701.
In some embodiments, the OTP memory cell array 701 may include a pair of memory cells (not shown in fig. 7 and 8) having the same logical address, and the pair of memory cells includes one memory cell 704 and a redundant memory cell corresponding thereto. The control circuit 812 may control the row decoder/WL driver 808, the voltage generator 810, the column decoder/BL driver 806, etc. to perform the same operation on the memory cell 704 and its corresponding redundant memory cell based on the same logical address that the memory cell 704 and its corresponding redundant memory cell have.
FIG. 9 is a flowchart illustrating a method of memory operation, according to an example embodiment. The method as shown in fig. 9 can be applied, for example, to an OTP memory including an OTP peripheral circuit as shown in fig. 8 for programming an OTP memory cell array.
Referring to fig. 9, a method 90 provided by an embodiment of the present disclosure may include the following steps S902 to S908.
In step S902, a first voltage is applied to a control gate of a selected memory cell in the memory cell array.
In some embodiments, the first voltage may be a turn-on voltage of the control gate of the selected memory cell, for example, 2.5V, 3.0V, 3.5V, and so on. The OTP peripheral circuit may be configured to generate a first voltage by the voltage generator, the first voltage being applied by the control circuit to the first word line to which the control gate of the selected memory cell is connected by the control circuit to turn on the control transistor of the selected memory cell, thereby turning on the connection of the drain of the memory transistor of the selected memory cell to the first bit line.
In step S904, a first programming voltage is applied to the memory gate of the selected memory cell for a first duration.
In some embodiments, applying the first programming voltage for the first duration may be applying one programming pulse, the width of the pulse being the first duration, and the height of the pulse being the first programming voltage. The first programming voltage may be a breakdown voltage of a memory gate of the selected memory cell, for example, 6V, 6.5V, 7.0V, and so on. The first duration of time actually employed, the first programming voltage, may be set according to the current programming times, and implementation in some exemplary embodiments may refer to fig. 10.
In some embodiments, the OTP peripheral circuit may be configured to generate a first programming voltage by the voltage generator, control the word line driver to apply the first programming voltage for a first duration to a second word line to which the memory gate of the selected memory cell is connected by the control circuit, and apply a ground voltage to the first bit line by the bit line driver to create a high voltage difference between the gate and drain of the memory transistor of the selected memory cell to breakdown the memory transistor.
In step S906, a verification operation is performed on the selected memory cell.
In some embodiments, a first voltage may be continuously applied to a first word line connected to a control gate of a selected memory cell, and a ground voltage may be continuously applied to a first bit line connected to a first terminal of the selected memory cell, and a verification voltage may be applied to a second word line connected to a memory gate of the selected memory cell, to perform a verification operation on the selected memory cell. The magnitude of the verification voltage can be selected according to the actual situation of the storage gate.
In step S908, a second programming voltage is applied to the memory gate of the selected memory cell for a second period of time in response to the result of the verify operation being failed, wherein the second period of time is greater than the first period of time and/or the second programming voltage is greater than the first programming voltage.
In some embodiments, if the result of the verify operation is failed, the next program pulse may be applied to the memory gate of the selected memory cell with the control transistor turned on by applying the first voltage to the control gate of the selected memory cell, and the probability of program success may be increased by increasing the width and/or height of the pulse.
In some embodiments, if the result of the verify operation is a pass, the next memory cell can be selected for programming, thereby avoiding applying an excessive number of high voltages to the memory cell with its gate connected to the first word line.
According to the memory operation method provided by the embodiment of the disclosure, the first voltage is applied to the control gate of the selected memory cell in the memory cell array, the first programming voltage with a first duration is applied to the memory gate of the selected memory cell, then the verification operation is performed on the selected memory cell, and the second programming voltage with a second duration is applied to the memory gate of the selected memory cell if the result of the verification operation is failed, wherein the second duration is longer than the first duration, and/or the second programming voltage is longer than the first programming voltage, the programming pulse width/height is increased in a targeted manner through the verification step after programming, and the programming can be stopped under the condition that the verification is passed, so that the programming efficiency of the OTP memory cell can be improved under the premise of ensuring successful programming, the high voltage is reduced, the pressure on the OTP memory cell is lightened, and the power leakage of the OTP memory is reduced.
Fig. 10 is a schematic diagram showing the processing procedure of step S904 shown in fig. 9 in an embodiment. As shown in fig. 10, in the embodiment of the present disclosure, the above step S904 may further include the following steps S1002 to S1004.
In step S1002, in response to determining that the current programming number of the selected memory cell is 0, the first programming voltage is obtained as a preset programming voltage, which is a programming voltage for obtaining a memory gate of a preset proportion that can be successfully programmed through the test.
In some embodiments, the program pulse may not be applied only once to program the memory cell. A counting module may be provided for recording the current programming times of the memory cells. And under the condition that the current programming times recorded by the counting module corresponding to the selected storage unit is 0, namely the current programming is the first programming of the selected storage unit, the preset programming voltage of the storage grid which can be successfully programmed by the preset proportion and is obtained in the test can be used as the first programming voltage. For example, if the program voltage of the memory gate which can be successfully programmed 80% obtained in the test is 6V, the program voltage of the memory gate which can be successfully programmed 85% is 6.5V, the program voltage of the memory gate which can be successfully programmed 90% is 7.0V, and 6V of the memory gate which can be successfully programmed 80% can be selected as the first program voltage to reduce the voltage applied to the unselected memory cells connected to the second word line as much as possible.
In step S1004, a first programming voltage is applied to the memory gate of the selected memory cell for a first duration.
In some embodiments, the first duration may also be the shortest pulse width obtained in the test that the application of the corresponding preset programming voltage may successfully program a preset proportion of the memory gates, thereby also shortening the time for applying the high voltage to the unselected memory cells connected to the second word line.
According to the method provided by the embodiment of the disclosure, when the selected memory cells are programmed for the first time, the preset programming voltage of the memory gates which can be used for successfully programming the preset proportion and is obtained in the test can be used as the first programming voltage, and the shortest pulse width of the memory gates which can be used for successfully programming the preset proportion and are applied with the corresponding preset programming voltage can be used, so that the voltage and the time applied to unselected memory cells connected to the same word line are reduced as much as possible, and the device aging caused by the fact that the unselected memory cells need to be programmed for multiple times due to the fact that some selected memory cells are hard to break down is avoided to a certain extent.
Fig. 11 is a schematic diagram showing the processing procedure of step S908 shown in fig. 9 in an embodiment. As shown in fig. 11, in the embodiment of the present disclosure, the above step S908 may further include the following steps S1102 to S1106.
In step S1102, the current programming times of the selected memory cells are obtained.
In step S1104, in response to the result of the verification operation being failed, it is determined whether the current programming number of the selected memory cell is less than the preset programming number threshold.
In step S1106, a second programming voltage is applied to the memory gate of the selected memory cell for a second duration in response to determining that the current programming number of the selected memory cell is less than the preset programming number threshold.
In some embodiments, a preset programming number threshold may be set for the total number of programming of one memory cell. If the current programming times recorded by the counting module corresponding to the selected storage unit are not more than the preset programming times threshold value, the next programming operation can be continued to the selected storage unit so as to increase the probability of successful programming to the selected storage unit.
In other embodiments, if the result of the verify operation after one time programming of the selected memory cell is failed, and it is determined that the current programming number of the selected memory cell is not less than (e.g., equal to) the preset programming number threshold, programming of the selected memory cell may be stopped, and the memory cell programming failure may be recorded, so as to avoid applying too much high voltage to the memory cells connected on the same word line.
According to the method provided by the embodiment of the disclosure, the preset programming frequency threshold value is set for the total programming frequency of one memory cell, and when the result of the verification operation after one-time programming of the selected memory cell is failed, programming is continued only when the current programming frequency is determined not to exceed the preset programming frequency threshold value, so that the programming success rate is improved, and meanwhile, the application of excessive high voltage to the OTP memory is avoided.
Fig. 12 is a schematic diagram showing the processing procedure of step S908 shown in fig. 9 in another embodiment. As shown in fig. 12, in the embodiment of the present disclosure, the above step S908 may further include the following steps S1202 to S1204.
In step S1202, in response to the result of the verification operation being failed, the first time length is increased by a first predetermined step length to obtain a second step length, and/or the first program voltage is increased by a second predetermined step length to obtain a second program voltage.
In step S1204, a second programming voltage is applied to the memory gate of the selected memory cell for a second duration.
In some embodiments, a step program operation that increases the pulse width and/or height may be performed on a selected memory cell if the result of a verify operation after one time programming of the selected memory cell is failed. Fig. 13A and 13B illustrate two exemplary programming voltage waveforms according to fig. 12.
Fig. 13A illustrates a programming voltage waveform of a stepped pulse width. As shown in fig. 13A, the left to right pulse represents a programming pulse applied to the word line connected to the memory gate of the selected memory cell from the first programming to Pmax (corresponding to a preset programming number threshold) times, wherein the height of the pulse applied each time is the same, the first programming pulse width is W, and the pulse width is increased step (corresponding to a first preset step size) each time from the first programming to Pmax times.
Fig. 13B illustrates a programming voltage waveform for stepping the pulse height. As shown in fig. 13B, the left to right pulse represents a program pulse applied to the word line connected to the memory gate of the selected memory cell from the first programming to Pmax programming, wherein the width of each applied pulse is the same, the first programming pulse height is V, and the pulse height is increased by step' (corresponding to the second predetermined step) from the first programming to Pmax programming.
It should be appreciated that the number of times each memory cell is programmed is determined by the verification result after each programming, and may be any of 1 to Pmax times. Moreover, the waveforms in fig. 13A and 13B are only illustrative, and both pulse width and pulse height may be stepped in practical applications.
According to the method provided by the embodiment of the disclosure, by a step programming mode of step pulse width and/or height, the probability of success of the next programming can be improved under the condition that the previous programming is unsuccessful, so that the programming efficiency of the OTP memory cell is improved.
FIG. 14 is a flowchart illustrating another method of memory operation, according to an example embodiment. The method shown in fig. 14 can be applied, for example, to an OTP memory including an OTP peripheral circuit shown in fig. 8 for programming a selected memory cell and its corresponding redundant memory cell in an OTP memory cell array.
Referring to fig. 14, the method 140 provided by the embodiment of the present disclosure may include the following steps S1402 to S1408.
In step S1402, a first voltage is applied to control gates of selected memory cells and their corresponding redundant memory cells in the memory cell array.
In step S1404, a first programming voltage is applied for a first duration to the memory gates of the selected memory cell and its corresponding redundant memory cell.
In step S1406, a verification operation is performed on the selected memory cell and its corresponding redundant memory cell.
In some embodiments, the selected memory cell has the same logical address as its corresponding redundant memory cell, and thus the voltages applied in the programming operation and the verifying operation performed on the selected memory cell and its corresponding redundant memory cell are the same. In steps S1402 to S1406, the time for operating the selected memory cell and the time for operating the corresponding redundant memory cell may be different, and taking step S1402 as an example, for example, applying the first voltage to the control gate of the selected memory cell, applying the first voltage to the control gate of the corresponding redundant memory cell, and so on may be sequentially performed.
In step S1408, in response to the selected memory cell and/or its corresponding redundant memory cell verification operation failing, a second programming voltage is applied to the memory gate of the selected memory cell and its corresponding redundant memory cell for a second period of time, wherein the second period of time is greater than the first period of time and/or the second programming voltage is greater than the first programming voltage.
In some embodiments, the second programming voltage may be applied to the memory gate of the selected memory cell and its corresponding redundant memory cell for a second duration in the event that neither the selected memory cell nor the corresponding redundant memory cell pass the verification operation, i.e., if one of the selected memory cell and the redundant memory cell is successfully programmed, the programming may be stopped, which may reduce the number of times a high voltage is applied to a memory cell connected to the same word line in the event that at least one of the selected memory cell and the corresponding redundant memory cell is successfully programmed.
In other embodiments, the second programming voltage may be applied to the storage gates of the selected memory cell and the corresponding redundant memory cell for a second duration in the event that one of the verification operations of the selected memory cell and the corresponding redundant memory cell fails, so as to ensure that the selected memory cell and the corresponding redundant memory cell are successfully programmed, thereby implementing the redundant memory function of the OTP memory.
Fig. 15 is a schematic diagram of a program-verify operation flow of the memory shown in fig. 9 to 14. The flow shown in fig. 15 may include the following steps S1502 to S1522.
In step S1502, the flow starts.
In step S1504, a first address is acquired, and a memory cell and a corresponding redundant memory cell are selected. The first address may be a first address of a plurality of addresses to be programmed, each address may point to a pair of memory cells.
In step S1506, the programming times X are initialized for the selected memory cells and the corresponding redundant memory cells, and the values of the programming pulse parameters W, V are obtained.
In step S1508, a program operation and a verify operation are performed on the selected memory cell and its corresponding redundant memory cell. Embodiments may refer to step S902, step S904, and step S1406.
In step S1510, it is determined whether the verification result is passed. The embodiment may refer to step S1408.
In step S1512, if the verification result is pass (e.g. logic "1"), it is determined whether the current programming address is the last address of the plurality of addresses to be programmed.
Step S1514, if the current programming address is not the last address of the plurality of addresses to be programmed, the next programming address (second address) is obtained, and step S1506 is returned.
Step S1516, if the current programming address is the last address of the plurality of addresses to be programmed, the programming is successful, and the process ends.
In step S1518, if the verification result in step S1510 is failed (e.g., is logic "0"), it is determined whether the current programming number X is Pmax.
In step S1520, if the current programming number X is not Pmax, the current programming number x=x+1 is updated, the programming pulse parameters w=w+1 and/or v=v+1 are updated, and the process returns to step S1508. The embodiment may refer to step S908, fig. 12, fig. 13A and fig. 13B.
In step S1522, if the current programming number X is Pmax, the programming fails, and the process ends.
According to the program-verification process provided by the embodiment of the disclosure, the process can be executed in the form of a state machine when the OTP memory is programmed, so that the programming efficiency of the OTP memory cell can be improved, the programming time of the OTP memory cell can be shortened, the high voltage applied to the OTP memory cell can be reduced, the high current passing through the OTP memory can be reduced, and the power leakage of the OTP memory can be reduced on the premise of not increasing additional cost and ensuring successful programming.
In some embodiments, the control gate of the selected memory cell is connected to a first word line, the gate of the memory gate of the selected memory cell is connected to a second word line, and the first terminal of the selected memory cell is connected to a first bit line. The control gates of the unselected memory cells are connected to the third word line, the gates of the memory gates of the unselected memory cells are connected to the fourth word line, and the first ends of the unselected memory cells are connected to the second bit line. Fig. 16 to 22 show embodiments of the program operation and the verify operation in fig. 9 to 14 and voltage waveforms taking this as an example.
Fig. 16 is a flow chart illustrating a program operation of a selected memory cell for a first period of time according to fig. 9 to 14. Referring to fig. 16, the method 16 provided by the embodiments of the present disclosure may include the following steps S1602 to S1606.
In step S1602, a first voltage is applied to a first word line for a first period of time.
In step S1604, a first programming voltage is applied to the second word line for a first duration of time during a first period of time.
In step S1606, a ground voltage is applied to the first bit line for a first period of time.
Fig. 17 is a flowchart showing a program inhibit operation for unselected memory cells for a first period of time according to fig. 9 to 14. Referring to fig. 17, the method 17 provided by the embodiment of the present disclosure may include the following steps S1702 to S1706.
In step S1702, a second voltage is applied to a third word line for a first period of time, the second voltage being less than the first voltage.
In some embodiments, the second voltage may be a ground voltage (0V) or 0.5V, or the like, i.e., without turning on the control transistors of unselected memory cells.
In step S1704, a program inhibit voltage is applied to the fourth word line for the first period.
In some embodiments, the program inhibit voltage may be substantially less than the first program voltage, e.g., may be 1V, 1.05V, 1.1V, etc., to avoid a high voltage difference between the gates and drains of the memory transistors of the unselected memory cells.
In step S1706, a third voltage is applied to the second bit line during the first period, the third voltage being greater than the ground voltage.
According to the method provided by the embodiment of the disclosure, in a first time period for programming the selected memory cell, a second voltage smaller than a conducting voltage is applied to a third word line connected to a control gate of the unselected memory cell, a program inhibit voltage smaller than a first programming voltage is applied to a fourth word line connected to a memory gate of the unselected memory cell, and a third voltage larger than a ground voltage is applied to a second bit line connected to a first end of the unselected memory cell, so that a high voltage difference between a gate and a drain of a memory transistor of the unselected memory cell can be effectively avoided, and program inhibition of the unselected memory cell is realized.
Fig. 18 is a voltage waveform diagram of the selected memory cell and the unselected memory cell according to fig. 16 and 17 at a first programming stage. As shown in fig. 18, in the first period Tpgm1, the first voltage V1 is applied to the first word line (selected CG WL) to which the control gate of the selected memory cell is connected, the first program voltage Vpgm1 is applied to the second word line (selected MG WL) to which the memory gate of the selected memory cell is connected, and the ground voltage is applied to the first bit line (selected BL) to which the first terminal of the selected memory cell is connected, so that the program operation to the selected memory cell is realized. In the same manner as in the first period Tpgm1, the ground voltage (second voltage) is applied to the third word line (unselected CG WL) connected to the control gate of the unselected memory cell, the program inhibit voltage Vpass is applied to the fourth word line (unselected MG WL) connected to the memory gate of the unselected memory cell, and the third voltage V3 is applied to the second bit line (unselected BL) connected to the first terminal of the unselected memory cell, so that the program inhibit operation for the unselected memory cell is realized.
Fig. 19 is a flow chart showing a verification operation of a selected memory cell for a second period of time after the first period of time according to fig. 9 to 14. Referring to fig. 19, the method 19 provided by the embodiment of the present disclosure may include the following steps S1902 to S1906.
In step S1902, the first voltage continues to be applied on the first word line for a second period of time.
In step S1904, a verify voltage is applied to the second word line for a second period of time.
In step S1906, a ground voltage is applied to the first bit line for a second period of time.
FIG. 20 is a voltage waveform diagram during a verify phase according to the selected and unselected memory cells shown in FIG. 19. As shown in fig. 19, in the second period Tverf, the first voltage V1 is continuously applied to the first word line (selected CG WL) to which the control gate of the selected memory cell is connected, the verification voltage Vread is applied to the second word line (selected MG WL) to which the memory gate of the selected memory cell is connected, and the ground voltage is applied to the first bit line (selected BL) to which the first terminal of the selected memory cell is connected, so that the verification operation for the selected memory cell is realized. In the same manner as in the second period Tverf, the ground voltage (second voltage) is continuously applied to the third word line (unselected CG WL) connected to the control gate of the unselected memory cell, the program inhibit voltage Vpass is continuously applied to the fourth word line (unselected MG WL) connected to the memory gate of the unselected memory cell, and the third voltage V3 is continuously applied to the second bit line (unselected BL) connected to the first terminal of the unselected memory cell, so that the program (and verify) inhibit operation of the unselected memory cell is realized.
Fig. 21 is a flowchart illustrating a program operation of a selected memory cell for a third period of time after the second period of time according to fig. 9 to 14. Referring to fig. 21, the method 21 provided by the embodiment of the present disclosure may include the following steps S2102 to S2106.
In step S2102, the first voltage continues to be applied to the first word line for a third period of time.
In step S2104, a second programming voltage is applied to the second word line for a second period of time for a third period of time.
In step S2106, a ground voltage is applied to the first bit line for a third period of time.
FIG. 22 is a voltage waveform diagram of selected and unselected memory cells shown in FIG. 21, in a second programming stage. As shown in fig. 22, in the second program phase, i.e., in the third period Tpgm2, the first voltage V1 is continuously applied to the first word line (selected CG WL) to which the control gate of the selected memory cell is connected, the second program voltage Vpgm2 is continuously applied to the second word line (selected MG WL) to which the memory gate of the selected memory cell is connected, and the ground voltage is continuously applied to the first bit line (selected BL) to which the first terminal of the selected memory cell is connected, thereby realizing the program operation to the selected memory cell. In the same way as in the third period Tpgm2, the ground voltage (second voltage) is continuously applied to the third word line (unselected CG WL) connected to the control gate of the unselected memory cell, the program inhibit voltage Vpass is continuously applied to the fourth word line (unselected MG WL) connected to the memory gate of the unselected memory cell, and the third voltage V3 is continuously applied to the second bit line (unselected BL) connected to the first end of the unselected memory cell, so that the program inhibit operation for the unselected memory cell is realized.
Exemplary embodiments of the present disclosure are specifically illustrated and described above. It is to be understood that the disclosure is not to be limited to the details of construction, arrangement or method of implementation described herein, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
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