CN119923013A

CN119923013A - Chip packaging method and chip packaging structure

Info

Publication number: CN119923013A
Application number: CN202510053999.4A
Authority: CN
Inventors: 周悦; 施秋楠; 谢国梁; 李俊杰; 王蔚
Original assignee: China Wafer Level CSP Co Ltd
Current assignee: China Wafer Level CSP Co Ltd
Priority date: 2025-01-14
Filing date: 2025-01-14
Publication date: 2025-05-02

Abstract

The present invention discloses a chip packaging method and a chip packaging structure, the chip packaging method comprises: providing a frame, the frame comprises a frame and an elastic conductive member extending from the frame to one side; providing a chip package; arranging the chip package on the frame, and electrically connecting the chip to the elastic conductive member; placing the frame provided with a plurality of chip packages in a packaging mold; regulating the pressure applied by the packaging mold to the chip package, so that the cover plates of all chip packages abut against the packaging mold; injecting plastic packaging material into the packaging mold to form a plastic packaging body; demoulding and removing the frame of the frame to release the elastic conductive member; forming a welding protrusion on the elastic conductive member; cutting to form a plurality of chip packaging structures. The chip packaging method and the chip packaging structure of the present invention can solve the problem of plastic packaging material overflow in an open plastic packaging process, maintain the function of the original chip, and improve the chip packaging yield.

Description

Chip packaging method and chip packaging structure

Technical Field

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a chip packaging method and a chip packaging structure.

Background

The packaging structure of the optical image sensing chip is usually a cavity structure, the structure is fragile, and the vehicle-mounted chip is required to be sealed and protected by a plastic packaging technology so as to improve the reliability.

In the prior art, in order to protect the photosensitive area of the optical image sensor chip from being polluted and blocked, an open type plastic packaging technology is generally used. In the open type plastic packaging technology, a layer of film is covered on the upper surface of a cover plate, an upper die of a packaging die is in direct contact with the film and is tightly pressed above the cover plate, plastic packaging materials enter a die cavity from an injection molding opening at the side edge of the packaging die, solidification is completed at high temperature and high pressure, and finally, the surface film is uncovered to realize open type plastic packaging.

However, in the open plastic packaging process, since the upper die is in direct contact with the cover plate on the chip, and there is a height tolerance between the chips, the chips with lower heights may overflow due to the clearance between the film and the cover plate of the chip, and the chips with higher heights may be delaminated due to the high pressure.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a chip packaging method and a chip packaging structure, which can solve the problem of overflow of plastic packaging materials in an open type plastic packaging process, maintain the functions of an original chip and improve the chip packaging yield.

In order to achieve the above object, a specific embodiment of the present invention provides the following technical solution:

A method of chip packaging, comprising:

Providing a frame, wherein the frame comprises a frame and an elastic conductive piece extending from the frame to one side, and the elastic conductive piece is configured to deform under the action of force;

providing a chip package, wherein the chip package comprises a chip and a cover plate arranged to cover the chip;

Disposing the chip package on the frame and electrically connecting the chip with the elastic conductive member;

placing a frame provided with a plurality of chip packages in a packaging mold;

Regulating and controlling the pressure applied to the chip packaging parts by the packaging mould, and deforming the corresponding elastic conductive parts to change the heights of the chip packaging parts to which the elastic conductive parts belong relative to the frame, so that the cover plates of all the chip packaging parts are abutted with the packaging mould;

injecting a plastic packaging material into the packaging mould to form a plastic packaging body, wherein the plastic packaging body at least covers the joint of the frame and the chip packaging piece;

Demolding and forming welding protrusions on the elastic conductive piece;

And cutting and removing the frame of the frame to release the elastic conductive piece and form a plurality of chip packaging structures.

In one or more embodiments of the present invention, the elastic conductive member has a first end connected to the frame and a second end far from the frame, and a predetermined height is provided between the second end and the frame, and the predetermined height is higher than a height tolerance of the plurality of chip packages.

In one or more embodiments of the invention, the chip is electrically connected to the second end of the elastic conductive element, and/or,

A solder bump is formed on a first end of the elastic conductive element.

In one or more embodiments of the present invention, the pressure of the packaging mold applied to the chip package is regulated, so that the elastic conductive element corresponding to the chip package with a relatively high height is extruded and deformed to reduce the preset height, and is propped against the packaging mold together with the chip package with a relatively low height.

In one or more embodiments of the present invention, the encapsulation mold includes an upper mold and a lower mold that are mated with each other;

regulating and controlling the pressure applied to the chip packaging part by the upper die of the packaging die, and deforming the corresponding elastic conductive part to change the height of the chip packaging part to which the elastic conductive part belongs relative to the frame, so that the cover plates of all the chip packaging parts are abutted against the inner surface of the upper die of the packaging die.

In one or more embodiments of the present invention, the inner surface of the upper mold is provided with a release film.

In one or more embodiments of the present invention, after the frame is cut off, the elastic conductive members are not connected to each other.

In one or more embodiments of the present invention, there is provided a chip package including:

Providing a wafer, wherein the wafer comprises a plurality of chips, each chip is provided with a first surface and a second surface which are oppositely arranged, and a functional area and a welding pad are formed on the first surface;

providing a cover plate, and arranging the cover plate on the first surface to cover the functional area;

forming a bump on the second surface to electrically connect the pad;

Dicing the wafer to form a chip package.

A chip package structure, comprising:

the chip packaging piece comprises a chip and a cover plate which is arranged to cover the chip;

the elastic conductive piece is arranged on one side of the chip, which is away from the cover plate, and is electrically connected with the chip, and the elastic conductive piece is arranged to deform under the action of force;

The plastic package body is arranged on the peripheral surface of the chip package piece and at least coats the joint of the elastic conductive piece and the chip.

In one or more embodiments of the present invention, the elastic conductive member has a first end and a second end disposed opposite to each other, the second end being electrically connected to the chip, and the first end being provided with a solder bump, and the solder bump being exposed outside the plastic package.

Compared with the prior art, the chip packaging method and the chip packaging structure of the invention utilize the variability of the elastic conductive piece through the arrangement of the elastic conductive piece, improve the uniformity of the height of the pressed chip in the open type plastic packaging process, improve the layering and glue overflow problems of the chip with the cavity structure in the open type plastic packaging process, and improve the packaging yield.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.

FIG. 1 is a flow chart of a method for packaging a chip according to an embodiment of the invention;

FIGS. 2 a-2 j are block diagrams illustrating steps of a method for packaging a chip according to an embodiment of the invention;

fig. 3 is a cross-sectional view of a chip package structure according to an embodiment of the invention.

Detailed Description

In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

As to the background art, there is a height tolerance between chips, in the open-type plastic packaging process of chips, a higher chip can set up the upper mold of the film and the packaging mold, so that the lower chip cover plate surface cannot be completely protected when the film is covered, the upper mold cannot compress each chip cover plate surface, a gap exists between the cover plate top surface of a part of chips and the packaging mold, plastic packaging materials overflow into the gap and pollute the chips when in injection molding, the packaging yield and the chip functions are affected, and even layering problems are caused.

Based on the above, the invention provides a chip packaging method and a chip packaging structure, through the arrangement of the elastic conductive piece, deformation can be controlled manually in the open type plastic packaging process to reduce or eliminate the height tolerance among different chips, thereby solving the problem of overflow of plastic packaging materials in the open type plastic packaging process, maintaining the functions of the original chips and improving the chip packaging yield.

As shown in fig. 1, the chip packaging method in an embodiment of the invention specifically includes the following steps:

S1, providing a frame, wherein the frame comprises a frame and an elastic conductive piece extending from the frame to one side, and the elastic conductive piece is arranged to deform under the action of force.

In a preferred embodiment, the elastic conductive element may be formed by stamping the frame. The frame comprises a square frame and a plurality of elastic conductive pieces. The middle part of square frame is formed with a plurality of windows, and a plurality of elasticity electrically conductive piece arrange in proper order in the window of square frame. The elastic conductive piece is provided with a first end connected with the frame and a second end far away from the frame. The second end is configured as a free end of the elastic conductive element. The second end and the frame are provided with a preset height, and the preset height is higher than the height tolerance of the chip packages. By applying pressure to the second end in the thickness direction of the frame, the relative height between the second end and the rim can be changed.

S2, providing a chip package, wherein the chip package comprises a chip and a cover plate arranged to cover the chip.

Wherein, provide the chip package, include the following step:

a wafer is provided, the wafer comprises a plurality of chips, each chip is provided with a first surface and a second surface which are oppositely arranged, and a functional area and a welding pad are formed on the first surface.

A cover plate is provided and disposed on the first surface to cover the functional area. The cover plate and the first surface of the chip can be bonded through a glue bonding layer. The glue bonding layer is formed on the periphery of the functional area and forms a sealed cavity surrounding the functional area together with the cover plate.

Bumps for electrically connecting the pads are formed on the second surface. Illustratively, the bond pads may be exposed by opening holes in the second surface of the chip by TSV (through silicon via) technology. And forming a conductive layer electrically connected with the welding pad in the through hole, wherein the conductive layer extends to the second surface of the chip. The bump is formed on the conductive layer of the second surface.

Dicing the wafer to form the chip package.

And S3, arranging the chip packaging piece on the frame, and enabling the chip to be electrically connected with the elastic conductive piece.

In a preferred embodiment, the chip package is flip-chip mounted on the frame, with the bumps on the chip in the chip package being in one-to-one correspondence with and electrically connected to the elastic conductive members.

S4, placing the frame provided with the plurality of chip packages in a packaging mold.

In this step, elimination of multiple chip package height tolerances may be performed. The pressure applied to the chip packaging part by the packaging mould is regulated, so that the elastic conductive part corresponding to the chip packaging part with higher relative height is extruded to deform so as to reduce the preset height of the elastic conductive part, further the height of the chip packaging part with higher relative height relative to the frame is changed, the elastic conductive part and the chip packaging part with lower relative height are propped against the packaging mould together, and the cover plates of all the chip packaging parts are guaranteed to be propped against the packaging mould.

It is understood that the package mold includes an upper mold and a lower mold that are mated with each other. The inner surface of the upper die is provided with a release film, and the release film can be contacted with a cover plate of the chip packaging part in the subsequent plastic packaging process so as to protect the chip packaging part. The height tolerance of the chip package is eliminated by regulating the pressure applied to the chip package by the upper die of the package die.

And S5, injecting a plastic packaging material into the packaging mould to form a plastic packaging body, wherein the plastic packaging body at least covers the joint of the frame and the chip packaging piece.

In order to further improve the structural strength of the chip package, the plastic package body covers the connection part of the elastic conductive piece and the chip package, the peripheral surface of the chip package and the elastic conductive piece, and only the top surface of the chip package and the first end of the elastic conductive piece are exposed.

And S6, demolding and forming welding protrusions on the elastic conductive piece.

In order to facilitate subsequent electrical connection to the circuit substrate, solder bumps may be formed on the exposed first ends of the resilient conductive members after demolding.

S7, cutting and removing the frame of the frame to release the elastic conductive piece, and forming a plurality of chip packaging structures.

Illustratively, dicing is performed in units of dicing for a single chip package structure. When cutting, the frame of the frame is cut off together, and only the elastic conductive piece on the frame is reserved. After the frame of the frame is removed, the first ends of the elastic conductive pieces can be completely released, and the first ends of the adjacent elastic conductive pieces are not communicated, so that mutual electric isolation is realized.

Fig. 2a to fig. 2j are schematic structural views illustrating specific steps of the chip packaging method according to the present invention, and the chip packaging method according to the present invention is described in detail below with reference to fig. 2a to fig. 2j, so as to further understand the technical scheme of the present invention.

Referring to fig. 2a, a wafer 10 is provided, the wafer 10 including a plurality of chips 11 and scribe lines 12 formed between adjacent chips 11. The chip 11 has a first surface and a second surface disposed opposite to each other, and the first surface has a functional region 111 and a bonding pad 112 coupled to the functional region formed thereon.

It will be appreciated that the dicing streets 12 between adjacent chips 11 are used for dicing after wafer level packaging is completed. The chip 11 may be an optical image sensor chip or the like. The functional region 111 is an optical sensing region, and may be formed by arranging a plurality of photodiodes, for example, which may convert an optical signal irradiated to the functional region 111 into an electrical signal. The pads 112 serve as input and output terminals for connection of the devices in the functional region 111 to external circuits.

Referring to fig. 2b, a cover plate 20 is provided. The cover plate 20 is preferably a transparent substrate such as glass or the like. The cover plate 20 is bonded to the first surface of the chip 11 by bonding glue, and the cover plate 20 is disposed to cover the functional area 111. For example, a glue bonding layer a may be formed on the surface of the cover plate 20 and/or the first surface of the chip 11 by a spraying, spin coating or pasting process, the glue bonding layer a being located at the periphery of the functional region 111. And then the cover plate 20 is pressed against the first surface of the chip 11, and is combined by bonding glue.

The bonding glue can realize the bonding effect and also can play the roles of insulation and sealing. The bonding glue can be a high molecular bonding material, such as polymer materials of silica gel, epoxy resin, benzocyclobutene and the like.

Referring to fig. 2c, the chip 11 is etched from the second surface of the chip 11 to form a through hole (not shown), which exposes the pad 112 on the first surface side of the chip 11.

An insulating layer 113 is formed on the second surface of the chip 11 and on the sidewall of the through hole, the insulating layer 113 exposes the bonding pad 112 at the bottom of the through hole, the insulating layer 113 may provide electrical insulation for the second surface of the chip 11, and the material of the insulating layer 113 may be silicon oxide, silicon nitride, silicon oxynitride or insulating resin.

The conductive layer 114 connected to the bonding pad 112 is formed on the surface of the insulating layer 113, the conductive layer 114 may be used as a rewiring layer to guide the bonding pad 112 to the second surface of the chip 11, and then connected to an external circuit, and the conductive layer 114 is formed after deposition of a metal film and etching of the metal film.

A solder mask 115 having an opening (not shown) is formed on the surface of the conductive layer 114 and the surface of the insulating layer 113, and the opening exposes a portion of the surface of the conductive layer 114, and the material of the solder mask 115 is an insulating dielectric material such as silicon oxide or silicon nitride, so as to protect the conductive layer 114.

Bumps 116 are formed on the surface of the solder resist layer 115. The protrusions 116 fill the openings and protrude through the openings. The bump 116 is a metal bump and has conductivity.

Referring to fig. 2d, the wafer 10 and the cover plate 20 are diced along dicing streets 12 to form chip packages 100.

Referring to fig. 2e and 2f, fig. 2e is a schematic top view of the frame 30, and fig. 2f is a schematic cross-sectional view of the frame 30. A frame 30 is provided. The frame 30 includes a frame 31 and an elastic conductive member 32 extending from the frame 31 to one side, and the elastic conductive member 32 is configured to be deformed by a force.

In the present embodiment, the elastic conductive member 32 may be formed by punching the frame 30. The frame 30 includes a square frame 31 and a plurality of elastic conductive members 32. A plurality of windows 301 are formed in the middle of the square frame 31, and a plurality of elastic conductive pieces 32 are sequentially arranged in the windows 301 of the square frame 31. Each elastic conductive element 32 has a first end 321 connected to the frame 31 and a second end 322 remote from the frame 31. The second end 322 has a predetermined height H1 with respect to the frame 31, and the predetermined height H1 is higher than a height tolerance of the plurality of chip packages 100. By applying pressure to the second end 322 in the thickness direction of the frame 30, the relative height between the second end 322 and the bezel 31 can be changed.

Referring to fig. 2g, a plurality of chip packages 100 are flip-chip mounted on the frame 30. Wherein the bumps 116 on the chip 11 in the chip package 100 are in one-to-one correspondence and electrically connected with the second ends 322 of the elastic conductive elements 32. In an initial state, a certain height tolerance H2 exists after the plurality of chip packages 100 are formed on the frame 30.

Referring to fig. 2h, the release film 220 is attached to the inner top surface of the upper mold 210 of the package mold 200, the frame 30 provided with the plurality of chip packages 100 is placed in the package mold 200, and an open type plastic packaging process is performed.

In the open plastic packaging process, after the flat upper mold 210 presses the release film 220, the die package 100 can be pressed, and the elastic conductive element 32 of the frame 30 is deformed to change the preset height H1. The taller chip package 100 is pressed, and the corresponding elastic conductive member 32 is deformed and lowered by the preset height H1, so that the upper mold 210 presses the shorter chip package 100, and finally, the height uniformity is achieved.

The plastic package material is filled into the package mold 200 through the injection port, the plastic package material is a polymer composite material such as epoxy resin, polyimide, a dry mold and the like, and then the plastic package material is cured under high temperature and high pressure to form the plastic package body 50, and the plastic package body 50 provides physical support for the package structure and plays a role in sealing and protecting the chip package 100, the frame 30 and the elastic conductive piece 32. The molding compound 50 exposes the top surface of the chip package 100 and the first end 321 of the elastic conductive member 32.

Referring to fig. 2i, the demolded plastic sealed body 50 covers the sidewall of the cover plate 20 and is flush with the top surface of the cover plate 20, and the top surface of the cover plate 20 does not form the plastic sealed body 50.

Referring to fig. 2j, a solder bump 40 is formed on the exposed first end 321 of the elastic conductive element 32. The package structure and the frame 30 after the plastic package 50 is formed are cut along the dashed line positions in fig. 2e and fig. 2j, the frame 31 of the frame 30 is completely cut, and only the elastic conductive members 32 on the frame 31 are remained, so as to form a plurality of chip package structures. After the frame 31 of the frame 30 is removed, the first ends 321 of the elastic conductive elements 32 are completely released, and the first ends 321 of the adjacent elastic conductive elements 32 are not connected to each other, so as to realize mutual electrical isolation.

The invention also provides a chip packaging structure which is packaged by adopting the chip packaging method. The description of the chip packaging method described above in connection with fig. 2 a-2 j may be incorporated herein.

Referring to fig. 3, the chip package structure includes a chip package 100, an elastic conductive member 32, a solder bump 40, and a molding body 50.

The chip package 100 includes a chip 11 and a cover plate 20 disposed to cover the chip 11. The chip 11 has a first surface and a second surface disposed opposite to each other, the first surface having the functional region 111 and the pads 112 formed thereon, and the second surface having bumps 116 electrically connected to the pads 112 formed thereon. The bump 116 is a metal bump, and has conductivity.

The cover plate 20 is disposed on the first surface of the chip 11 through the adhesive bonding layer a to cover the functional region 111.

The elastic conductive element 32 is disposed on the second surface side of the chip 11 and is electrically connected to the chip 11.

Specifically, the elastic conductive element 32 has a first end 321 and a second end 322 disposed opposite to each other. The second end 322 and the first end 311 have a predetermined height H1 therebetween, and the predetermined height H1 is higher than a height tolerance of the plurality of chip packages 100. The second ends 322 of the elastic conductive elements 32 are in one-to-one correspondence and electrically connected with the bumps 116 of the chip 11. The first end 321 of the elastic conductive member 32 is provided with a solder bump 40.

The elastic conductive element 32 is arranged to deform under the force. Applying pressure to the elastic conductive element 32 in the thickness direction of the chip package 100 can change the relative height H1 between the second end 322 and the first end 321, thereby adjusting the relative height tolerance of the plurality of chip packages 100 during the open plastic packaging process.

The plastic package body 50 encapsulates the elastic conductive element 32, the connection between the elastic conductive element 32 and the chip package 100, and the peripheral surface of the chip package 100. The top surface of the cover 20 of the chip package 100 and the solder bumps 40 are exposed outside the plastic package 50.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.

Claims

1. A method of packaging a chip, comprising:

placing a frame provided with a plurality of chip packages in a packaging mold;

Demolding and forming welding protrusions on the elastic conductive piece;

2. The method of claim 1, wherein the elastic conductive member has a first end connected to the frame and a second end remote from the frame, and the second end and the frame have a predetermined height therebetween, and the predetermined height is higher than a height tolerance of the plurality of chip packages.

3. The method of packaging a chip as claimed in claim 2, wherein the chip is electrically connected to the second end of the elastic conductive member, and/or,

A solder bump is formed on a first end of the elastic conductive element.

4. The method of claim 2, wherein the pressure of the packaging mold applied to the chip package is controlled so that the elastic conductive element corresponding to the chip package with a relatively high height is deformed by extrusion to reduce the preset height and is propped against the packaging mold together with the chip package with a relatively low height.

5. The chip packaging method according to claim 1, wherein the packaging mold includes an upper mold and a lower mold that are mated with each other;

6. The method of claim 5, wherein the inner surface of the upper mold is provided with a release film.

7. The method of claim 1, wherein the elastic conductive members are not connected to each other after the frame is cut off.

8. The chip packaging method according to claim 1, wherein providing a chip package comprises:

forming a bump on the second surface to electrically connect the pad;

Dicing the wafer to form a chip package.

9. A chip package structure, comprising:

10. The chip package structure of claim 9, wherein the elastic conductive member has a first end and a second end disposed opposite to each other, the second end being electrically connected to the chip, the first end being provided with a solder bump, the solder bump being exposed outside the plastic package.