CN119937939B

CN119937939B - Data caching and sending method based on multistage FIFO

Info

Publication number: CN119937939B
Application number: CN202510439619.0A
Authority: CN
Inventors: 郑浩威; 严棚; 魏宇星
Original assignee: Institute of Optics and Electronics of CAS
Current assignee: Institute of Optics and Electronics of CAS
Priority date: 2025-04-09
Filing date: 2025-04-09
Publication date: 2025-08-01
Anticipated expiration: 2045-04-09
Also published as: CN119937939A

Abstract

The present invention discloses a method for data caching and sending based on multi-level FIFO, which belongs to the field of data caching technology, including: after writing data into a first-level FIFO, reducing the transmission speed of the data through a second-level FIFO, and the read control logic of the second-level FIFO then divides the data into four parts of similar quantity according to the read order with timing as part of the control condition. The first part is written into the first-level FIFO, and after receiving the data, the first-level FIFO reads the data into the fourth-level FIFO, and writes the second part of the data to the second-level FIFO, and the first-level FIFO writes the third part of the data until the first data is completely written into the fourth-level FIFO. When the fourth-level FIFO completely reads the first data, it writes the subsequent data in sequence. The present invention uses multi-level FIFO cache control to save space for deploying external storage chips and reduce the complexity of the control system.

Description

Data caching and sending method based on multistage FIFO

Technical Field

The invention belongs to the technical field of data caching, and particularly relates to a data caching and sending method based on multistage FIFO (first in first out).

Background

The field programmable gate array (Field Programmable GATE ARRAYS, FPGA) is a signal processing device which can be used in a programmable manner, has rich logic resources, and can be used for automatically changing configuration information according to design requirements to define functions. FIFO (First Input First Output) is one of the common units of chip design, and because of its functional characteristics of first-in first-out, it is widely used in the fields of data receiving, transmitting, processing, etc. FIFOs are used today as the most prominent standard memory modules in more and more FPGA design engineering.

With the increasing demand of engineering, the scale of engineering design is expanding, and more digital chips need to be integrated in the control board card. Particularly in space-based platforms, space-based devices often require the integration and routing of a plurality of boards in a limited space, which often limits the number of chips. In the existing data caching technology, especially in the extreme case that a fast clock domain spans a slow clock domain and a parallel data signal is converted into a serial data signal, a reliable solution is to integrate a DDR3 chip, cache data is realized by calling the DDR3 chip with large capacity, and finally proper control logic is designed to realize data transmission. However, there is typically more than one functional module that needs to be called for on DDR3 chips, and increasing the number of aerospace level DDR3 chips creates additional space occupation and routing pressure. Therefore, a technical route for data caching and sending under extreme conditions such as space limitation by fully utilizing the resources of the digital chip is needed, so that a new solution is provided for the design of the space-based equipment platform.

Disclosure of Invention

The invention provides a data caching and transmitting method based on a multi-stage FIFO (first in first out) aiming at the defect that the existing data caching and transmitting method is applied to a space-based platform. The method gives play to the characteristics of abundant logic resources, high speed and high performance of the FPGA, and fully utilizes the resources of the FPGA chip to replace the use of an additional memory chip, thereby realizing the effects of reducing space occupation and wiring pressure of the space-based platform.

The technical scheme adopted by the invention is as follows, a data caching and sending method based on multistage FIFO, comprising the following steps:

step one, a first-level FIFO acquires data.

And step two, reading data from the first-stage FIFO according to the empty state of the first-stage FIFO by the second-stage FIFO, and realizing the speed reduction output of the data.

The method comprises the steps of dividing data into four approximate parts by read control logic of a second-level FIFO, wherein first data are used for writing the first-level FIFO, second data are used for writing the second-level FIFO, the speed-down output of the data is realized in the process, after the first-level FIFO writes the first data, the first data are written into the second-level FIFO through judging the empty state of the first-level FIFO, the second-level FIFO writes the second data through the empty state of the second-level FIFO in the process, and the first-level FIFO writes the third data according to the empty state of the second-level FIFO while reading the first data until the third data are completely written into the first-level FIFO and the first data are completely written into the fourth-level FIFO.

And fifthly, after the far-end read control logic completely reads out the first data, the fourth-stage FIFO writes the second data through the empty state of the second-stage FIFO, and the second-stage FIFO writes the fourth data from the second-stage FIFO through the empty state after the data are read out.

And step six, after the far-end read control logic completely reads out the second data, the fourth-stage FIFO sequentially writes the third and fourth data through the empty state of the second-stage FIFO, and the far-end read control logic reads out the third and fourth data.

And caching and sending the data are completed.

Compared with the prior art, the invention has the advantages that:

in the design of the invention, the advantage of rich logic resources of the FPGA can be fully exerted in the limited space of the space-based platform, the use of a memory chip is reduced, the space occupation is reduced, and the wiring pressure is relieved.

The invention realizes the multi-level buffer storage and transmission of data through a plurality of FIFOs, has simple connection mode, can flexibly adjust the use quantity and connection mode of the FIFOs according to the actual conditions such as time sequence requirements or the data quantity, and widens the application scene.

The read-write control of the FIFO module replaces the control module of DDR3, and the complexity of control logic is reduced.

The invention designs the input/output interface as a standard FIFO read-write interface, and has simple operation.

In the multi-system integrated circuit environment, the invention uses the buffer control of the multi-stage FIFO, saves the space for deploying the plug-in memory chip, reduces the complexity of the control system, has concise data flow direction, is convenient for further expansion, and can be flexibly configured according to the requirements of data quantity and time sequence.

Drawings

FIG. 1 is a block diagram of a method for buffering and transmitting data based on a multi-stage FIFO according to the present invention;

Fig. 2 is a flow chart of a method for caching and transmitting data based on a multi-stage FIFO according to the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the specific embodiments. It should be understood that the following description is only for explaining the present invention, and not limiting the present invention, and the technical features of the embodiments may be combined as long as they do not conflict with each other.

According to an embodiment of the present invention, a method for buffering and transmitting data based on a multi-stage FIFO is provided, a block diagram of the method is shown in fig. 1, a flow chart is shown in fig. 2, in fig. 1 and 2, FIFO1 refers to a first-stage FIFO, FIFO2 refers to a second-stage FIFO, FIFO3.1 refers to a first-stage FIFO, FIFO3.2 refers to a second-stage FIFO, and FIFO4 refers to a fourth-stage FIFO. The first stage, second stage, third stage and fourth stage refer to that a multi-stage FIFO is arranged in a FIFO structure.

Step one, a primary FIFO, retrieves data, which in one example is 836000 bytes in total, and writes it through near-end write control logic.

And step two, the second-stage FIFO reads data from the first-stage FIFO according to the empty state of the first-stage FIFO and realizes the speed-down output of the data, wherein the empty state is shown as empty1 in FIG. 1, and the reading speed of the second-stage FIFO is reduced to 64% of the writing speed in the speed-down output.

And step three, the read control logic of the second-level FIFO divides the data into a plurality of approximate four parts, wherein the first data is used for being written into the first-level FIFO, the second data is used for being written into the second-level FIFO, the speed-down output of the data is realized in the process, the read speed of the third-level FIFO is reduced to 62.5% of the write speed in the speed-down output, and the part with the minimum data amount in the four parts is 70.3% of the most part. In an example, the first two data are all hundred thousand, the third data are 9 ten thousand, the fourth data are 128000, and in fact, the temporary storage of four data can be satisfied within the range of the data volume allowed in the setting of the FIFO, the situation that any FIFO overflows is not caused, and the specific data volume can be flexibly controlled.

And writing the first data into the first-stage FIFO by the write control logic of the fourth-stage FIFO by judging the empty state (shown as empty3.1 in figure 1) of the first-stage FIFO, writing the second data into the second-stage FIFO by the empty state (shown as empty2 in figure 1) of the second-stage FIFO in the process, writing the third data into the first-stage FIFO according to the empty state of the second-stage FIFO while reading the first data by the first-stage FIFO until the third data is completely written into the first-stage FIFO and the first data is completely written into the fourth-stage FIFO, and writing by judging the empty state of the first-stage FIFO means that the fourth-stage FIFO is enabled to take effect after the empty state of the first-stage FIFO is not empty, and receiving the data from the first-stage FIFO.

In the fourth step, the writing of the first data by the fourth-stage FIFO, the writing of the second data by the second-stage FIFO, and the reading of the first data from the first-stage FIFO are performed simultaneously, so that it is ensured that the full state of the first-stage FIFO does not occur when the first-stage FIFO writes the third data.

The first data is buffered in the four-stage FIFO and read out by the remote read control logic, and when the four-stage FIFO does not completely read out the first data, the second data is buffered in the second-stage FIFO, the third data is buffered in the first-stage FIFO, and the fourth data is buffered in the second-stage FIFO.

That is, when the second data is completely written into the fourth FIFO, the second third FIFO writes the fourth data from the second FIFO, and after the fourth FIFO reads one data completely, the next data is written into the third FIFO in sequence, and so on, thereby completing the buffering and sending of the data.

Wherein the remote read control logic takes full advantage of the blanking time to read data out of the four-stage FIFO in sequence. The far-end read logic performs a read operation based on the empty state of the four-stage FIFO.

The near end refers to control logic close to one-stage FIFO, and the far end refers to control logic close to four-stage FIFO.

As shown in fig. 2, in the present embodiment, data needs to be transferred from a fast clock domain to a slow clock domain, and converted from a parallel signal to a serial signal. First, the primary FIFO writes a 16-bit data signal (shown as data (16 bits) in fig. 2) at a clock frequency of 125MHz (shown as wr_clk (125 MHz)) and reads out a 32-bit data signal (shown as data (32 bits) in fig. 2) at a clock frequency of 125MHz (shown as rd_clk (125 MHz)) and the secondary FIFO realizes a partial cross-clock domain function as a transition, and the data is inputted at a clock frequency of 125MHz (shown as wr_clk (125 MHz) in fig. 2) and outputted at a clock frequency of 80MHz (shown as rd_clk (80 MHz)) and a 16-bit data signal (shown as data (16 bits) in fig. 2). The second-level FIFO sends 1-200000 bytes to the first-level FIFO (FIFO 3.1), as shown by 1-100000 and 200001-290000 in fig. 2, and 200001-400000 bytes to the second-level FIFO (3.2), as shown by 100001-200000 and 290001-418000 in fig. 2. The first three stage FIFO (FIFO 3.1) is input at a clock frequency of 80MHz (shown as wr_clk (80 MHz) in fig. 2), and the second three stage FIFO (FIFO 3.2) is similarly output at a clock frequency of 50MHz (shown as rd_clk (50 MHz) in fig. 2) with 16 bits of data signal (shown as data (16 bits) in fig. 2). Meanwhile, the four-stage FIFO writes 1-200000 bytes from FIFO3.1, based on the empty state of FIFO3.1 as a condition judgment. The four-stage FIFO (FIFO 4) inputs at a clock frequency of 50MHz (shown as wr_clk (50 MHz) in fig. 2), and outputs a 16-bit data signal (shown as rd_clk (50 MHz) in fig. 2) at a clock frequency of 50MHz (shown as data (16 bits) in fig. 2). All data output by the four-stage FIFO (FIFO 4) is processed by the remote read control logic. After the second FIFO sends the forty-thousand bytes into FIFO3.2, the 400001-580000 bytes continue to be sent to FIFO3.1, with the last 256000 bytes temporarily buffered in the second FIFO. When the four-stage FIFO has data written, the remote read control logic reads the data from the four-stage FIFO and performs parallel-serial conversion. After the current twenty-thousand bytes are completely read by the far-end control logic, the four-stage FIFO makes logic judgment through the empty state of the FIFO3.2, writes the 200001-400000 bytes, and continues to be read by the far-end control logic. And FIFO3.2 also uses its empty state to condition the last 256000 bytes read from the secondary FIFO. After each four-stage FIFO reads out one data completely, the subsequent data is received from the three-stage FIFO in sequence, and is output by remote read control and is subjected to parallel-serial conversion, and finally, a 1-bit data signal is output.

The above description is only an example of the present application and is not intended to limit the present application. It will be apparent to those skilled in the art that the present application is capable of numerous extensions and modifications, and that the described functions may be implemented using different embodiments within the scope of the present application depending on the actual application, all of which are within the scope of the present disclosure.

Claims

1. A method for buffering and transmitting data based on a multi-stage FIFO, the method comprising the steps of:

step one, a first-level FIFO obtains data;

step two, the second-level FIFO reads data from the first-level FIFO according to the empty state of the first-level FIFO, and realizes the speed-down output of the data;

Dividing data into four approximate parts by a read control logic of the second-level FIFO, wherein the first data is used for being written into the first-level FIFO, the second data is used for being written into the second-level FIFO, and the speed-down output of the data is realized in the process; the third data is less than the first data and the second data respectively, the fourth data is less than the third data, and the data contained in the part with the least data amount is 70.3% of the part with the most data;

Step four, after the first data is written into the first-stage FIFO, the writing control logic of the fourth-stage FIFO writes the first data from the first-stage FIFO by judging the empty state of the first-stage FIFO, during the process, the second-stage FIFO writes the second data through the empty state of the second-stage FIFO, the first third-stage FIFO reads out the first data and writes third data according to the empty state of the second-stage FIFO until the third data is completely written into the first third-stage FIFO and the first data is completely written into the fourth-stage FIFO;

Step five, after the far-end read control logic completely reads out the first data, the fourth-stage FIFO writes the second data through the empty state of the second-stage FIFO, and the second-stage FIFO writes the fourth data from the second-stage FIFO through the empty state after the data are read out;

Step six, after the far-end read control logic completely reads out the second data, the fourth-stage FIFO sequentially writes in a third part of data and a fourth part of data through the empty state of the second-stage FIFO, and the fourth part of data is read out by the far-end read control logic;

and caching and sending the data are completed.

2. The method of claim 1, wherein the first stage FIFO comprises writing data via the near-end write control logic.

3. The method of claim 2, wherein the near end is near one stage FIFO and the far end is near four stages FIFO.

4. The method of claim 1, wherein the step two includes a step two of reducing the rate of the second FIFO to 64% of the write rate.

5. The method of claim 1, wherein in the fourth step, the fourth stage FIFO writes the first portion of data using the first stage FIFO, the second stage FIFO writes the second portion of data, and the first portion of data is read from the first stage FIFO.

6. The method of claim 1, wherein after the fourth step, the first data is buffered in the fourth FIFO and read by the remote read control logic, the second data is buffered in the second FIFO, the third data is buffered in the first FIFO, and the fourth data is buffered in the second FIFO.

7. The method of claim 1, wherein the remote read control logic uses blanking times to read data from the four-stage FIFO in sequence.

8. The method of claim 1, wherein in the steps one to six, the data is transferred from the fast clock domain to the slow clock domain.

9. The method of claim 8, wherein the second FIFO is input at a clock frequency of 125MHz, the first FIFO and the second FIFO are input at a clock frequency of 80MHz, the fourth FIFO is input at a clock frequency of 50MHz, and the fourth FIFO is output at a clock frequency of 50 MHz.