CN119989998B - Asynchronous micro pipeline structure based on 'transmitting-relay-receiving' structure - Google Patents
Asynchronous micro pipeline structure based on 'transmitting-relay-receiving' structure Download PDFInfo
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Abstract
The invention discloses an asynchronous micro-pipeline structure based on a 'sending-relaying-receiving' structure, which comprises an asynchronous control component, wherein the asynchronous control component comprises one or more of a Sender (Sender), a Relay (Receiver), a Receiver (Receiver) or a Relay (PmtRelay) permission, the Sender comprises a trigger, an inverter and a delay module, the Relay comprises an exclusive OR gate, an AND gate, a D trigger, an inverter and a delay module, the implementation is realized on the basis of a Click asynchronous controller, the Receiver comprises a trigger, a pmt control mechanism is added in the Click controller by PmtRelay, the asynchronous control component is one of Fifo, pmtFifo, selector, splitter, waitMerge, mutexMerge, and the asynchronous micro-pipeline structure is built by one or more of the asynchronous control components. The asynchronous micro-flow structure of the invention provides fine granularity control, utilizes event flow to drive control, adopts a unified control chain template, is simpler and straighter in design, and is more concerned with delay and generation conditions of event signals, and the design process is more flexible and efficient.
Description
Technical Field
The invention belongs to the technical field of asynchronous control circuits, and particularly relates to an asynchronous micro-pipeline structure based on a transmission-relay-receiving structure.
Background
The asynchronous micro-pipeline structure is the core for constructing an asynchronous circuit, the traditional micro-pipeline is realized by adopting a coarse-granularity static data flow structure, a design method based on the static data flow structure adopts a coarse-granularity control structure, a designer only needs to master a small amount of event driving details, and the event driving circuit is designed completely from the angle of a control mode. The structure can better distinguish the control path from the data path, ensure the consistency of the data in the whole circuit and avoid data collision or error. However, the pipeline of the coarse-grained control structure needs to be refined for many times according to functions and layers, so that an event mechanism is difficult to describe from the aspect of control, a part of the structure needs to be customized manually, and the pipeline of the coarse-grained control structure uses a large number of C units as a basic structure, so that the difficulty of circuit verification is increased by using the C units in large-scale digital design, extra obstruction is introduced to the large-scale design, and in addition, when engineering practice is carried out by utilizing a coarse-grained static data flow structure, extra customized design tools are needed, and the design flow is not compatible with the existing mainstream design flow.
Based on static micro-pipeline, research has proposed a more fine-grained "chain-link" architecture model that combines various types of asynchronous controllers with the necessary delays, where the chain architecture is responsible for event transmission and delays within the controlled modules, and the link architecture is responsible for event exchange and functional module management. Unlike static data flow structures at the macro scale, the "chain-link" structure focuses on the dynamic driving mechanism of events, rather than abstract control, and better conforms to the working principle of event-driven design. The method can adjust the realization of the micro-pipeline structure from the microscopic aspect, and is suitable for the development of high-speed asynchronous circuits. The development of such a structure requires a great deal of knowledge of the asynchronous controller principles and details and involves modification and division of the asynchronous control circuit, which is a difficult task to develop a micro-pipeline on the basis of a "chain-link" structure.
Disclosure of Invention
In view of the foregoing problems with the background art, it is an object of the present invention to provide an asynchronous micro pipeline structure based on a "transmit-relay-receive" structure.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
The invention provides an asynchronous micro pipeline structure based on a 'send-Relay-receive' structure, comprising an asynchronous control component comprising one or more of a Sender (Sender), a Relay (Relay), a Receiver (Receiver) or a permitted Relay (PmtRelay), wherein:
The Sender (Sender) comprises a trigger, an inverter and a delay module, when receiving a driving pulse signal i_drive, the Sender turns over an output level signal, and an input pulse signal i_free is delayed by the delay module and then is output as o_free;
the repeater (Relay) consists of an exclusive-or gate, an AND gate, a D trigger, an inverter and a delay module, and is realized based on a Click asynchronous controller;
The Receiver (Receiver) includes a trigger that is activated when the lower pulse signal i_ freeNext is received;
the admission relay (PmtRelay) adds an admission (pmt) control mechanism in the Click controller, connects the output end of the Click controller with a pmt control signal, and controls the flip-flop output level to turn over after the trigger pulse signal reaches the trigger end of the trigger;
The asynchronous control assembly comprises one of Fifo, pmtFifo, selector, splitter, waitMerge, mutexMerge, an asynchronous micro-pipeline structure is built by one or more of the asynchronous control assemblies, and an asynchronous control chain formed by the asynchronous control assemblies is as follows:
(1) The asynchronous control chain consists of a Fifo, wherein the input control chain and the output control chain are used for generating a plurality of pulse signals in the transmission process after signals corresponding to events and data pass through the input control chain, and the signals corresponding to the events and the data are used for triggering the combination logic circuit and are output by the output control chain;
(2) PmtFifo an input control chain and an output control chain, wherein after signals corresponding to events and data pass through the input control chain, the transmission is controlled by an admission mechanism, a primary pulse signal is generated in the transmission process and used for triggering a combinational logic circuit, and the signals corresponding to the events and the data are output by the output control chain;
(3) The asynchronous control chain consists of an input control chain and two branch chains, wherein signals corresponding to events and data are input by the input control chain, and the signals corresponding to the events and the data of one branch chain are selected to be output after being transmitted by the branch chains;
(4) The asynchronous control chain consists of an input control chain and a plurality of branch output control chains, wherein signals corresponding to events and data are input by the input control chain, and signals corresponding to the events and the data are divided into a plurality of events and data and are respectively output by the plurality of branch output control chains;
(5) WAITMERGE, wherein a plurality of input control chains and an output control chain are adopted, signals corresponding to a plurality of events and data are respectively input by the plurality of input control chains, and are output by the output control chain after being combined;
(6) MutexMerge, wherein signals corresponding to a plurality of events and data are respectively input by the input control chains, signals corresponding to one path of effectively input events and data are identified, and the signals are output by the output control chains.
Further, the Fifo comprises Sender, relay, receiver, the PmtFifo comprises Sender, pmtRelay, receiver and an AND gate, the Selector comprises Sender, relay, receiver, an AND gate and a NOT gate, the Splitter comprises Contap, an AND gate, an OR gate and a NOR gate, the WAITMERGE comprises Contap, an AND gate and an OR gate, the MutexMerge comprises Contap, an AND gate, an OR gate and a multiplexer, and the Contap adopts a Selector which does not generate a free signal, and the Contap comprises a trigger and an inverter for converting a pulse signal into a level signal.
Further, in the Fifo, the Sender receives the driving pulse signal drive from the upper module and sends the driving pulse signal drive to the Relay, and generates multiple pulse signals fire sequentially through multiple relays to trigger the combinational logic circuit, when all the pulse signals fire are excited, the signals are sent to the Receiver to generate the lower driving pulse signal drive and are transmitted to the lower module, and meanwhile, the Fifo returns a free signal to the upper module to indicate that the operation of the upper module is completed, and can receive new driving pulse signals.
Further, in PmtFifo, the Sender receives the driving pulse signal drive from the upper module and sends it to PmtRelay, after waiting for the permission control mechanism to change state, pmtRelay generates a primary pulse signal fire for triggering the combinational logic circuit, when the pulse signal fire is excited, it sends it to the Receiver to generate the lower driving pulse signal drive, and sends it to the lower module, and at the same time PmtFifo returns a free signal to the upper module, indicating that the present module has completed operation, and can receive a new driving pulse signal.
Further, in the Selector, after receiving the driving pulse signal drive from the upper module, the Selector delays the driving pulse signal drive by the delay module and outputs the driving pulse signal drive to the Relay, the Relay generates a pulse fire, delays the pulse fire by the delay module and transmits the pulse fire to the two and gates, the two and gates are selectively conducted to generate the lower driving pulse signal drive, and the output data controls the trigger in the Receiver to acquire data, so that the whole branch selection process is triggered.
Further, in the Splitter, when the event and the data trigger the Splitter through the driving pulse signal drive, the Splitter copies and distributes the event and the data to a plurality of branches, the plurality of branches process the event and the data simultaneously, and after all the branches complete processing and return a reply signal, the Splitter sends a free signal to an upper module through a free signal to wait for receiving the next event.
Further, in WAITMERGE, after receiving the driving pulse signals drive and the corresponding data of the plurality of upper modules, WAITMERGE combines the multiple driving pulse signals into a single driving pulse signal to be transmitted to the lower module, and simultaneously splices multiple data into a single data stream to be transmitted to the lower module.
Further, mutexMerge, after receiving the driving pulse signals drive and the corresponding data of the plurality of upper modules, the driving pulse signals drive of the plurality of upper modules are used as effective input signals, and the event and the data corresponding to the effective input signals are transmitted to the lower module, meanwhile, the driving pulse signals drive of the plurality of upper modules respectively control Contap and Contap output signals as selection signals of the selector, one path of data output is selected through the selection signals, and MutexMerge sends a free signal to the upper module after all the inputs are processed, and waits for receiving new data.
Compared with the defects and shortcomings of the prior art, the invention has the following beneficial effects:
(1) The asynchronous micro-pipeline structure based on the 'transmitting-relaying-receiving' structure provides fine-granularity control, so that the mechanism for describing the event from the control layer is more visual, the event flow is utilized to drive the control, and a unified control chain template is adopted, so that the design is more straight-white and simpler;
(2) Compared with a large number of coarse-granularity static data stream structures using C units, the repeater is realized based on the Click asynchronous controller, the C units of the coarse-granularity control structure are replaced by the Click units, the trigger edges can be generated when the handshake signals are transmitted by the Click units, and the asynchronous control mode is more approximate to synchronous control, so that the verification of middle circuits of large-scale design is facilitated;
(3) The asynchronous control chain consisting of the asynchronous control components is built by using the basic logic units, and the synchronous design flow can be completely compatible in the design, so that the disadvantage of lack of special EDA in the asynchronous design is greatly relieved, the design flow is more standardized, and the dependence on customized design tools is reduced;
(4) Compared with a chain-link structure needing to master the principle and details of a large number of asynchronous controllers, the asynchronous micro-flow structure provided by the invention simplifies the design flow, a designer only needs to master a small number of event driving details, designs an event driving circuit completely from the angle of a control mode, reduces the learning difficulty of engineering personnel, can understand and apply the structures more quickly, and in addition, the asynchronous micro-flow structure provided by the invention focuses more on the delay and generation conditions of event signals, so that the design process is more flexible and efficient.
Drawings
FIG. 1 is a schematic diagram of a Sender according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a Relay according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a Receiver according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a PmtRelay according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of Fifo according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a PmtFifo according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a Selector according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a Splitter according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a WAITMERGE according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of MutexMerge according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific embodiments in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention provides a coarse-granularity asynchronous micro-pipeline structure based on a 'transmitting-relaying-receiving' structure, wherein the granularity of the structure is between a static data stream and a 'chain-linking' structure, and the delay and the generation conditions of event signals are concerned, so that the design process is more flexible and efficient. The architecture includes one or more of four infrastructures, namely a Sender (Sender), a Relay (Relay), a Receiver (Receiver) and a Relay (PmtRelay) through which a core event-driven mechanism is expressed, and a driving logic circuit of an event signal adopts Boolean logic expression.
The structure of the Sender is shown in figure 1, and comprises a trigger, an inverter and a delay module, which are responsible for starting the asynchronous control path to work and ensuring the reliable transmission of data. When receiving the driving pulse signal i_drive, the Sender turns over the output level signal, and the input pulse signal i_free is delayed by the delay module and then output as o_free. The specific process is that the output port outR is low level at the initial moment, and the D end of the trigger is high level. When the pulse signal i_free arrives, the data of the D terminal of the flip-flop is copied to the Q terminal, the output port outR is turned to the high level, and the D terminal is turned to the low level.
The Relay is structurally shown in fig. 2, and comprises an exclusive-or gate, an AND gate, a D trigger, an inverter and a delay module, and is realized based on a Click asynchronous controller. Interaction of the Click controller with the outside is accomplished by two inputs containing inR and the outA signals and three outputs containing inA, outR and pulse fire. The pulse fire is responsible for controlling the trigger to collect data, the Click controller strictly manages data flow through the pulse fire, and the other four signals are used for interaction with the adjacent Click controller. In the initial state, all input/output level signals are kept at a low level, inR and inA are exclusive-ored to inRA at a low level, the output a and outR are exclusive-ored to outRA at a high level, and inRA and outRA are exclusive-ored to keep at a low level, so that the pulse fire also keeps at a low level. When inR is flipped, the controller is enabled, inRA changes from low to high, and then the pulse fire also changes from low to high, and the flip-flop copies the data at the D terminal to the Q terminal, and the level signals of inA and outR will be pulled up after passing through a delay unit, and the next-stage Click request signal and the response signal of the previous-stage Click are generated. Subsequently, the pulse fire is pulled down from the high level, producing a complete pulse signal, and the data is smoothly transferred under this control. When the next Click feeds back the outA, the controller is ready to receive the next round of event triggers, which is also a handshake mechanism between the two-stage controllers, thereby ensuring event and data bound transmission.
The Receiver is shown in the structure shown in figure 3, and comprises a trigger, when the lower pulse signal i_ freeNext is received, the trigger is activated, the data at the D end of the trigger is copied to the Q end, namely inR is transmitted to the inA, so that the data synchronization is realized, and the consistency of the data in a pipeline is ensured. This structure is typically located at the end of the micro-pipeline and is responsible for resetting the entire asynchronous control path.
PmtRelay the architecture is shown in FIG. 4, and a allow (pmt) control mechanism is added to the Click controller to achieve finer data transmission control. The output end of the Click controller is connected with a pmt control signal, when pmt is low level 0, the pulse fire can not reach the trigger end of the trigger, and when pmt is high level 1, the pulse fire reaches the trigger end of the trigger to control the output level of the trigger to be turned over. Otherwise, the behavior of the two inputs inR and outA, and the two outputs inA and outR are consistent with Click.
A variety of complex asynchronous control components Fifo, pmtFifo, selector, splitter, waitMerge, mutexMerge are constructed with four basic structures. An asynchronous micro-pipeline structure is built up from one or more asynchronous control components that will form an asynchronous control chain to accomplish a variety of complex control tasks.
The asynchronous control chain consists of a Fifo, an input control chain and an output control chain, wherein after signals corresponding to events and data pass through the input control chain, multiple pulse signals are generated in the transmission process and used for triggering a combinational logic circuit, so that the flow of the data in a pipeline is controlled, the signals corresponding to the events and the data are output by the output control chain, and a delay module is added in the asynchronous control chain.
The structure of Fifo is shown in FIG. 5 and comprises a Sender and a plurality of Relay, receiver. The Sender receives the driving pulse signal i_drive from the upper module and sends the driving pulse signal i_drive to n Relay, and then sequentially reaches Relay 0 and Relay 1, and then signals o_fire_0 and o_fire_1 are sequentially generated and used for triggering a combinational logic circuit, after the o_fire_n-1 is generated, a lower driving pulse signal o_ driveNext is generated at the lower stage of a delay module, and then the pulse signal o_free is generated and transmitted to a lower pulse signal i_ freeNext through a delay module, so that the current module can receive a new driving pulse signal. rst is a reset signal of the module to return the module to an initial state. Fifo can be implemented to generate any number of pulses fire to accommodate different data flow control requirements, and these drive pulses are in strict chronological order. The Fifo design maps event transfer to a specific control layer of the circuit, so that the asynchronous circuit design based on the Fifo is logically clearer and is convenient to understand and maintain.
PmtFifo an input control chain and an output control chain, wherein signals corresponding to events and data are controlled to be transmitted by an admission mechanism after passing through the input control chain, a primary pulse signal is generated in the transmission process and used for triggering a combinational logic circuit, the signals corresponding to the events and the data are output by the output control chain, and a delay module is added in the asynchronous control chain.
PmtFifo are shown in FIG. 6, including Sender, pmtRelay, receiver. The Sender receives the driving pulse signal i_drive from the upper module and sends the driving pulse signal i_drive to PmtRelay, waits for the inversion of the input permission signal pmt, then generates an o_fire signal for triggering the combinational logic circuit, and after the o_fire is generated, generates a lower driving pulse signal o_ driveNext through a lower stage of a delay module, generates a pulse signal o_free through a delay module, transmits the lower pulse signal i_ freeNext, indicates that the current stage module has completed operation, and can receive a new driving pulse signal. rst is a reset signal of the module to return the module to an initial state. PmtFifo adds a admission control mechanism on the basis of Fifo to achieve finer signal reception, processing and delivery.
The asynchronous control chain consists of one input control chain and two branch chains, wherein the signals corresponding to the events and the data are input by the input control chain, the signals corresponding to the events and the data of one branch chain are selected to be output after being transmitted by the branch chains, and a delay module is added in the asynchronous control chain.
The structure of the Selector is shown in FIG. 7, and comprises Sender, relay, receiver, AND gates and NOT gates. After receiving the driving pulse signal i_drive from the upper module, the Sender delays by the delay module and outputs the delayed driving pulse signal i_drive to the Relay0, and the output data controls the trigger in the Receiver to collect data, so that the whole branch selection process is triggered. The Relay0 generates a signal o_fire_0, and the signal is delayed by a delay module and then is transmitted to two AND gates, the two AND gates respectively generate lower driving pulse signals o_ dirveNext0 and o_ dirveNext1, only one of the two AND gates is conducted according to a selection bit in input data i_data_x, namely, o_ dirveNext0 or o_ dirveNext1 generates a pulse, and the data o_data0_y or o_data1_y is output. After the o_fire_0 signal is generated, the pulse signal o_free is generated by the delay module, and the lower pulse signals i_ freeNext0 and i_ freeNext1 are transmitted to indicate that the current stage module has completed operation. rst is a reset signal of the module to return the module to an initial state. The branch signal acts as a critical control bit dynamically indicating which branch the data and signal should flow to. The Selector ensures that the output driving pulse signal and the output data of the correct branch are valid only when the branch signal is at a high level by a logical AND operation, and that the output driving pulse signal of the wrong branch is valid only when the branch signal is at a low level. The structure of the Selector allows a designer to flexibly determine the path of data transmission according to the input branch signal, and the data bound with the branch event is customized by a user, so that the Selector can adapt to various data processing requirements, and the flexibility and adaptability of the design are improved.
The asynchronous control chain consists of an input control chain and a plurality of branch output control chains, wherein signals corresponding to events and data are input by the input control chain, and signals corresponding to the events and the data are respectively output by the plurality of branch output control chains.
The Splitter is constructed as shown in FIG. 8, and includes Contap, AND gate, OR gate, NOR gate, contap a flip-flop and inverter for converting the pulse signal to a level signal using a Sender that does not generate a free signal, contap. Split receives the driving pulse signal i_drive and the data i_data_x, which are directly connected to the two output signals o_ driveNext and o_ driveNext1, while the input data i_data_x is split into two output data o_data0_y and o_data1_z. i_drive pulls the signal high through Contap, i_ freeNext0 and i_ freeNext1 pull the signal low through Contap to control the generation of the signal o_free, thereby delivering the lower pulse signals i_ freeNext0 and i_ freeNext1.rst is a reset signal of the module to return the module to an initial state. Split copies and distributes events and data to multiple branches, which process events and data simultaneously, allowing events to be processed in parallel in multiple branches, increasing the parallelism and throughput of the system. After all branches complete processing and return a reply signal, the Splitter sends a free signal to the upper module through a free signal, and waits for receiving the next event. The handshake mechanism ensures orderly flow of events in the Splitter, avoids data collision and processing errors, and particularly in a scene that a single event needs to be distributed to a plurality of processing units for parallel processing, not only can the efficiency of event processing be improved, but also the system is allowed to execute different operations on different branches, so that the flexibility and the expandability of the system are improved.
WAITMERGE, wherein a plurality of input control chains and an output control chain are adopted, signals corresponding to a plurality of events and data are respectively input by the plurality of input control chains, and are output by the output control chain after being combined, and a delay module is added in the asynchronous control chain.
WAITMERGE is shown in fig. 9, which includes Contap, and gate, or gate, contap using a Sender that does not generate a free signal, contap including a flip-flop and an inverter, converting the pulse signal to a level signal. After WAITMERGE receives the driving pulse signals and corresponding data of the upper modules, WAITMERGE combines the multiple driving pulse signals into a single driving pulse signal to be transmitted to the lower module, so that the spliced data can be safely processed. And simultaneously splicing the multiple paths of data into a single data stream to be transmitted to the lower-level module, wherein the spliced data stream contains the data provided by all the upper-level modules, and the data are combined together to form a complete data set so that the lower-level module can perform further processing or operation. The two input signals i_drive0 and i_drive1 control the two Contap to pull up their output signals, respectively, and the output signal o_ driveNext is generated only when both i_drive0 and i_drive1 arrive, o_ driveNext pulls down the signals through Contap to control the generation of the signal o_free, and the lower pulse signal i_ freeNext restores the two Contap output signals to an initial state. The input data i_data0_x and i_data1_x are spliced into new data as output of o_datay. rst is a reset signal of the module to return the module to an initial state. WAITMERGE plays roles of data aggregation and control synchronization in the asynchronous micro-pipeline, so that a lower-level module can efficiently process the combined data flow, and the data processing capacity and efficiency of the whole system are improved.
MutexMerge, wherein signals corresponding to a plurality of events and data are respectively input by the input control chains, signals corresponding to one path of effectively input events and data are identified, and the signals are output by the output control chains. This design ensures that even if multiple input ports exist, only one input carries events and data to the lower module during each processing, thereby avoiding data collision.
MutexMerge is shown in fig. 10, which includes Contap, and gate, or gate, multiplexer, contap using a Sender that does not generate a free signal, contap including a flip-flop and an inverter, to convert the pulse signal to a level signal. MutexMerge receives the driving pulse signals and corresponding data of the upper modules, and then the result of phase or of the driving pulse signals of the upper modules is used as an effective input signal, and the event and the data corresponding to the effective input signal are transmitted to the lower module. The result of the phase or of the two input signals i_drive0 and i_drive1 is taken as the output result of o_ driveNext, and meanwhile, the i_drive0 and i_drive1 respectively control the two Contap to enable the output signals to be taken as the selection signals of the selector, so that one path is selected as the output result of i_data0_z in the two input data i_data0_x and i_data1_y. After all inputs are processed, mutexMerge sends out o_free signal to the upper module, and the lower pulse signal i_ freeNext restores the two Contap output signals to initial state. rst is a reset signal of the module to return the module to an initial state. MutexMerge simplifies the management of multiple inputs by ensuring that only one path of data and events are output at a time, improves the stability and efficiency of the system, and is particularly suitable for the scene requiring ensuring the data sequence and exclusive access.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
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