CN110011533A - Voltage doubling circuit unit, multi-stage voltage doubling circuit, control method and storage medium thereof - Google Patents

Abstract

The present application discloses a voltage doubling circuit unit, a multi-level voltage doubling circuit, a control method thereof, and a storage medium. The voltage doubling circuit unit includes a first branch and a second branch, and the first branch has at least two first switches The second branch has at least two second switching elements; the sequence signal generator is used to generate multiple first sequence signals, multiple second sequence signals, third sequence signals, fourth sequence signals and fifth sequence signals signal; the first sequence signal is used to control the on-off of each first switching element; the second sequence signal is used to control the on-off of each second switching element; the first sequence signal and the second sequence signal are inverted; the third The sequence signal is used to align the timing of each of the first sequence signals; the fourth sequence signal is used to align the timing of each of the second sequence signals. The above solution allows each switch to operate at high frequency, and ensures high symmetry of switches on different branches in the single-stage voltage doubling unit.

Description

Voltage doubling circuit unit, multi-stage voltage doubling circuit, control method and storage medium thereof

technical field

The present invention generally relates to the technical field of voltage doubling circuits, and in particular relates to a voltage doubling circuit unit, a multi-stage voltage doubling circuit, a control method thereof, and a storage medium.

Background technique

The voltage doubler circuit is to realize the purpose of circuit boosting. Generally, the multi-stage voltage doubling is realized by "switches and capacitors", and the switches are, for example, but not limited to, triodes. Each stage of the voltage multiplier circuit includes 4 boost switches, and there is a switch between the two stages of the voltage multiplier circuit. The action of the switch can be controlled through an application processor (Application Processor; AP for short) and a general input/output (General Purpose Input Output; GPIO for short) interface. Generally, when N-level voltage multiplier is implemented, the number of GPIOs ranges from 2N-1 to 5N-1. Ideally, the switch of one branch of the voltage multiplier circuit of each stage occupies one GPIO, and the signal of the other road is generated by an inverter, which does not occupy GPIO resources.

In the multi-level voltage doubling circuit, the AP is responsible for the multi-level voltage doubling switch action as the core processing unit. The timing control of the GPIO is not its main task, and the program modification is time-consuming and laborious. The frequent actions of the GPIOs require adjusting the timing constraints/path delays of the existing programs, and even changing the software architecture.

SUMMARY OF THE INVENTION

In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a voltage doubling circuit unit, a multi-stage voltage doubling circuit, a control method and a storage medium thereof, which can perform discrete control of the switch, allow the switch to operate at a high frequency, and ensure that all levels of High symmetry of switching keys on different paths of the voltage doubler circuit unit.

In a first aspect, the present invention provides a voltage doubling circuit unit, comprising a first branch and a second branch, the first branch has at least two first switching elements, and the second branch has at least two second switching elements ;

a sequence signal generator for generating a plurality of first sequence signals, a plurality of second sequence signals, a third sequence signal, a fourth sequence signal and a fifth sequence signal, wherein the third sequence signal, the fourth sequence signal and the fifth sequence signal The sequence signals are all correction signals;

The first sequence signal is used for one-to-one on-off control of the first switching element;

The second sequence signal is used for one-to-one on-off control of the second switching element;

The first sequence signal is inverted with the second sequence signal;

The third sequence signal is used to correct the timing alignment of each first sequence signal;

The fourth sequence signal is used to correct the timing alignment of each second sequence signal;

The fifth sequence signal is used to correct the timing alignment of the first sequence signal and the second sequence signal.

Further, the sequence signal generator also includes a correction unit, and the correction unit is configured to:

Use the third sequence signal to perform logical AND, OR, and NOT operations on the first sequence signal, so that each pulse rising edge/falling edge of the third sequence signal is aligned with the corresponding pulse rising edge/falling edge of the first sequence signal;

Use the fourth sequence signal to perform logical AND, OR, and NOT operation on the second sequence signal, so that each pulse rising edge/falling edge of the fourth sequence signal is aligned with the corresponding pulse rising edge/falling edge of the second sequence signal;

Use the fifth sequence signal to perform logical AND, OR, and NOT operation on the first sequence signal and the second sequence signal, so that each pulse rising edge/falling edge of the fifth sequence signal corresponds to the first sequence signal and the second sequence signal Pulse rising/falling edge alignment.

Further, the first sequence signal and the second sequence signal use square wave pulse signals, and the third sequence signal, the fourth sequence signal and the fifth sequence signal use spike pulse signals.

Further, the pulse interval of the first sequence signal and the second sequence signal is one switching clock cycle, the pulse interval of the third sequence signal and the fourth sequence signal is n switching clock cycles, and the pulse interval of the fifth sequence signal is 2n. Switch clock period, where n is a natural number greater than 2.

In a second aspect, the present invention provides a method for controlling a voltage doubling circuit unit, which is used for on-off control of a switching element of the voltage doubling circuit unit. The voltage doubling circuit unit includes a first branch and a second branch, and the first branch is on There are at least two first switching elements, and the second branch has at least two second switching elements,

After obtaining the enable signal, the sequence signal generator generates a plurality of first sequence signals, a plurality of second sequence signals, a third sequence signal, a fourth sequence signal and a fifth sequence signal, wherein the third sequence signal and the fourth sequence signal The signal and the fifth sequence signal are both correction signals;

The first sequence signal is used for one-to-one on-off control of the first switching element;

The second sequence signal is used for one-to-one on-off control of the second switching element;

The first sequence signal is inverted with the second sequence signal;

The third sequence signal is used to correct the timing alignment of each first sequence signal;

The fourth sequence signal is used to correct the timing alignment of each second sequence signal;

The fifth sequence signal is used to correct the timing alignment of the first sequence signal and the second sequence signal.

Further, the third sequence signal is used to correct the timing alignment of each first sequence signal; the fourth sequence signal is used to correct the timing alignment of each second sequence signal; the fifth sequence signal is used to correct the first sequence signal The correction of timing alignment with the second sequence signal includes:

Use the third sequence signal to perform logical AND, OR, and NOT operations on the first sequence signal, so that each pulse rising edge/falling edge of the third sequence signal is aligned with the corresponding pulse rising edge/falling edge of the first sequence signal;

Use the fourth sequence signal to perform logical AND, OR, and NOT operation on the second sequence signal, so that each pulse rising edge/falling edge of the fourth sequence signal is aligned with the corresponding pulse rising edge/falling edge of the second sequence signal;

Use the fifth sequence signal to perform logical AND, OR, and NOT operation on the first sequence signal and the second sequence signal, so that each pulse rising edge/falling edge of the fifth sequence signal corresponds to the first sequence signal and the second sequence signal Pulse rising/falling edge alignment.

In a third aspect, the present invention provides a multi-stage voltage doubling circuit, comprising a plurality of the above-mentioned voltage doubling circuit units connected in sequence, an output end of the previous stage voltage doubling circuit unit and an input end of the subsequent stage voltage doubling circuit unit connect;

The output end of the voltage doubling circuit unit of the previous stage is also connected with a feedback unit for enabling and controlling the voltage doubling circuit unit of the latter stage.

Further, the feedback unit is a switching device or circuit that conducts unidirectionally from the previous stage to the subsequent stage.

Further, the switching frequency of the voltage doubling circuit unit of the previous stage is more than twice the switching frequency of the voltage doubling circuit unit of the latter stage.

In a fourth aspect, the present invention provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented.

In the above scheme, the switches on each branch are controlled separately by the first sequence signal and the second sequence signal, and each switch is independent of each other, allowing each switch to operate at a high frequency. In addition, the third sequence signal and the first sequence signals are time-aligned. The fourth sequence signal is time-aligned to each second sequence signal; the fifth sequence signal is time-aligned to the first sequence signal and the second sequence signal, which ensures high symmetry of switches on different branches in the single-stage voltage doubling unit.

Description of drawings

Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

1 is a schematic diagram of a voltage doubling circuit unit provided by an embodiment of the present invention;

2 is a timing diagram of a single-stage voltage multiplier circuit provided by an embodiment of the present invention;

3 is a schematic diagram of a multi-stage voltage multiplier circuit provided by an embodiment of the present invention;

FIG. 4 is a timing diagram of a two-stage voltage doubling circuit provided by an embodiment of the present invention.

Detailed ways

The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the related invention, but not to limit the invention. In addition, it should be noted that, for the convenience of description, only the parts related to the invention are shown in the drawings.

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

As shown in FIG. 1 , it shows a voltage doubling circuit, which is only an example of a voltage doubling circuit, not a limitation of the voltage doubling circuit. There are other connection forms for the voltage doubler circuit.

The voltage doubling circuit in this example includes a first capacitor C1, the first terminal of the first capacitor C1 is connected to the voltage input terminal VDD, the second terminal of the first capacitor C1 is grounded, and the first terminal of the second capacitor C2 passes through the switch SW1-1 is connected to the first end of the first capacitor C1, the second end of the second capacitor C2 is connected to the first end of the first capacitor C1 through the switch SW2-1, and the second end of the second capacitor C2 is grounded through the switch SW1-2, The first terminal of the second capacitor C2 is connected to the voltage output terminal VDDH1' through the switch SW2-2, and the connection point between the switch SW2-2 and the voltage output terminal VDDH1' is grounded through the capacitor C3.

The switch SW1-1, the second capacitor C2 and the switch SW1-2 serve as the first branch, and the switch SW2-1, the second capacitor C2 and the switch SW2-2 serve as the second branch. When the switches SW1-1 and SW1-2 are closed, and the switches SW2-1 and SW2-2 are opened, the current flows from point a to point b. At this time, the voltage at point c = VDD; then, switch SW1-1 and switch SW1 -2 is turned on, switches SW2-1 and SW2-2 are closed, and the current flows from point b to point a. At this time, the voltage of point b is VDD. Due to the bootstrap effect of the capacitor, the voltage of point c = V(C2) = 2VDD. Among them, C3 is used to maintain the voltage at point c.

The voltage doubling circuit unit provided by the embodiment of the present invention includes a first branch and a second branch, the first branch has at least two first switching elements, and the second branch has at least two second switching elements; the sequence signal a generator for generating a plurality of first sequence signals, a plurality of second sequence signals, a third sequence signal, a fourth sequence signal and a fifth sequence signal, wherein the third sequence signal, the fourth sequence signal and the fifth sequence signal Both are correction signals; see also Figure 2, the number of the first sequence signal is the same as that of the first switch element, the first sequence signal is used for one-to-one on-off control of the first switch element; the second sequence signal and the second switch The number of elements is the same, and the second sequence signal is used for one-to-one on-off control of the second switching element; the first sequence signal and the second sequence signal are inverted; the third sequence signal is used for timing the first sequence signals. alignment correction; the fourth sequence signal is used for timing alignment correction on each second sequence signal; the fifth sequence signal is used for timing alignment correction on the first sequence signal and the second sequence signal.

For example, but not limited to, the voltage doubling circuit unit in this embodiment may use the above-mentioned voltage doubling circuit, wherein the switch SW1-1, the second capacitor C2 and the switch SW1-2 are used as the first branch, and the switch SW2-1, the second The capacitor C2 and the switch SW2-2 serve as the second branch. The switch SW1-1 and the switch SW1-2 are the first switch elements, and the switch SW2-1 and the switch SW2-2 are the second switch elements, which can all use triodes, MOS transistors, and the like. The switches SW1-1 and SW1-2 are controlled to act synchronously by two first sequence signals of the same timing, that is, one of the first sequence signals controls the action of the switch SW1-1, and the other first sequence signal controls the action of the switch SW1-2. , the switch SW2-1 and the switch SW2-2 are controlled to act synchronously by two second sequence signals of the same timing, that is, one of the second sequence signals controls the action of the switch SW2-1, and the other second sequence signal controls the switch SW2-2. action. Among them, a high level means that the switch is closed, and a low level means that the switch is open. It can be understood that, in practical applications, whether the switch control signal is active at high level or active at low level can be determined according to the type of the switch tube used.

The first sequence signal and the second sequence signal are inverted signals, and the third sequence signal ensures the timing alignment of the first sequence signals, the fourth sequence signal ensures the timing alignment of the second sequence signals, and the fifth sequence signal ensures that the first sequence signals are aligned. When the first sequence of signals and the second sequence of signals are aligned in time sequence, when each first switch element is closed, each second switch element is disconnected; and when each second switch element is closed, each first switch element is disconnected, ensuring a single-stage High symmetry of switches on different branches in the voltage doubler unit.

In Fig. 2, S-LEVEL1 represents the enable signal, SW1-1 represents the first sequence signal controlling the operation of the switch SW1-1; SW1-2 represents the first sequence signal controlling the operation of the switch SW1-2; SW2-1 represents the control switch SW2 -1 is the second sequence signal of action; SW2-2 is the second sequence signal that controls the action of switch SW2-2; T _J1 is the third sequence signal; T _J12 is the fifth sequence signal; T _J2 is the fourth sequence signal.

There are many ways to align the sequence signal timing. In this embodiment, the timing alignment of each first sequence signal is corrected by logical operation, and it can be understood that the third sequence signal is used as a correction signal and is set to be active high, as shown in FIG. 2 . Each first sequence signal and the third sequence signal perform an "OR" logic operation, then the rising edge of the fourth pulse and the eighth pulse of each group of sequences in each first sequence signal starts from the rising edge of the pulse of the third sequence signal. Taking effect at the same time, the alignment of the rising edge of each pulse of the third sequence signal and the corresponding rising edge of the pulse of the first sequence signal is realized. As shown in FIG. 2, each group of sequences in the first sequence signal includes 8 pulses. The same is true for the timing alignment correction of the second sequence signal. If the first sequence signal and the second sequence signal are inverted signals, when the fifth sequence signal is used for timing alignment, the following logical operations are respectively used to perform timing alignment. Each first sequence signal and the fifth sequence signal perform an "OR" logic operation, then the rising edge of the first pulse of each group of sequences in each first sequence signal takes effect at the same time from the rising edge of the pulse of the fifth sequence signal. The rising edge of each pulse of the fifth sequence signal is aligned with the corresponding rising edge of the pulse of the first sequence signal.

The “AND” logic operation is performed between each second sequence signal and the fifth sequence signal after the logical NOT operation has been performed, then the falling edge of the first pulse of each group of each second sequence signal is changed from the rising edge of the pulse of the fifth sequence signal. At the same time, the rising edge of each pulse of the fifth sequence signal is aligned with the falling edge of the corresponding pulse of the second sequence signal.

It should be noted that the peak pulse position of each correction signal may be set at the falling edge or the rising edge of the corrected pulse, which is not limited here. Wherein, the logical operation may use a single AND, OR, NOT, AND NOT, OR NOT operation, or a combined operation of several of them, which is not limited here, according to application requirements.

In addition, in software implementation, for example, but not limited to, a non-blocking assignment method can be used for the first sequence signal and the second sequence signal, and a blocking assignment method can be used for the third sequence signal, the fourth sequence signal, and the fifth sequence signal. Way.

Further, the sequence signal generator is a programmable logic device (Programmable Logic Device; PLD for short), a Complex Programmable Logic Device (CPLD for short), or a Field-Programmable Gate Array (FPGA for short) ).

The FPGA can perform logic programming in advance according to the timing requirements of each branch switch action, so as to realize the output port of the FPGA to each branch switch to output the sequence signal for control according to the required timing requirements. PLDs and CPLDs are similar to FPGAs and will not be repeated here.

Further, the pulse interval of the first sequence signal and the second sequence signal is one switching clock cycle, the pulse interval of the third sequence signal and the fourth sequence signal is n switching clock cycles, and the pulse interval of the fifth sequence signal is 2n. Switch clock period, where n is a natural number greater than 2. FIG. 2 shows a specific embodiment, wherein the pulse interval of the third sequence signal and the fourth sequence signal is 4 switching clock cycles, and the pulse interval of the fifth sequence signal is 8 switching clock cycles.

In this embodiment, the enable signal S-level1 is valid at a high level, valid when the level rises from a low level to a high level, and the hold circuit can keep the level at a high level under normal working conditions .

The first sequence signal and the second sequence signal are both square wave pulse signals. Since the high and low levels of the square wave each occupy half a switching clock cycle, high symmetry of switches on different branches in the single-stage voltage multiplier unit can be ensured. The third sequence signal, the fourth sequence signal, and the fifth sequence signal are spike pulse signals. Specifically, their waveforms can be rectangular waves whose pulse width is smaller than the above-mentioned square wave pulse width, and the pulse width can be adjusted as required. It should be noted that the square wave pulses of the first sequence signal and the second sequence signal can be generated by one clock; the spike pulses of the third sequence signal, the fourth sequence signal and the fifth sequence signal can be generated by another relatively accurate clock. It can be understood that the generation of the above clock can be obtained by using a crystal oscillator integrated inside the CPLD/FPGA, or generated by an external crystal oscillator.

Further, an embodiment of the present invention also provides a method for controlling a voltage doubling circuit unit, which is used for on-off control of a switching element of the voltage doubling circuit unit. The voltage doubling circuit unit includes a first branch and a second branch. The branch has at least two first switching elements, the second branch has at least two second switching elements, and after obtaining the enable signal, the sequence signal generator generates multiple first sequence signals, multiple second sequence signals, The third sequence signal, the fourth sequence signal and the fifth sequence signal, wherein the third sequence signal, the fourth sequence signal and the fifth sequence signal are all correction signals; The second sequence signal is used to perform one-to-one on-off control of the second switching element; the first sequence signal and the second sequence signal are inverted; the third sequence signal is used for each first sequence signal timing alignment correction; the fourth sequence signal is used for timing alignment correction on each second sequence signal; the fifth sequence signal is used for timing alignment correction on the first sequence signal and the second sequence signal.

Because the first sequence signal and the second sequence signal are inverted signals, and the third sequence signal ensures the timing alignment of the first sequence signals, the fourth sequence signal ensures the timing alignment of the second sequence signals, and the fifth sequence signal ensures that the timing alignment of the second sequence signals The timing of the first sequence signal and the second sequence signal are aligned, then when each first switching element is closed, each second switching element is disconnected; and when each second switching element is closed, each first switching element is disconnected, ensuring a single High symmetry of the switches on the different branches in the stage voltage doubler unit.

Further, the third sequence signal is used to correct the timing alignment of each first sequence signal; the fourth sequence signal is used to correct the timing alignment of each second sequence signal; the fifth sequence signal is used to correct the first sequence signal The correction of timing alignment with the second sequence signal includes:

Use the third sequence signal to perform logical AND, OR, and NOT operations on the first sequence signal, so that the pulse rising edge/falling edge of the first sequence signal is aligned with the corresponding pulse rising edge/falling edge of the third sequence signal;

Use the fourth sequence signal to perform logical AND, OR, and NOT operations on the second sequence signal, so that the rising edge/falling edge of the pulse of the second sequence signal is aligned with the corresponding pulse rising edge/falling edge of the fourth sequence signal;

Use the fifth sequence signal to perform logical AND, OR, and NOT operation on the first sequence signal and the second sequence signal, so that the pulse rising edge/falling edge of the first sequence signal and the second sequence signal corresponds to the signal of the fifth sequence signal Pulse rising/falling edge alignment.

On the other hand, referring to FIG. 3 , an embodiment of the present invention provides a multi-stage voltage doubling circuit, including a plurality of the above-mentioned voltage doubling circuit units connected in sequence, and the sequence signal generator is used for the voltage doubling circuits of all levels. The switch performs on-off control, and the output end of the previous stage voltage doubling circuit unit is connected with the input end of the latter stage voltage doubling circuit unit; the output end of the previous stage voltage doubling circuit unit is also connected to the latter stage voltage doubling circuit unit The feedback unit (Feedback) for enabling control, the first-stage voltage doubling circuit unit 31 and the last-stage voltage doubling circuit unit 32 are shown in FIG. describe. The voltage output terminal VDDH1 of the last stage of the voltage doubling circuit unit 32 is also connected to two grounded capacitors C4 and CJ1 and two series connected resistors R1 and R2. A voltage output stage VDDH is connected between the resistors R1 and R2.

By setting the feedback unit, the two stages before and after can be correlated. On the one hand, it can assist the synchronization between the stages when the circuit is working normally, and it can also be interrupted in time when the circuit is working abnormally. For example, whether the voltage doubler circuit unit of the latter stage is working, Controlled by the previous stage voltage doubling circuit unit, the latter stage voltage doubling circuit unit will work only when the previous stage voltage doubling circuit unit works normally, which can effectively interrupt the program and avoid high voltage damage to other devices.

Further, the feedback unit is a switching device or circuit that conducts unidirectionally from the previous stage to the subsequent stage. The switching device can be, for example, a diode, the anode of the diode is connected to the output end of the voltage doubling circuit unit of the previous stage, and the cathode is connected to the input end of the voltage doubling circuit unit of the subsequent stage. The negative pole is also connected to an external voltage. Specifically, when the normal voltage multiplier value of the output terminal VDDH1 ′ of the previous stage voltage multiplier circuit unit is 4V, the external voltage can be 3.9V. At this time, when the output of the first-stage voltage doubling circuit unit is not stable to a voltage above 3.9V, the diode is not turned on, and the latter-stage voltage doubling circuit unit cannot work; the output of the current-stage voltage doubling circuit unit is stable When it reaches 4V, the diode is turned on, and the subsequent voltage doubler circuit unit starts to work. The specific value of the external voltage is determined according to the normal voltage multiplier value of the output terminal VDDH1 ′ of the previous stage voltage multiplier circuit unit and the turn-on voltage value of the diode, which will not be listed one by one here. In addition, a circuit that can realize unidirectional conduction can also be selected as required, and the circuit can be an existing circuit, and its structure will not be described in detail here.

Further, in order to ensure sufficient charging and discharging time between the preceding and subsequent stages, the switching frequency of the voltage doubling circuit unit of the previous stage is more than twice the switching frequency of the voltage doubling circuit unit of the subsequent stage.

For example, this embodiment is described by taking a two-stage voltage doubling circuit unit as an example. Referring to FIG. 4 , the switching frequency of the first-stage voltage doubling circuit unit is twice the switching frequency of the second-stage voltage doubling circuit unit. In the second-stage voltage multiplier circuit unit, the pulse interval of the third sequence signal and the fourth sequence signal as its pulses can also be set to 4 switching clock cycles of this stage, and the pulse interval of the fifth sequence signal is also 8 of this stage. switch clock cycle. That is to say, the structure of the voltage doubling circuit units at all levels is unified, and its control can correspond to the same program module. It only needs to set the only transmission parameter of the switching frequency, and at the same time, set the interval coefficient through the global variable, and uniformly modify the calibration point of the voltage doubling circuit unit. , and adjust the width of each alignment pulse through a local variable to precisely control the alignment (ie synchronization) of the corresponding sequence signal. The timing sequence between the voltage multiplier circuit units at all levels is relatively loose, and there is no need to align the sequence signals, so the sequence scheduling process of the sequence signal generator is simplified and the resource occupation is reduced.

In Fig. 3, S-LEVEL1 represents the enable signal of the first stage voltage doubling circuit unit, SW1-1 represents the first sequence signal that controls the action of the first stage voltage doubling circuit unit switch SW1-1; SW1-2 represents the control of the first stage The first sequence signal for the action of the voltage doubling circuit unit switch SW1-2; SW2-1 represents the second sequence signal for controlling the action of the first stage voltage doubling circuit unit switch SW2-1; SW2-2 represents the control of the first stage voltage doubling circuit unit The second sequence signal of the switch SW2-2 action; T _J1 represents the third sequence signal of the first stage voltage doubling circuit unit; T _J12 represents the fifth sequence signal of the first stage voltage doubling circuit unit; T _J2 represents the first stage doubling signal the fourth sequence signal of the voltage circuit unit. S-LEVEL2 represents the enable signal of the second-level voltage doubling circuit unit, SW1-1' represents the first sequence signal that controls the action of the second-level voltage doubling circuit unit switch SW1-1; SW1-2' represents the control of the second-level voltage doubling circuit unit The second sequence signal of the voltage circuit unit switch SW1-2; SW2-1' represents the second sequence signal to control the action of the second-stage voltage multiplier circuit unit switch SW2-1; SW2-2' represents the control of the second-stage voltage multiplier circuit The second sequence signal of the unit switch SW2-2 action; T _J1' represents the third sequence signal of the second-stage voltage doubling circuit unit; T _J12' represents the fifth sequence signal of the second-stage voltage doubling circuit unit; T _J2' represents the second sequence signal The fourth sequence signal of the second-stage voltage multiplier circuit unit.

As yet another aspect, the present application also provides a computer-readable storage medium. The computer-readable storage medium may be a computer-readable storage medium included in the apparatus described in the foregoing embodiments; A computer-readable storage medium that fits into a device. The computer-readable storage medium stores one or more programs used by one or more processors to execute the voltage doubler circuit unit control method described in this application.

The above description is only a preferred embodiment of the present application and an illustration of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solution formed by the specific combination of the above-mentioned technical features, and should also cover the above-mentioned technical features without departing from the inventive concept. Other technical solutions formed by any combination of its equivalent features. For example, a technical solution is formed by replacing the above-mentioned features with the technical features disclosed in this application (but not limited to) with similar functions.

Claims (10)

1. A voltage doubling circuit unit, characterized in that it comprises a first branch and a second branch, the first branch has at least two first switching elements, and the second branch has at least two first switching elements. Two switching elements; a sequence signal generator for generating a plurality of first sequence signals, a plurality of second sequence signals, a third sequence signal, a fourth sequence signal and a fifth sequence signal, wherein the third sequence signal, the fourth sequence signal and the The fifth sequence of signals are all correction signals; The first sequence signal is used for one-to-one on-off control of the first switch element; The second sequence signal is used for one-to-one on-off control of the second switching element; the first sequence signal and the second sequence signal are out of phase; The third sequence signal is used to perform timing alignment correction on each of the first sequence signals; The fourth sequence signal is used to perform timing alignment correction on each of the second sequence signals; The fifth sequence signal is used to correct the timing alignment of the first sequence signal and the second sequence signal. 2. The voltage multiplier circuit unit according to claim 1, wherein the sequence signal generator further comprises a correction unit, and the correction unit is configured to: Use the third sequence signal to perform logical AND, OR, and NOT operation on the first sequence signal, so that each pulse rising edge/falling edge of the third sequence signal and the corresponding pulse rising edge of the first sequence signal edge/falling edge alignment; The fourth sequence signal is used to perform logical AND, OR, and NOT operation on the second sequence signal, so that each pulse rising edge/falling edge of the fourth sequence signal corresponds to the corresponding pulse rising edge of the second sequence signal. /falling edge aligned; Use the fifth sequence signal to perform logical AND, OR, and NOT operation on the first sequence signal and the second sequence signal, so that each pulse rising edge/falling edge of the fifth sequence signal is combined with the sum of the first sequence signal and the second sequence signal. Corresponding pulse rising/falling edges of the second sequence of signals are aligned. 3. The voltage multiplier circuit unit according to claim 1 or 2, wherein the first sequence signal and the second sequence signal are square wave pulse signals, the third sequence signal, the fourth sequence signal The sequence signal and the fifth sequence signal use a spike signal. 4 . The voltage multiplier circuit unit according to claim 3 , wherein the pulse interval of the first sequence signal and the second sequence signal is one switching clock cycle, the third sequence signal and the first sequence signal are The pulse interval of the four-sequence signal is n switching clock cycles, and the pulse interval of the fifth sequence signal is 2n switching clock cycles, where n is a natural number greater than 2. 5. A method for controlling a voltage doubling circuit unit, which is used for on-off control of a switching element of the voltage doubling circuit unit, the voltage doubling circuit unit comprising a first branch and a second branch, and the first branch has At least two first switching elements, the second branch has at least two second switching elements, characterized in that: After obtaining the enable signal, the sequence signal generator generates a plurality of first sequence signals, a plurality of second sequence signals, a third sequence signal, a fourth sequence signal and a fifth sequence signal, wherein the third sequence signal, the The fourth sequence signal and the fifth sequence signal are both correction signals; The first sequence signal is used for one-to-one on-off control of the first switch element; The second sequence signal is used for one-to-one on-off control of the second switching element; the first sequence signal and the second sequence signal are out of phase; The third sequence signal is used to perform timing alignment correction on each of the first sequence signals; The fourth sequence signal is used to perform timing alignment correction on each of the second sequence signals; The fifth sequence signal is used to correct the timing alignment of the first sequence signal and the second sequence signal. 6 . The method for controlling a voltage multiplier circuit unit according to claim 5 , wherein the third sequence signal is used to correct the timing alignment of each of the first sequence signals; the fourth sequence signal is used to Performing timing alignment correction on each of the second sequence signals; the fifth sequence signal used for performing timing alignment correction on the first sequence signal and the second sequence signal respectively includes: using the third sequence The signal performs logical AND, OR, and NOT operation on the first sequence signal, so that each pulse rising edge/falling edge of the third sequence signal is aligned with the corresponding pulse rising edge/falling edge of the first sequence signal; The fourth sequence signal is used to perform logical AND, OR, and NOT operation on the second sequence signal, so that each pulse rising edge/falling edge of the fourth sequence signal corresponds to the pulse rising edge of the second sequence signal. /falling edge aligned; Use the fifth sequence signal to perform logical AND, OR, and NOT operation on the first sequence signal and the second sequence signal, so that each pulse rising edge/falling edge of the fifth sequence signal is combined with the sum of the first sequence signal and the second sequence signal. Corresponding pulse rising/falling edges of the second sequence of signals are aligned. 7. A multi-stage voltage doubling circuit, characterized in that it comprises a plurality of sequentially connected voltage doubling circuit units as described in any one of claims 1-4, and the output end of the voltage doubling circuit unit in the previous stage is the input end of the voltage multiplier circuit unit in the latter stage is connected; The output end of the voltage doubling circuit unit of the previous stage is further connected with a feedback unit for enabling and controlling the voltage doubling circuit unit of the subsequent stage. 8 . The multi-stage voltage doubling circuit according to claim 7 , wherein the feedback unit is a switching device or circuit that conducts unidirectionally from a previous stage to a subsequent stage. 9 . 9 . The multi-stage voltage doubling circuit according to claim 7 , wherein the switching frequency of the voltage doubling circuit unit in the previous stage is twice the switching frequency of the voltage doubling circuit unit in the latter stage. 10 . above. 10. A computer-readable storage medium on which a computer program is stored, characterized in that, when the computer program is executed by a processor, the method according to any one of claims 5-6 is implemented.