CN110047757A - The preparation method of the trench-type power semiconductor device of low cost - Google Patents

Abstract

The invention relates to a method for preparing a low-cost trench type power semiconductor device. A substrate terminal trench is arranged in a terminal area of a semiconductor substrate, and a second conductive type body region of the terminal area is formed in cooperation with the substrate terminal trench. The required terminal region structure, and the second conductive type body region is obtained without a mask. Compared with the existing process, the trench type power semiconductor device can use one less mask when preparing the front structure, effectively reducing the cost of Fabrication cost of power semiconductor devices. By using the base region of the second conductivity type of the substrate existing in the active region, the doping concentration of the second conductivity type in the active region can be adjusted, and the breakdown characteristics of the terminal region of the prepared power semiconductor device can be ensured. The conduction characteristics of the source region, the entire process is compatible with the existing process, safe and reliable.

Description

Method for fabricating low-cost trench-type power semiconductor devices

technical field

The invention relates to a preparation method, in particular to a preparation method of a low-cost trench type power semiconductor device, and belongs to the technical field of power semiconductor device preparation technology.

Background technique

At present, power semiconductor devices are developing rapidly. On the one hand, the technology of IGBT and VDMOS is constantly innovating to achieve excellent performance; on the other hand, low cost has also become the pursuit goal of power semiconductor development. In the processing cost of power semiconductors, the cost of the mask and the corresponding photolithography process are often the main factors, so reducing the number of masks becomes the key to reducing the cost of the device. In most cases, there is often a trade-off between high-performance devices and low cost, unless new devices, process methods, etc. appear.

As shown in FIG. 1 to FIG. 11 , the manufacturing process steps of the front surface structure of the existing trench type power semiconductor device are shown. Specifically,

As shown in FIG. 1 , an N-type semiconductor substrate 1 is provided, and a first photoresist layer 2 of the substrate is coated on the front surface of the semiconductor substrate 1 , and the first photoresist layer 2 of the substrate is subjected to Photolithography is performed to obtain the first photoresist layer window 4 of the substrate passing through the first photoresist layer 2 of the substrate.

As shown in FIG. 2 , the front surface of the semiconductor substrate 1 is implanted by using the first photoresist layer 2 of the substrate and the window 4 of the first photoresist layer of the substrate to obtain a terminal ring 5 located in the terminal area. The window 4 of the first photoresist layer 2 of the substrate corresponds to the window 4 of the first photoresist layer of the substrate.

As shown in FIG. 3 , the first photoresist layer 2 of the substrate is removed, and a field oxide layer 7 and a second photoresist layer 8 of the substrate covering the field oxide layer 7 are arranged on the front surface of the semiconductor substrate 1 , The second photoresist layer 8 of the substrate is photoetched by using the second mask plate 6 of the substrate, and the field oxide layer 7 corresponding to the active region is etched by the second photoresist layer 8 of the substrate after photoetching, so as to A field oxide layer 7 on the termination region can be obtained;

As shown in FIG. 4 , the second photoresist layer 8 of the substrate is removed, and the third photoresist layer 9 of the substrate is coated on the active area of the semiconductor substrate 1 and the field oxide layer 7, and the third mask of the substrate is used. 10. Perform photolithography on the third photoresist layer 9 of the substrate to obtain the third photoresist layer window 12 of the substrate passing through the third photoresist layer 9 of the substrate; use the third photoresist layer 9 of the substrate and the third photoresist layer of the substrate The resist layer window 12 is used to etch the semiconductor substrate 1 in the active region to obtain the active region trench 11 in the active region.

As shown in FIG. 5 , the third photoresist layer 9 of the substrate is removed, an insulating gate oxide layer 13 is grown in the active region trench 11 , and an insulating gate oxide layer 13 is grown in the active region trench 11 The trench conductive polysilicon 14 is filled and the excess polysilicon is etched away.

As shown in FIG. 6 , P-type ions are implanted and propelled above the semiconductor substrate 1 to obtain a substrate P-type base region 15 located in the active region. At the same time, the field oxide layer 7 on the semiconductor substrate 1 can be used to The P-type ions are blocked from being implanted into the termination region, and the P-type base region 15 of the substrate is located above the bottom of the trench 11 in the active region.

As shown in FIG. 7 , N-type ions are implanted and propelled above the semiconductor substrate 1 to obtain a substrate N+ active layer 16 located in the active region, and the substrate N+ active layer 16 is located on the substrate P-type Above the base region 15, the N-type ion implantation into the termination region can be blocked by the field oxide layer 7.

As shown in FIG. 8 , a dielectric layer is deposited on the front surface of the above-mentioned semiconductor substrate 1, and the dielectric layer covers the substrate N+ active layer 16 and the field oxide layer 7 to obtain a substrate dielectric layer 17. The substrate dielectric layer 17 covers the notch of the trench 11 in the active region; coat the fourth substrate photoresist layer 18 on the substrate dielectric layer 17, and use the substrate fourth mask 19 to perform photolithography on the substrate fourth photoresist layer 18 to A window 20 of the fourth photoresist layer of the substrate passing through the fourth photoresist layer 18 of the substrate is obtained, and the window 20 of the fourth photoresist layer of the substrate is located above the active region.

As shown in FIG. 9 , the substrate dielectric layer 17 and the substrate N+ active layer 16 are etched by using the substrate fourth photoresist layer 18 and the substrate fourth photoresist layer window 20 to obtain the substrate fourth photoresist The substrate contact holes 24 corresponding to the layer windows 20 pass through the substrate dielectric layer 17 , and the substrate N+ source regions 23 are obtained on both sides of the active region trench 11 .

As shown in FIG. 10 , the fourth photoresist layer 18 of the substrate is removed, and metal deposition is performed on the front surface of the semiconductor substrate 1 to obtain a front metal layer, which covers the substrate dielectric layer 17 and is filled in inside the substrate contact hole 24 .

The fifth photoresist layer 26 of the substrate is coated on the front metal layer, and the fifth photoresist layer 26 of the substrate is photoetched by using the fifth mask 27 of the substrate, so as to obtain a substrate penetrating the fifth photoresist layer 26 of the substrate The fifth photoresist layer window 28, the fifth photoresist layer window 28 of the substrate is located above the termination area. The front metal layer of the substrate is etched by using the fifth photoresist layer 26 of the substrate and the window 28 of the fifth photoresist layer of the substrate to obtain the metal separation hole 22 of the substrate, and the front metal layer is separated by the metal separation hole 22 to form the substrate terminal The front metal 25 and the front metal 21 of the substrate cell.

As shown in FIG. 11 , a passivation layer is deposited above the front surface of the semiconductor substrate 1 to obtain a front surface passivation layer 29 of the substrate, and the front surface passivation layer 29 covers the front metal layer 25 and the cell of the substrate terminal. On the front metal layer 21 , and the substrate front passivation layer 29 is filled in the substrate metal separation hole 22 .

The sixth photoresist layer 30 of the substrate is coated on the front passivation layer 29 of the substrate, and the sixth photoresist layer 30 of the substrate is photoetched by using the sixth mask plate 31 of the substrate, and the sixth photoresist layer 30 of the substrate after photoetching is used. The resist layer 30 etches the front surface passivation layer 29 of the substrate to obtain a substrate source pad hole 32 penetrating the front surface passivation layer 29 of the substrate. exposed.

After removing the sixth photoresist layer 30 of the substrate, the processing steps of the source pad can be performed; in addition, a backside process needs to be performed on the backside of the semiconductor substrate 1, and the required MOSFET device or IGBT device can be obtained according to the difference of the backside process. , the backside process can adopt the existing common process steps, which are well known to those skilled in the art, and will not be repeated here.

To sum up, for a MOSFET device or an IGBT device, at least six masks need to be provided during the front-side process to use the corresponding mask to perform the corresponding photolithography process steps, so that the prepared MOSFET device or IGBT device can be prepared. higher cost.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies in the prior art, and to provide a low-cost preparation method of a trench type power semiconductor device, which is compatible with the existing technology, reduces the preparation cost of the power semiconductor device, and is safe and reliable.

According to the technical solution provided by the present invention, a low-cost preparation method of a trench type power semiconductor device, the preparation method includes the following steps:

Step 1. Provide a semiconductor substrate with a first conductivity type, and perform trench etching on the semiconductor substrate to obtain a desired substrate trench, where the substrate trench includes a liner located in the active region. a bottom cell trench and a substrate termination trench located in the termination region;

Step 2, performing an oxide layer growth process in the above-mentioned substrate trench to obtain a cell insulating oxide layer covering the inner wall of the substrate cell trench and a terminal insulating oxide layer covering the inner wall of the substrate terminal trench; The substrate cell trench of the cell insulating oxide layer is filled with conductive polysilicon of the substrate cell, and at the same time, the substrate terminal conductive polysilicon is filled in the substrate terminal trench where the terminal insulating oxide layer is grown;

Step 3. Perform implantation and advancement of impurity ions of the second conductivity type on the front surface of the semiconductor substrate to obtain a second conductivity type body region traversing the upper part of the semiconductor substrate, and the second conductivity type body region is located in the substrate. Above the bottom of the bottom groove;

Step 4: Coating a photoresist layer on the front side of the above-mentioned semiconductor substrate, and using the second mask of the substrate to perform photolithography on the coated photoresist layer to obtain a substrate covering the terminal area of the semiconductor substrate a second photoresist layer;

Step 5, using the second photoresist layer of the substrate to implant the impurity ions of the first conductivity type and the impurity ions of the second conductivity type into the semiconductor substrate, and remove the second photoresist layer of the substrate after the implantation, and after annealing The first conductive type source doped region of the substrate and the second conductive type base region of the substrate located in the active region of the semiconductor substrate are obtained, and the second conductive type base region of the substrate is located at the bottom of the cell trench groove of the substrate Above, the first conductive type source doped region of the substrate is located above the second conductive type base region of the substrate, and the first conductive type source doped region of the substrate and the second conductive type base region of the substrate are both connected to the corresponding substrate The outer sidewall of the cell trench contacts;

In step 6, a dielectric layer is deposited on the front surface of the above-mentioned semiconductor substrate to obtain a substrate dielectric layer covering the front surface of the semiconductor substrate; the third photoresist layer of the substrate is coated on the substrate dielectric layer, and the The three masks perform photolithography on the third photoresist layer of the substrate to obtain a window of the third photoresist layer of the substrate passing through the third photoresist layer of the substrate;

Step 7: Etching the substrate dielectric layer by using the above-mentioned third substrate photoresist layer and the substrate third photoresist layer window to obtain through the substrate dielectric layer and the first conductive type source doped region of the substrate A medium contact hole is formed, and the first conductive type source doped region of the substrate can form the required first conductive type source region of the substrate through the medium contact hole;

Step 8: Remove the third photoresist layer of the above-mentioned substrate, and deposit a metal layer on the above-mentioned substrate dielectric layer to obtain a front-side metal layer of the substrate, and the front-side metal layer of the substrate is covered on the substrate dielectric layer and is Filled in the dielectric contact hole, the front metal layer of the substrate filled in the dielectric contact hole is in ohmic contact with the source region of the first conductivity type of the substrate and the base region of the second conductivity type of the substrate;

Step 9: Coating the fourth photoresist layer of the substrate on the metal layer on the front side of the substrate, and using the fourth mask of the substrate to perform photolithography on the fourth photoresist layer of the substrate to obtain the fourth photoresist penetrating the substrate. The fourth photoresist layer window of the substrate of the resist layer is used to etch the metal layer on the front side of the substrate by using the fourth photoresist layer of the substrate and the window of the fourth photoresist layer of the substrate, so as to obtain a metal layer through the front side of the substrate The substrate metal separation hole of the layer, and the substrate metal separation hole can be used to separate the substrate front metal layer to obtain the substrate cell front metal layer and the substrate terminal front metal layer, and the substrate cell front metal layer and the lining the bottom first conductive type source region and the substrate second conductive type base region are in ohmic contact;

Step 10, removing the above-mentioned fourth photoresist layer of the substrate and depositing a passivation layer to obtain a front-side passivation layer covering the front-side metal layer of the substrate cell and the front-side metal layer of the substrate terminal, and all The front passivation layer of the substrate is also filled in the metal separation hole of the substrate;

Step 11, coat the fifth photoresist layer of the substrate on the front passivation layer of the substrate, use the fifth mask layer of the substrate to perform photolithography on the fifth photoresist layer of the substrate, and use the photoetched photoresist layer. The fifth photoresist layer of the substrate etches the front passivation layer of the substrate to obtain a substrate source pad hole penetrating the front passivation layer of the substrate. The front metal layer of the substrate cell corresponding to the substrate source pad hole is exposed;

Step 12, removing the above-mentioned fifth photoresist layer of the substrate, and performing a required backside process on the backside of the semiconductor substrate.

In step 1, the first photoresist layer of the substrate is coated on the front side of the semiconductor substrate, and the first photoresist layer of the substrate is photoetched by using the first mask of the substrate, so as to obtain the first photoresist layer through the substrate. The first photoresist layer window of the substrate of the photoresist layer, after the front surface of the semiconductor substrate is etched by using the first photoresist layer of the substrate and the window of the first photoresist layer of the substrate, the required lining can be obtained. Bottom groove.

The material of the semiconductor substrate includes silicon.

In step 2, the cell insulating oxide layer and the terminal insulating oxide layer are the same process step layer, and the cell insulating oxide layer and the terminal insulating oxide layer are silicon dioxide layers.

The doping concentration of the second conductive type base region of the substrate is greater than the doping concentration of the second conductive type body region.

In both the "first conductivity type" and the "second conductivity type", for N-type power semiconductor devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power semiconductor devices, the first conductivity type refers to N-type. A conductivity type and a second conductivity type refer to types that are just opposite to N-type power semiconductor devices.

The advantages of the present invention: a substrate terminal trench is arranged in the terminal area of the semiconductor substrate, a terminal insulating oxide layer and a substrate terminal conductive polysilicon are arranged in the substrate terminal trench, and the second conductivity type is performed on the front side of the semiconductor substrate. Impurity ion implantation can obtain the second conductivity type body region, and the second conductivity type body region of the terminal region cooperates with the substrate terminal trench to form the required terminal region structure, and the mask plate is not required to obtain the second conductivity type body region Compared with the existing process, the trench type power semiconductor device can use less mask when preparing the front structure, which effectively reduces the preparation cost of the power semiconductor device.

The active region of the semiconductor substrate can be implanted with N-type impurity ions and P-type impurity ions by using the second photoresist layer of the substrate. After the second photoresist layer of the substrate is removed and activated by annealing, the first substrate A conductive type source doping region and a second conductive type base region of the substrate can reduce the use of masks and further reduce the cost under the condition of ensuring the doping concentration of the second conductive type base region of the substrate. By using the second conductive type base region of the substrate in the active region, the doping concentration of the second conductive type in the active region can be adjusted, which ensures the breakdown characteristics of the terminal region of the prepared power semiconductor device and the active The conduction characteristics of the region, the entire process is compatible with the existing process, safe and reliable.

Description of drawings

1 to 11 are cross-sectional views of the specific manufacturing process steps of the conventional power semiconductor device, wherein

FIG. 1 is a cross-sectional view after obtaining a first photoresist layer window of a substrate.

FIG. 2 is a cross-sectional view after obtaining the terminal ring.

FIG. 3 is a schematic diagram after etching the field oxide layer of the active region.

FIG. 4 is a cross-sectional view after obtaining trenches in the active region.

FIG. 5 is a cross-sectional view after obtaining trench conductive polysilicon.

FIG. 6 is a cross-sectional view after obtaining the P-type base region of the substrate.

FIG. 7 is a cross-sectional view after obtaining the N+ active layer of the substrate.

FIG. 8 is a cross-sectional view after obtaining a fourth photoresist layer window of the substrate.

FIG. 9 is a cross-sectional view after obtaining a substrate contact hole.

FIG. 10 is a cross-sectional view after obtaining the metal separation holes of the substrate.

FIG. 11 is a cross-sectional view after obtaining a substrate source pad hole.

12 to 19 are cross-sectional views of the specific implementation process steps of the present invention, wherein

FIG. 12 is a cross-sectional view of the substrate trench obtained by the present invention.

FIG. 13 is a cross-sectional view of the substrate cell conductive polysilicon and the substrate terminal conductive polysilicon obtained by the present invention.

FIG. 14 is a cross-sectional view after the P-type base region is obtained in the present invention.

FIG. 15 is a cross-sectional view of the present invention after obtaining the second photoresist layer of the substrate.

FIG. 16 is a cross-sectional view of the substrate N+ source doped region obtained by the present invention.

FIG. 17 is a cross-sectional view of the present invention after obtaining the window of the third photoresist layer of the substrate.

18 is a cross-sectional view of the present invention after obtaining a dielectric contact hole.

FIG. 19 is a cross-sectional view of the present invention after obtaining the substrate metal separation hole.

FIG. 20 is a cross-sectional view of the present invention after obtaining the substrate source pad hole.

Description of reference numerals: 1-semiconductor substrate, 2-substrate first photoresist layer, 3-substrate first mask, 4-substrate first photoresist layer window, 5-terminal ring, 6-substrate second mask Template, 7-field oxide layer, 8-substrate second photoresist layer, 9-substrate third photoresist layer, 10-substrate third mask, 11-active area trench, 12-substrate third photoresist Resist layer window, 13-insulation gate oxide layer, 14-trench conductive polysilicon, 15-substrate P-type base region, 16-substrate N+ active layer, 17-substrate dielectric layer, 18-substrate fourth photoresist layer , 19-substrate fourth mask, 20-substrate fourth photoresist layer window, 21-substrate cell front metal, 22-substrate metal separation hole, 23-substrate N+ source region, 24-substrate contact hole, 25- Front side metal of substrate terminal, 26-substrate fifth photoresist layer, 27-substrate fifth mask, 28-substrate fifth photoresist layer window, 29-substrate front passivation layer, 30-substrate sixth photoresist layer, 31-substrate sixth mask, 32-substrate source pad hole, 33-substrate first photoresist layer, 34-substrate first mask, 35-substrate terminal trench, 36-liner Bottom cell trench, 37-terminal insulating oxide layer, 38-substrate terminal conductive polysilicon, 39-P-type body region, 40-substrate second photoresist layer, 41-substrate second mask, 42- Substrate P-type base region, 43-substrate third photoresist layer, 44-substrate third mask, 45-substrate third photoresist layer window, 46-substrate N+ source doping region, 47 -Substrate N+ source region, 48-media contact hole, 49-substrate fourth mask, 50-substrate fourth photoresist layer, 51-substrate terminal front side metal layer, 52-substrate fourth lithography Adhesive layer window, 53-substrate dielectric layer, 54-substrate front passivation layer, 55-substrate fifth photoresist layer, 56-substrate fifth mask, 57-substrate source pad hole, 58-semiconductor substrate, 59-substrate cell conductive polysilicon, 60-cell insulating oxide layer, 61-substrate cell front metal layer and 62-substrate metal separation hole.

Detailed ways

The present invention will be further described below with reference to the specific drawings and embodiments.

As shown in FIGS. 12 to 19 : in order to prepare a low-cost trench-type power semiconductor device, an N-type power semiconductor device is used to illustrate the specific preparation process steps of the present invention. Specifically, the preparation method includes the following steps :

Step 1. Provide an N-type semiconductor substrate 58, and perform trench etching on the semiconductor substrate 58 to obtain a desired substrate trench, and the substrate trench includes the substrate located in the active region cell trenches 36 and substrate termination trenches 35 in the termination region;

Specifically, the material of the semiconductor substrate 58 includes silicon. Of course, the semiconductor substrate 58 can also use other common semiconductor materials, and the specific type can be selected according to needs, which is well known to those skilled in the art, and will not be repeated here. During specific implementation, the first substrate photoresist layer 33 is coated on the front side of the semiconductor substrate 58, and the substrate first photoresist layer 33 is photoetched by using the substrate first mask 34, so as to obtain through The substrate first photoresist layer window of the substrate first photoresist layer 33 is used to etch the front surface of the semiconductor substrate by using the substrate first photoresist layer 33 and the substrate first photoresist layer window, The desired substrate trench can be obtained, as shown in FIG. 12 .

In the embodiment of the present invention, the substrate cell trench 36 is located in the active area of the semiconductor substrate 58 , the substrate terminal trench 35 is located in the terminal area of the semiconductor substrate 58 , and the active area is generally located in the semiconductor substrate 58 . The central area and the terminal area are located in the outer ring of the active area, and the relative positional relationship between the active area and the terminal area is set by those skilled in the art as needed, which is well known to those skilled in the art, and will not be repeated here. . The substrate cell trenches 36 and the substrate terminal trenches 35 have the same depth. The depths of the substrate cell trenches 36 and the substrate terminal trenches 35 are both smaller than the thickness of the semiconductor substrate 58 . The substrate cell trenches have the same depth. 36. The substrate termination trench 35 extends vertically downward from the front surface of the semiconductor substrate 58.

Step 2, performing an oxide layer growth process in the above-mentioned substrate trench to obtain a cell insulating oxide layer 60 covering the inner wall of the substrate cell trench 36 and a terminal insulating oxide layer 37 covering the inner wall of the substrate terminal trench 35; The substrate cell conductive polysilicon 59 is filled in the substrate cell trench 36 on which the cell insulating oxide layer 60 is grown, and the substrate terminal conductive polysilicon 59 is filled in the substrate terminal trench 35 where the terminal insulating oxide layer 37 is grown. polysilicon 38;

Specifically, the cell insulating oxide layer 60 and the terminal insulating oxide layer 37 are prepared by a thermal oxidation process. The cell insulating oxide layer 60 covers the sidewalls and bottom walls of the cell trench 36 in the substrate, and the terminal insulating oxide layer 37 covers the substrate. The sidewalls and bottom walls of the bottom terminal trench 35 , the cell insulating oxide layer 60 and the terminal insulating oxide layer 37 are generally silicon dioxide layers. The substrate cell conductive polysilicon 59 is filled in the substrate cell trench 36, and the substrate cell conductive polysilicon 59 is insulated from the semiconductor substrate 58 by the cell insulating oxide layer 60, and the substrate terminal conductive polysilicon 38 is insulated by the terminal The oxide layer 37 is insulated from the semiconductor substrate 58 as shown in FIG. 12 . In specific implementation, before the thermal oxidation process is performed, the substrate first photoresist layer 33 on the front surface of the semiconductor substrate 58 needs to be removed, and the specific process of removing the substrate first photoresist layer 33 is for those skilled in the art known. In addition, the cell insulating oxide layer 60 and the terminal insulating oxide layer 37 can be prepared by the thermal oxidation process commonly used in the technical field, and the process of filling the substrate cell conductive polysilicon 59 in the substrate cell trench 36 is as follows. It is well known to those skilled in the art and will not be repeated here.

Step 3. Perform the implantation and advancement of P-type impurity ions on the front surface of the semiconductor substrate 58 to obtain a P-type body region 39 that traverses the upper part of the semiconductor substrate 58, and the P-type body region 39 is located in the substrate trench above the bottom of the groove;

Specifically, the implantation and advancement of P-type impurity ions can be performed by using the existing common process conditions. Generally, an activation step is required after ion implantation. During activation, the temperature of high-temperature annealing is generally above 800°C, and the specific temperature The conditions can be selected according to needs, which are well known to those skilled in the art, and will not be repeated here. In addition, the type of the P-type impurity ions can be selected as required, and details are not repeated here. The obtained P-type body region 39 covers the upper part of the semiconductor substrate 58 , that is, the P-type body region 39 traverses the upper part of the semiconductor substrate 58 , and the P-type body region 39 is located in the corresponding active region of the semiconductor substrate 58 and in the terminal area. The upper surface of the P-type body region 39 corresponds to the front surface of the semiconductor substrate 58 , and the P-type body region 39 is located above the bottom of the trench in the substrate, as shown in FIG. 14 .

Step 4. Coating a photoresist layer on the front side of the above-mentioned semiconductor substrate 58, and using the second reticle 41 of the substrate to perform photolithography on the coated photoresist layer to obtain a terminal area covered on the semiconductor substrate 58. the second photoresist layer 40 of the substrate;

Specifically, a photoresist layer is coated on the front surface of the above-mentioned semiconductor substrate 58 by using technical means commonly used in the technical field, and the front surface of the semiconductor substrate 58 can be covered by the photoresist layer. The photoresist layer is photoetched by using the second reticle 41 of the substrate to remove the photoresist layer covering the active area of the semiconductor substrate 58 , so that the first substrate covering the terminal area of the semiconductor substrate 58 can be obtained. Two photoresist layers 40 , that is, the second photoresist layer 40 of the substrate can shield the terminal area of the semiconductor substrate 58 , and the active area of the semiconductor substrate 58 is exposed without shielding, as shown in FIG. 15 .

Step 5, using the second photoresist layer 40 of the substrate to implant N-type impurity ions and P impurity ions into the above-mentioned semiconductor substrate 58, and removing the second photoresist layer 40 of the substrate after the implantation, and annealing to obtain a The substrate N+ source doped region 46 and the substrate P-type base region 42 in the active region of the semiconductor substrate 58 are located above the bottom of the cell trench 36 in the substrate, and the substrate P-type base region 42 is located above the bottom of the cell trench 36 in the substrate. The bottom N+ source doped region 46 is located above the substrate P-type base region 42, and the substrate N+ source doped region 46 and the substrate P-type base region 42 are both in contact with the outer sidewalls of the corresponding substrate cell trenches 36;

Specifically, the order of N-type impurity ion implantation and P-type impurity ion implantation can be selected as required, that is, N-type impurity ion implantation can be performed first, and then P-type impurity ion implantation can be performed, or P-type impurity ion implantation can be performed first, Next, N-type impurity ion implantation is performed. When the specific implantation sequence is different, the corresponding process conditions of N-type impurity ion implantation and P-type impurity ion implantation are different, which are well known to those skilled in the art and will not be repeated here. In the embodiment of the present invention, N-type impurity ions and P-type impurity ions are implanted through the window of the second photoresist layer 40 of the substrate. After the implantation, the second photoresist layer 40 of the substrate needs to be implanted from The semiconductor substrate 58 is removed to perform the subsequent annealing activation process. The temperature during annealing is generally above 800° C., and the specific temperature conditions are well known to those skilled in the art, and will not be repeated here.

The following takes the process of first performing P-type impurity ion implantation and then performing N-type impurity ions as an example for specific description, specifically:

During the P-type impurity ion implantation, the second photoresist layer 40 of the substrate is used to shield the terminal region corresponding to the semiconductor substrate 58, so that the P-type impurity ions can only be implanted in the active region of the semiconductor substrate 58, Therefore, the substrate P-type base region 42 located in the active region can be obtained, that is, the substrate P-type base region 42 can be obtained by implanting and advancing P-type impurity ions in the P-type body region 39 of the active region, thereby obtaining the substrate P-type base region 42 . The doping concentration of the P-type base region 42 of the substrate is greater than the doping concentration of the P-type body region 39, that is, the P-type impurity implanted in the active region of the semiconductor substrate 58 and the P-type body region in the active region are obtained as described above. 39 can obtain the P-type base region 42 of the substrate, and at the same time, after being shielded by the second photoresist layer 40 of the substrate, the P-type body region 39 in the semiconductor substrate 58 corresponding to the termination region remains unchanged.

Specifically, during the N-type impurity ion implantation, the second photoresist layer 40 of the substrate is still used to shield the terminal region, so that the N-type impurity ions can only be implanted in the active region. The technical process is well known to those skilled in the art and will not be repeated here. After the N-type impurity ion implantation is performed, the substrate N+ source doping region 46 can be obtained above the substrate P-type base region 42, and the substrate N+ source doping region 46 is parallel to the substrate P-type base region 42. , the substrate N+ source doping region 46 and the substrate P-type base region 42 are in contact with the outer walls of the corresponding adjacent substrate cell trenches 36, and the substrate N+ source doping region 46 is in contact with the substrate cell trench 36. The notches correspond, as shown in Figure 16.

In step 6, a dielectric layer is deposited on the front surface of the above-mentioned semiconductor substrate 58 to obtain a substrate dielectric layer 53 covering the front surface of the semiconductor substrate 58; a third photoresist layer of the substrate is coated on the substrate dielectric layer 53 43, using the third substrate mask 44 to perform photolithography on the third substrate photoresist layer 43 to obtain the substrate third photoresist layer window 45 penetrating the substrate third photoresist layer 43;

Specifically, the second photoresist layer 40 of the substrate is removed by using technical means commonly used in the technical field, and a dielectric layer is deposited after the second photoresist layer 40 of the substrate is removed, so as to obtain a surface covering the front surface of the semiconductor substrate 58 . The substrate dielectric layer 53, the substrate dielectric layer 53 may be a silicon dioxide layer. After the substrate dielectric layer 53 is obtained, the third substrate photoresist layer 43 is obtained by coating the substrate dielectric layer 53, and the third substrate photoresist layer 43 is photolithographically performed by using the substrate third mask 44 , the window 45 of the third photoresist layer of the substrate is obtained, the window 45 of the third photoresist layer of the substrate passes through the third photoresist layer 43 of the substrate, and the window 45 of the third photoresist layer of the substrate is located in the active directly above the area, as shown in Figure 17.

Step 7. The substrate dielectric layer 53 is etched by using the third substrate photoresist layer 43 and the substrate third photoresist layer window 45 to obtain the through-substrate dielectric layer 53 and the substrate N+ source doping The dielectric contact hole 48 of the region 46, the substrate N+ source doped region 46 can form the required substrate N+ source region 47 through the dielectric contact hole 48;

Specifically, the substrate dielectric layer 53 is etched by using the third photoresist layer 43 of the substrate and the window 45 of the third photoresist layer of the substrate to obtain a medium corresponding to the window 45 of the third photoresist layer of the substrate. The contact hole 48 , the dielectric contact hole 48 penetrates through the substrate dielectric layer 53 and the substrate N+ source doped region 46 . On the cross section of the power semiconductor device, after the dielectric contact hole 48 penetrates the substrate N+ source doped region 46, the substrate N+ source region 47 located on both sides of the substrate cell trench 36 is obtained, and the substrate N+ source region 47 is obtained. Contacts are made with the outer sidewalls of the corresponding adjacent substrate cell trenches 36 as shown in FIG. 18 .

Step 8. Remove the third photoresist layer 43 of the above-mentioned substrate, and deposit a metal layer on the above-mentioned substrate dielectric layer 53 to obtain a front-side metal layer of the substrate, and the front-side metal layer of the substrate covers the substrate dielectric layer 53 and filled in the dielectric contact hole 48, the substrate front metal layer filled in the dielectric contact hole 48 is in ohmic contact with the substrate N+ source region 47 and the substrate P-type base region 42;

Specifically, the third photoresist layer 43 of the substrate is removed by using technical means commonly used in the technical field, and then the metal layer is deposited by using technical means commonly used in the technical field. The metal layer can be made of commonly used materials. A selection is required and will not be repeated here. The substrate front metal layer covers the substrate dielectric layer 53 and is filled in the dielectric contact holes 48. After the substrate front metal layer is filled in the dielectric contact holes 48, the substrate front metal layer can interact with the substrate N+ source region 47, The substrate P-type base region 42 is in ohmic contact.

Step 9, coating the fourth substrate photoresist layer 50 on the above-mentioned substrate front metal layer, and using the substrate fourth mask 49 to perform photolithography on the substrate fourth photoresist layer 50 to obtain a through substrate The substrate fourth photoresist layer window 52 of the fourth photoresist layer 50 uses the substrate fourth photoresist layer 50 and the substrate fourth photoresist layer window 52 to etch the front metal layer of the substrate, In order to obtain the substrate metal separation hole 62 penetrating the front metal layer of the substrate, and the substrate metal separation hole 62 can be used to separate the substrate front metal layer to obtain the substrate cell front metal layer 61 and the substrate terminal front metal layer 51, The front metal layer 61 of the substrate cell is in ohmic contact with the substrate N+ source region 47 and the substrate P-type base region 42;

Specifically, the fourth substrate photoresist layer 50 is obtained by coating the metal layer on the front side of the substrate, and the fourth substrate photoresist layer 50 is photoetched by using the fourth substrate mask 49 to obtain the substrate fourth photoresist layer 50. Four photoresist layer windows 52, the fourth photoresist layer window 52 of the substrate is located above the termination area. When using the fourth substrate photoresist layer 50 and the fourth substrate photoresist layer window 52 to etch the metal on the front side of the substrate, the substrate metal separation hole 62 located above the terminal area can be obtained, and the substrate metal separation hole 62 can be obtained. The hole 62 penetrates through the front metal layer of the substrate, so that the front metal layer of the substrate can be separated to obtain the front metal layer 61 of the substrate cell and the front metal layer 51 of the substrate terminal. The front metal layer 51 of the substrate terminal passes through the substrate metal separation hole 62 It is separated from the front metal layer 61 of the substrate cell, the front metal layer 51 of the substrate terminal is located in the terminal area, and the front metal layer 61 of the substrate cell is in ohmic contact with the substrate N+ source region 47 and the substrate P-type base region 42. As shown in Figure 19.

Step 10, removing the above-mentioned fourth photoresist layer 50 of the substrate and depositing a passivation layer to obtain a front-side passivation layer covering the front-side metal layer 61 of the substrate cell and the front-side metal layer 51 of the substrate terminal 54, and the substrate front passivation layer 54 is also filled in the substrate metal separation hole 62;

Specifically, the fourth photoresist layer 50 of the substrate is removed by using technical means commonly used in the technical field, and a passivation layer is deposited by using technical means commonly used in the technical field. The material of the passivation layer can be silicon nitride, The substrate front passivation layer 54 covers the substrate cell front metal layer 61 and the substrate terminal front metal layer 51 , and the substrate front passivation layer 54 is also filled in the substrate metal separation holes 62 .

Step 11: Coat the fifth substrate photoresist layer 55 on the above-mentioned substrate front passivation layer 54, use the substrate fifth mask layer 56 to perform photolithography on the substrate fifth photoresist layer 55, and use The fifth photoresist layer 55 of the substrate after photoetching etches the front surface passivation layer 54 of the substrate to obtain a substrate source pad hole 57 penetrating the front surface passivation layer 54 of the substrate, and passes through the substrate source electrode pad hole 57. The pad hole 57 can expose the front metal layer 61 of the substrate cell corresponding to the substrate source pad hole 57;

Specifically, the fifth photoresist layer 55 of the substrate is obtained by coating the front surface passivation layer 54 of the substrate, and the fifth photoresist layer 55 of the substrate is photoetched by using the fifth mask 56 of the substrate, and then the substrate is subjected to photolithography. The bottom front passivation layer 54 is etched to obtain the substrate source pad hole 57, the substrate source pad hole 57 passes through the substrate front passivation layer 54, and the substrate source pad hole 57 is located in the active region Above, through the substrate source pad hole 57, the front metal layer 61 of the substrate cell corresponding to the substrate source pad hole 57 can be exposed, as shown in FIG. The source electrode of the semiconductor device is formed after the layer 61 is drawn out, and the specific process of forming the source electrode is well known to those skilled in the art.

Step 12 , removing the above-mentioned fifth photoresist layer 55 of the substrate, and performing a required backside process on the backside of the semiconductor substrate 58 .

Specifically, the fifth photoresist layer 55 of the substrate is removed by technical means commonly used in the art to complete the required front-side process, and then the required back-side process is performed on the backside of the semiconductor substrate 58 as required. Different power semiconductor devices can be obtained, such as obtaining a MOSFET device or an IGBT device, and the specific backside process and backside structure are well known to those skilled in the art, and will not be repeated here.

It can be seen from the above description that the substrate terminal trench 35 is arranged in the terminal region of the semiconductor substrate 58, and the terminal insulating oxide layer 37 and the substrate terminal conductive polysilicon 38 are arranged in the substrate terminal trench 35. P-type impurity ion implantation is performed on the front side to obtain a P-type body region 39, and the P-type body region 39 of the terminal region cooperates with the substrate terminal trench 35 to form the required terminal region structure, and it is not necessary to obtain the P-type body region 39. Compared with the existing technology, the reticle can make the trench type power semiconductor device use one less reticle when preparing the front structure, which effectively reduces the manufacturing cost of the power semiconductor device.

The active region of the semiconductor substrate 58 can be implanted with N-type impurity ions and P-type impurity ions by using the second photoresist layer 40 of the substrate. After the second photoresist layer 40 of the substrate is removed and activated by annealing, the obtained The substrate N+ source doping region 46 and the substrate P-type base region 42 can reduce the use of masks under the condition of ensuring the doping concentration of the substrate P-type base region 42, thereby further reducing the cost. Using the substrate P-type base region 42 in the active region can realize the adjustment of the P-type doping concentration in the active region, which ensures the breakdown characteristics of the terminal region of the prepared power semiconductor device and the conduction of the active region. The whole process is compatible with the existing process, safe and reliable.

In the embodiment of the present invention, the P-type doping concentration in the active region should be higher to prevent the base region from breaking through under high voltage. When the P-type doping concentration in the active region is low, the high voltage The P-type base region 42 will be completely depleted, and the electric field will extend to the substrate cell front-side metal layer 61 or the N+ source region 47 filled in the dielectric contact hole 48, so that punch-through occurs. When the substrate P-type base region 42 is prepared in the active region, the withstand voltage requirement of the active region can be met, that is, the breakdown characteristics of the terminal region of the prepared power semiconductor device and the conduction characteristics of the active region can be ensured . The specific conditions of the P-type doping concentration in the active region, that is, the process and method of adjusting the P-type doping concentration in the active region are well known to those skilled in the art, and will not be repeated here.

Claims (5)

1. a preparation method of a low-cost trench type power semiconductor device, is characterized in that, described preparation method comprises the steps: Step 1. Provide a semiconductor substrate with a first conductivity type, and perform trench etching on the semiconductor substrate to obtain a desired substrate trench, where the substrate trench includes a liner located in the active region. a bottom cell trench and a substrate termination trench located in the termination region; Step 2, performing an oxide layer growth process in the above-mentioned substrate trench to obtain a cell insulating oxide layer covering the inner wall of the substrate cell trench and a terminal insulating oxide layer covering the inner wall of the substrate terminal trench; The substrate cell trench of the cell insulating oxide layer is filled with conductive polysilicon of the substrate cell, and at the same time, the substrate terminal conductive polysilicon is filled in the substrate terminal trench where the terminal insulating oxide layer is grown; Step 3. Perform implantation and advancement of impurity ions of the second conductivity type on the front surface of the semiconductor substrate to obtain a second conductivity type body region traversing the upper part of the semiconductor substrate, and the second conductivity type body region is located in the substrate. Above the bottom of the bottom groove; Step 4: Coating a photoresist layer on the front side of the above-mentioned semiconductor substrate, and using the second mask of the substrate to perform photolithography on the coated photoresist layer to obtain a substrate covering the terminal area of the semiconductor substrate a second photoresist layer; Step 5, using the second photoresist layer of the substrate to implant the impurity ions of the first conductivity type and the impurity ions of the second conductivity type into the semiconductor substrate, and remove the second photoresist layer of the substrate after the implantation, and after annealing The first conductive type source doped region of the substrate and the second conductive type base region of the substrate located in the active region of the semiconductor substrate are obtained, and the second conductive type base region of the substrate is located at the bottom of the cell trench groove of the substrate Above, the first conductive type source doped region of the substrate is located above the second conductive type base region of the substrate, and the first conductive type source doped region of the substrate and the second conductive type base region of the substrate are both connected to the corresponding substrate The outer sidewall of the cell trench contacts; In step 6, a dielectric layer is deposited on the front surface of the above-mentioned semiconductor substrate to obtain a substrate dielectric layer covering the front surface of the semiconductor substrate; the third photoresist layer of the substrate is coated on the substrate dielectric layer, and the The three masks perform photolithography on the third photoresist layer of the substrate to obtain a window of the third photoresist layer of the substrate passing through the third photoresist layer of the substrate; Step 7: Etching the substrate dielectric layer by using the above-mentioned third substrate photoresist layer and the substrate third photoresist layer window to obtain through the substrate dielectric layer and the first conductive type source doped region of the substrate A medium contact hole is formed, and the first conductive type source doped region of the substrate can form the required first conductive type source region of the substrate through the medium contact hole; Step 8: Remove the third photoresist layer of the above-mentioned substrate, and deposit a metal layer on the above-mentioned substrate dielectric layer to obtain a front-side metal layer of the substrate, and the front-side metal layer of the substrate is covered on the substrate dielectric layer and is Filled in the dielectric contact hole, the front metal layer of the substrate filled in the dielectric contact hole is in ohmic contact with the source region of the first conductivity type of the substrate and the base region of the second conductivity type of the substrate; Step 9: Coating the fourth photoresist layer of the substrate on the metal layer on the front side of the substrate, and using the fourth mask of the substrate to perform photolithography on the fourth photoresist layer of the substrate to obtain the fourth photoresist penetrating the substrate. The fourth photoresist layer window of the substrate of the resist layer is used to etch the metal layer on the front side of the substrate by using the fourth photoresist layer of the substrate and the window of the fourth photoresist layer of the substrate, so as to obtain a metal layer through the front side of the substrate The substrate metal separation hole of the layer, and the substrate metal separation hole can be used to separate the substrate front metal layer to obtain the substrate cell front metal layer and the substrate terminal front metal layer, and the substrate cell front metal layer and the lining the bottom first conductive type source region and the substrate second conductive type base region are in ohmic contact; Step 10, removing the above-mentioned fourth photoresist layer of the substrate and depositing a passivation layer to obtain a front-side passivation layer covering the front-side metal layer of the substrate cell and the front-side metal layer of the substrate terminal, and all The front passivation layer of the substrate is also filled in the metal separation hole of the substrate; Step 11, coat the fifth photoresist layer of the substrate on the front passivation layer of the substrate, use the fifth mask layer of the substrate to perform photolithography on the fifth photoresist layer of the substrate, and use the photoetched photoresist layer. The fifth photoresist layer of the substrate etches the front passivation layer of the substrate to obtain a substrate source pad hole penetrating the front passivation layer of the substrate. The front metal layer of the substrate cell corresponding to the substrate source pad hole is exposed; Step 12, removing the above-mentioned fifth photoresist layer of the substrate, and performing a required backside process on the backside of the semiconductor substrate. 2 . The method for preparing a low-cost trench-type power semiconductor device according to claim 1 , wherein in step 1, a first photoresist layer of the substrate is coated on the front surface of the semiconductor substrate, using The first mask of the substrate performs photolithography on the first photoresist layer of the substrate, so as to obtain a window of the first photoresist layer of the substrate passing through the first photoresist layer of the substrate, and the first photoresist layer of the substrate is used. And after the front surface of the semiconductor substrate is etched by the first photoresist layer window of the substrate, the required substrate trench can be obtained. 3 . The method for fabricating a low-cost trench-type power semiconductor device according to claim 1 , wherein the material of the semiconductor substrate comprises silicon. 4 . 4. The method for preparing a low-cost trench-type power semiconductor device according to claim 1, wherein in step 2, the cell insulating oxide layer and the terminal insulating oxide layer are the same process step layer, and the cell insulating oxide layer is the same process step layer. The layer and the terminal insulating oxide layer are silicon dioxide layers. 5 . The method for fabricating a low-cost trench-type power semiconductor device according to claim 1 , wherein the doping concentration of the second conductive type base region of the substrate is greater than that of the second conductive type body region. 6 . concentration.