CN110060720A - The transistor latch prevention system of dynamic RAM - Google Patents
The transistor latch prevention system of dynamic RAM Download PDFInfo
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- CN110060720A CN110060720A CN201910274706.XA CN201910274706A CN110060720A CN 110060720 A CN110060720 A CN 110060720A CN 201910274706 A CN201910274706 A CN 201910274706A CN 110060720 A CN110060720 A CN 110060720A
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
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Abstract
The invention discloses a kind of transistor latch prevention systems of dynamic RAM, including electrification circuit, first powered on drive and the second powered on drive, the electrification circuit generates multiple power on signal, including the first power on signal, second power on signal and third power on signal, first powered on drive drives first voltage signal to the trap end of transistor, as one or more power on signal, second powered on drive sends second voltage signal to the drain electrode of transistor, as one or more power on signal, wherein first power on signal is greater than the second power on signal.By above-mentioned, the transistor latch prevention system of dynamic RAM provided by the invention, ensure that first voltage signal is equal to or more than second voltage signal (including using in the powering on of respective memory, standby, activation, when power-off) at any time, to prevent the latch-up of transistor.
Description
Technical field
The present invention relates to the technical fields of dynamic RAM, more particularly to a kind of crystal of dynamic RAM
Stopcock locks prevention system.
Background technique
There is a large amount of transistor in dynamic RAM (DRAM), such as complementary metal-oxide semiconductor (MOS) (CMOS) is brilliant
Body Manifold technology may meet with latch-up.CMOS integrated circuit has n-channel metal-oxide semiconductor (MOS) (NMOS) transistor and p
Channel mos (PMOS) transistor.NMOS and PMOS integrated circuit there are four terminal (grade), including leakage, source,
Grid (door) and body.Body end is otherwise referred to as trap or body end, can add bias.For example, positive bias voltage may be added to PMOS crystalline substance
The N-shaped body of body pipe, negative bias voltage may be added to the p-type body of NMOS transistor.These bias voltages increase the threshold of transistor
Threshold voltage, to reduce the leakage current of transistor.Leakage current is reduced to reduce power consumption.
In common CMOS integrated circuit transistor structure, doped semiconductor region forms a pair of of parasitic bipolar crystal
Pipe.Bipolar transistor existing for parasitism makes CMOS transistor vulnerable to a kind of influence of bad phenomenon for being known as latch-up.It is fastening with a bolt or latch
During locking effect, the feedback path in parasitic bipolar transistor causes CMOS transistor function abnormal.In severe cases,
Latch-up can permanent damages CMOS transistor and corresponding device.In the integrated circuit using body bias, latch problem is outstanding
It is serious.Accordingly, it is desirable to provide a kind of memory, it can prevent the latch-up of transistor.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of transistor latch prevention system of dynamic RAM,
Ensure first voltage signal be equal to or more than at any time second voltage signal (including the powering on of respective memory, to
Machine, activation use, when power-off), to prevent the latch-up of transistor.
In order to solve the above technical problems, one technical scheme adopted by the invention is that: provide a kind of dynamic random storage
The transistor latch prevention system of device, including electrification circuit, the first powered on drive and the second powered on drive, described is upper
The multiple power on signal of circuit generation, including the first power on signal, the second power on signal and third power on signal, described first
Powered on drive drives first voltage signal to the trap end of transistor, as one or more power on signal, described second
Powered on drive sends second voltage signal to the drain electrode of transistor, as one or more power on signal, wherein described
First power on signal is greater than the second power on signal.
In a preferred embodiment of the present invention, first power on signal by memory the first internal power source voltage
Vdd1 is generated；Second power on signal is generated by the second internal power source voltage Vdd2 of the first power on signal and memory；
The third power on signal is generated by the second internal power source voltage Vdd2 of the second power on signal and memory.
In a preferred embodiment of the present invention, the first internal power source voltage Vdd1 is greater than the second internal electric source electricity
Press Vdd2.
In a preferred embodiment of the present invention, first powered on drive include clamp circuit, the first phase inverter,
First PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor and first resistor, it is described
Clamp circuit inputs multiple power on signal, deep-sleep signal and outer power voltage, and it is anti-to first to export a clamp signal
Phase device, the output of first phase inverter is enter into the grid end of the first PMOS transistor and the second NMOS transistor, described
The first PMOS transistor, the first NMOS transistor and the second PMOS transistor using serial connection, the first resistor connects
It is connected to the grid end and outer power voltage of the first NMOS transistor, second PMOS transistor is connected to the second internal electric source
Voltage Vdd2 and drain terminal are connected to the drain terminal of the first PMOS transistor, first PMOS transistor and the second PMOS transistor
Drain terminal provide first voltage signal Vccp.
In a preferred embodiment of the present invention, there are two branches, including the first branch and second for the clamp circuit
Branch；First branch is by the second phase inverter, the first NAND gate, third phase inverter, the 4th phase inverter and the 5th phase inverter
Serial connection；Second branch is by the second NAND gate, hex inverter, the 7th phase inverter, the 8th phase inverter and one
NMOS transistor serial connection.
In a preferred embodiment of the present invention, second powered on drive includes voltage detector, the 9th reverse phase
Device, the tenth phase inverter, the 11st phase inverter, third NAND gate and third PMOS transistor, the output of the voltage detector
It is connected to the input of the 9th phase inverter, the 9th phase inverter is output to first input of third NAND gate, and described the
Ten phase inverters are output to second input of third NAND gate, and the output of the third NAND gate is connected to the grid of the 3rd PMOS
End, the drain terminal of the 3rd PMOS are connected to the second internal power source voltage Vdd2, and the source of the third PMOS transistor generates the
Two voltage signal Vcca, second voltage signal Vcca feed back to voltage detector.
The beneficial effects of the present invention are: the transistor latch prevention system of dynamic RAM of the invention, it is ensured that the
One voltage signal is equal to or more than second voltage signal (including in the powering on of respective memory, standby, activation at any time
Using, power-off when), to prevent the latch-up of transistor.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, in which:
Fig. 1 illustrates the memory block diagram disclosed in the present application with electrification circuit and clamp circuit；
Fig. 2 illustrates the outwardly and inwardly voltage pattern of the memory of the application；
Fig. 3 illustrates the block diagram of the electrification circuit of the application；
Fig. 4 illustrates the chart of the external voltage of the memory of the application, builtin voltage and upper piezoelectric voltage；
Fig. 5 illustrates electric drive circuit on the Vccp of the power up phase for providing memory of the application；
Fig. 6 illustrates the clamp circuit of the application；
Fig. 7 illustrates the external voltage and supply voltage schematic diagram of the memory of the application；
Fig. 8 illustrates electric drive circuit on the Vcca for providing memory power up phase of the application；
Fig. 9 illustrates another figure of the external voltage of the memory of the application, builtin voltage and upper piezoelectric voltage.
Specific embodiment
The technical scheme in the embodiments of the invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's all other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
The embodiment of the present invention includes:
A kind of transistor latch prevention system of dynamic RAM, including electrification circuit, the first powered on drive and
Two powered on drive, the electrification circuit generate multiple power on signal, including the first power on signal, the second power on signal and the
Three power on signal, first powered on drive drive first voltage signal to the trap end of transistor, as one or more
A power on signal, second powered on drive send second voltage signal to the drain electrode of transistor, as one or more
A power on signal, wherein first power on signal is greater than the second power on signal.
Among the above, first power on signal is generated by the first internal power source voltage Vdd1 of memory；Described
Two power on signal are generated by the second internal power source voltage Vdd2 of the first power on signal and memory；The third power on signal
It is generated by the second internal power source voltage Vdd2 of the second power on signal and memory.Wherein, first internal power source voltage
Vdd1 is greater than the second internal power source voltage Vdd2.
Further, first powered on drive include clamp circuit, the first phase inverter, the first PMOS transistor,
Second PMOS transistor, the first NMOS transistor, the second NMOS transistor and first resistor, the clamp circuit input are multiple
It is anti-to the first phase inverter, described first to export a clamp signal for power on signal, deep-sleep signal and outer power voltage
The output of phase device is enter into the grid end of the first PMOS transistor and the second NMOS transistor, first PMOS transistor,
Using serial connection, the first resistor is connected to the first NMOS transistor for first NMOS transistor and the second PMOS transistor
Grid end and outer power voltage, second PMOS transistor be connected to the second internal power source voltage Vdd2 and connected with drain terminal
To the drain terminal of the first PMOS transistor, the drain terminal of first PMOS transistor and the second PMOS transistor provides first voltage
Signal Vccp.
Wherein, there are two branches, including the first branch and the second branch for the clamp circuit；First branch by
What the second phase inverter, the first NAND gate, third phase inverter, the 4th phase inverter and the 5th phase inverter were connected in series；Described second
Branch is by the second NAND gate, hex inverter, the 7th phase inverter, the 8th phase inverter and a NMOS transistor serial connection.
Further, second powered on drive include voltage detector, the 9th phase inverter, the tenth phase inverter,
11st phase inverter, third NAND gate and third PMOS transistor, the output of the voltage detector are connected to the 9th reverse phase
The input of device, the 9th phase inverter are output to first input of third NAND gate, and the tenth phase inverter is output to
Second input of third NAND gate, the output of the third NAND gate are connected to the grid end of the 3rd PMOS, the 3rd PMOS's
Drain terminal is connected to the second internal power source voltage Vdd2, and the source of the third PMOS transistor generates second voltage signal
Vcca, second voltage signal Vcca feed back to voltage detector.
Wherein the source of the 4th NMOS transistor is connected to second voltage signal Vcca, and drain terminal is connected to ground.Described
Three power on signal are input into the first NAND gate, wherein the second power on signal is input into the second NAND gate, wherein the first branch
Export clamp signal.
It illustrates:
Fig. 1 illustrates the memory block diagram that the present invention has storage sub-block.Memory of the invention includes a command block 10, is deposited
Store up core 12, analog circuit 19, DQ (input/output) 14, reading and writing data channel 22 and 24.Command block 10 includes order and ground
The input of location.Storing core 12 includes 8 block storages: memory block 0,1,2,3,4,5,6,7.Each memory block is divided into upper half sub-block
With lower half sub-block.0-7 memory block is arranged by 4x4 array.The upper half sub-block of 0-7 memory block is arranged in the top half of 4x4 array,
That is the 1st row and the 2nd row of array.The lower half sub-block of 0-7 memory block is arranged in the lower half portion of 4x4 array, i.e. the 3rd row of array
With the 4th row.Reading and writing data channel channel 22 is routed between the 1st row of 4x4 array and the 2nd row, connects the upper half of memory block 0-7
A sub-block is to DQ block 14.Reading and writing data channel channel 24 is routed between the 3rd row of 4x4 array and the 4th row, is connected to memory block
The lower half sub-block of 0-7 is to DQ block 14.Analog circuit 19 is distributed in the centre of storage core, and analog circuit 19 includes powering on electricity
Road, clamp circuit and other circuits not shown, for example generate charge pump circuit, reference circuit, the bleeder circuit of high pressure
Deng.Clamp circuit 20 is other than being distributed in analog circuit, and there is also part clamp circuits at the edge of command block 10 and DQ block.
The latch prevention system of PMOS transistor can be integrated into memory or independently of memory.The latch prevention
System includes electrification circuit, Vccp powered on drive and Vcca powered on drive.The electrification circuit generates multiple power on signal and exists
It is used in the memory.As the function of one or more power on signal, Vccp powered on drive drives Vccp voltage signal
To the trap end of transistor.As the function of one or more power on signal, Vcca, which is powered on, drives device driving Vcca voltage signal to crystalline substance
The drain terminal of body pipe.Vccp voltage be equal to or more than at any time Vcca voltage signal (including the powering on of respective memory,
Standby, activation uses, when power-off), to prevent latch-up.
In embodiment, latch prevention system can integrate in memory.In this integrate, memory is further wrapped
Include clamp circuit 20 and the electrification circuit 22 for memory power supply.Clamp circuit 20 can be located at the perimeter of memory.It should
The purposes of clamp circuit 20 is clamper (or preliminary filling) Vccp to Vdd2 in respective memory power up, and Vcca is less than Vccp.
Since the respective power supply line of Vccp and Vcca is distributed in whole memory, clamp circuit 20 can be placed on respective storage
The corner and edge of device ensure that Vccp and Vcca are uniform preliminary filling in memory to reinforce clamper (i.e. preliminary filling).
Vccp powered on drive and Vcca powered on drive (not shown) can be located near clamp circuit 20.
Electrification circuit 22 can be located in analog circuit 19 (usually in the immediate vicinity of memory).Electrification circuit 22 uses
Builtin voltage Vdd1 and Vdd2.In power up, a low to high signal can be generated to open the circuit of some memories
With deposit element.For example, the other assemblies of latch and memory can be corresponding when internal electric source reaches defined state
Ground powers on.
Electrification circuit block is controlled by builtin voltage Vdd1 and Vdd2, and wherein Vdd1 is greater than Vdd2.As previously mentioned, builtin voltage
Vdd1 and vdd2 is to be generated by external power supply XVdd1 and XVdd2 by power gating.During powering on, XVdd1 and XVdd2 are
It can climb.After having crossed certain threshold voltage in power gating, builtin voltage Vdd1 follows XVdd1, Vdd2 to follow XVdd2.
During climbing, vdd1 and vdd2 reach certain voltage it is horizontal after, generate power supply signal Pwrup1, Pwrup2 and
Pwrup3.These power supply signals be mainly used for memory initialization (such as: initialization latch or is deposited to scheduled state
Certain signals are initialized as defined state by memory design or code requirement).Power on signal is in whole memory (entire core
Piece) in transmission: including reading and writing data channel, reading and writing data latchs, any central passage, order and test logic etc..
Fig. 2 illustrates the outwardly and inwardly voltage pattern of the memory of the application.When XVdd1 rises from a lower level
When, the XVdd1 power gating for being converted to Vdd1 is constantly in closed state, the threshold value electricity until reaching the power gating device
Pressure value, Vdd1 starts to follow XVdd1 at this time.Equally, XVdd2 is also to be promoted from low level, and XVdd2 is converted to the power supply of Vdd2
Gating device is constantly in closed state, and the threshold voltage until reaching the power gating device, Vdd2 starts and follows at this time
XVdd2.In this direction, power gating device is mainly realized by PMOS transistor, but other kinds of crystalline substance also can be used
Body pipe.Therefore, for threshold voltage according to used transistor types, the value for opening power gating device may be different.
Fig. 3 illustrates the block diagram of an electrification circuit disclosed in the present application.Electrification circuit 219 includes pwrup1 generator
320, pwrup2 generator 322, pwrup3 generator 324 and buffer 330.Pwrup1 generator 320 receive voltage Vdd1 and
DPD signal generates Pwrup1 signal as input.When memory powers on, DPD signal is low.It is raw that it can be used as 320-324
The enabling and disabling signal grown up to be a useful person.Pwrup2 generator 322 receives Pwrup1 signal, and voltage Vdd2 and DPD signal are used as input,
Pwrup2 signal is generated as output.Pwrup3 generator 324 receives Pwrup2 signal, and voltage Vdd2 and DPD signal are as defeated
Enter, generates Pwrup3 signal as output.Pwrup1 signal can be used for local voltage detector, it is thus possible to not need to input
To buffer 330.Pwrup2 and Pwrup3 signal is input to buffer 330, is partly led so that as needed or requirement driving is various
Volume elements part and memory.For example, Pwrup2 signal can be used for driving the clamp circuit 326 of the voltage detector sum of memory.
Pwrup3 signal can be used for driving data latches, command logic, test logic, clamp circuit, the builtin voltage of memory to drive
Dynamic device and pump oscillator 328.
Fig. 4 illustrates the external voltage of memory disclosed in the present application, builtin voltage power up figure.As previously mentioned, working as
When certain trigger events occur, Pwrup1 signal, Pwrup2 signal and the Pwrup3 signal of memory are since low voltage level
It is transformed into high voltage.The high-voltage value of Pwrup1 signal is Vdd1.The high-voltage value of Pwrup2 and Pwrup3 signal is Vdd2.Therefore work as
When high voltage, Pwrup2 and Pwrup3 signal voltage value having the same, but while converting from low to high, may difference at any time
And it is different, vice versa.
For Pwrup1 signal, when Vdd1 reaches certain threshold value, Pwrup1 signal is by low-voltage level conversion to high electricity
Voltage level.When Pwrup1 signal is that high and Vdd2 voltage reaches certain threshold value, pwrup2 signal is got higher by low.Work as Pwrup2
When signal is high and Vdd2 voltage reaches certain threshold value, Pwrup3 signal is transformed into high RST by low signal.For example, Pwrup2 signal
The time delay for being transformed into high voltage level with Pwrup3 signal is about 100 microseconds.According to different designs, delay can change
Become, to meet any necessary specification of memory.
Fig. 5 illustrates disclosed in the present application for operating the Vccp powered on drive of memory power up phase.Vccp is powered on
Driver includes clamp circuit 340, phase inverter 342, PMOS P1, PMOS P2, NMOS N1, NMOS N2 and resistance R1.Clamper
Circuit 340 receives following signals as input: XVdd2, DPD, Pwrup2, Pwrup3 simultaneously generate a ClampB signal as defeated
Out.ClampB signal is input to phase inverter 342.Phase inverter 342 can be powered by external voltage XVdd2.The ClampB signal of reverse phase
It is input to the door of PMOS P1 and NMOS N2.PMOS P1, NMOS N1 and NMOS N2 are serial connections.The grid of PMOS P2
It is connected to the source of PMOS P1.The drain terminal of PMOS P1 and P2 are connected to Vccp signal.The source of PMOS P2 is connected to voltage
Vdd2.PMOS P2 drives Vccp from Vdd2 when powering on.PMOS P2 is the PMOS device of a kind of high voltage, Low threshold.PMOS
The n trap of P2 may be coupled on Vccp signal.The grid of NMOS N1 are connected with resistance R1, the other end and external voltage of resistance R1
XVdd1 is connected.
Fig. 6 illustrates clamp circuit disclosed in the present application.Clamp circuit 340 can be by phase inverter 352,356-360,372-
390, NAND gate 354,362 and NMOS N4 is formed.Phase inverter 352,356-360,372-390 and NAND gate 354 and 362 are by outer
Portion voltage XVdd2 power supply.DPD signal is input to phase inverter 352.The output of phase inverter 352 is input into NAND gate 354 and 362.
Pwrup3 signal is input into another input terminal of NAND gate 354.Pwrup2 signal is input into another of NAND gate 362
Input terminal.The output of NAND gate 354 is input into the phase inverter 356,358 and 360 of serial connection.The output of phase inverter 360 produces
Raw ClampB signal.The output of NAND gate 362 is also input to the phase inverter 372,382 and 390 of serial connection.Phase inverter 390
Output generate a PEN signal, and be added to the grid of NMOS N4.Vcca signal is added to the source of NMOS N4, the leakage of NMOS N4
Pole is connected to ground.There is the people of common skill to be appreciated that the source electrode and drain electrode of each transistor of the disclosure connects in this respect
Connecing can configure according to the transistor and transistor of different circuits and be exchanged.
Fig. 7 is the memory external voltage of the disclosure and powers on voltage curve.Initially, DPD signal, Pwrup2 signal and
Pwrup3 signal is all low.On a memory during electricity, external voltage XVdd2 climbs.As supply voltage climbs, work as XVdd2
When reaching threshold value, the transistor of phase inverter 390 will be opened.Then phase inverter 390 will drive PEN signal.Once PEN signal reaches
When the threshold value of NMOS N4, NMOS N4 is opened and is driven so that Vcca signal is low.Once Pwrup2 signal becomes high, it will triggering
Pen signal becomes low.One low Pen signal will close NMOS N4, so that Vcca signal is driven to height.When Pwrup 3 believes
Number for it is low when, then ClampB signal be it is low.When Pwrup3 signal is converted into high, ClampB signal translates into height.
Fig. 8 illustrates the disclosure and provides the Vcca powered on drive of power up phase.The Vcca powered on drive includes Vcca
Detector 400, phase inverter 402,406,408, NAND gate 404 and PMOS P3.Vcca detector 400 receives following input:
Pwrup1 signal, Pwrup2 signal, Vref_cca signal, Vcca signal.Vcca detector 400 generates an Ensb_cca letter
Number, it is input to phase inverter 402.The output of phase inverter 402 is input to NAND gate 404.Offb_cca signal incoming serial is connected
Phase inverter 406 and 408.The output of phase inverter 408 is input into another input of NAND gate 404.The output of NAND gate 404
It is input into the grid of PMOS P3.Voltage Vdd2 is connected to the drain electrode of PMOS P3.Vcca signal is added to the source of PMOS P3, and
Feed back to Vcca detector 400.Vcca detector can adjust the voltage of Vcca by feeding back.PMOS P3 is a kind of standard
The PMOS device of voltage, level threshold value.The n trap of PMOS P3 is connected with Vdd2.
Fig. 9 illustrates another figure of the external voltage of disclosure memory, builtin voltage and supply voltage.Memory
Voltage vcc p and Vcca are external voltage XVdd1 and XVdd2, produce in builtin voltage Vdd1 and Vdd2 and memory power up
The function that other raw M signal voltages generate.
After powering on and powering on, Vccp signal voltage is consistently greater than Vcca.When Vdd2 reaches threshold value, Vcca signal is followed
The curve of Vdd1.The voltage value of Vccp is clamped on Vdd2, until a charge pump adapter tube and Vccp pump is arrived greater than Vdd2
Value.Vcca voltage increases with the increase of Vccp voltage, and is maintained at Vdd2 voltage maintenance level below.In this way,
Vccp voltage never is lower than Vcca voltage.
Therefore when powering on, XVdd1 and XVdd2 are elevated, and generate foregoing Pwrup1, Pwrup2 and Pwrup3
Signal.Vccp and Vcca signal initial value is Vss.Deep-sleep number keeps low when powering on.Offb_cca signal is when powering on
It keeps high, keeps low in memory depth suspend mode.When XVdd1 rises, GX1 follows electric drive on XVdd1 and enabled Vccp
The NMOS N1 of device.
When Pwrup2 signal is low, Vcca signal is remained low by NMOS N4.Meanwhile Ensb_cca signal keeps high
Position.Because Offb_cca keeps high-order and Ensb keeps an initial high position, the PMOS P3 of Vcca power drives is disabling.Cause
This, Vcca is not initially to be driven by electric drive circuit on Vcca, and be held in low voltage level.
When Vdd2 starts to increase, and Pwrup3 signal remains low, ClampB be initially it is low and always remain as it is low, until
Pwrup3 signal is transformed into high-voltage state.When ClampB is lower, and voltage XVdd2 is increased, the upper electric drive circuit of Vccp is issued
Clamp signal also increase, and XVdd2 voltage is followed, to open NMOS N2.NMOS N1 and N2 is all in conducting shape
State, it is low that this remains the signal ClampBi of Vccp powered on drive.When ClampBi is low, as long as Vdd2 voltage is high
In a certain threshold voltage, the PMOS device P2 of high pressure Low threshold is opened, since Vcca signal keeps low, so that the voltage of P2 driving
Vccp ratio Vcca signal is higher, faster.
When Pwrup2 signal is transformed into high, disables NMOS N4, while enabling Vcca detector, make Ensb_cca and
Ensb signal is lower.Low Ensb signal opens the PMOS P3 of normal voltage, level threshold value, and makes Vcca signal to Vcca electricity
It is flat to increase.Vcca signal feeds back to Vcca detector.Once Vcca detector is opened, behavior is similar to the comparison for receiving feedback
Device or detection amplifier, i.e. Vcca signal are compared with reference to Vref_cca signal.Then detector is according to Vcca signal
It is no to be less than or greater than Vref_cca signal to control Ensb signal.If Vcca signal is less than Vref_cca, Ensb letter is enabled
Number and be converted to low to drive Vcca signal.If Vcca signal is greater than Vref_cca, disables Ensb and be transformed into high pressure shape
State；In this case, Vcca signal is not driven.
As long as Vcca detector is opened, this process will be repeated constantly.Vcca signal stabilization is attached in Vref_cca benchmark
Closely, which is maintained by Vcca detector.Therefore, before Pwrup3 signal is transformed into height, Vccp signal is charged in advance
Vdd2 rank.Once Pwrup3 is transformed into height, to trigger, ClampB signal is high, then Vccp signal is thus lifted to by charge pump
Higher level.Therefore, Vccp signal will be greater than or equal to Vcca level at any time, especially electric phase on a memory
Between.
When deep-sleep, memory (such as low-power consumption DDR3 DRAM) requires the power consumption of each chip to be less than or equal to 100uA.
In order to reduce the leakage current from external voltage XVdd1, XVdd2, internal power source voltage Vdd1, Vdd2 by PMOS device with
XVdd1, XVdd2 are disconnected, which is controlled by DPD signal.These internal power source voltages include Vdd1 and Vdd2 and other
Builtin voltage is driven to ground.
Although the disclosure is described some embodiments, it is to be appreciated that the disclosure is not limited to
These embodiments.On the contrary, the disclosure is understood that and explains in its broadest sense, as claim is reflected.Cause
This, these claims are construed as not only including equipment described here, method and system, every other and into one
The change and modification of step will be apparent from for having the people of common skill in this respect.
In conclusion the transistor latch prevention system of dynamic RAM of the invention, it is ensured that first voltage signal
Be equal to or more than at any time second voltage signal (including being used in the powering on of respective memory, standby, activation, power-off
When), to prevent the latch-up of transistor.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright description is applied directly or indirectly in other relevant technology necks
Domain is included within the scope of the present invention.
Claims (6)
1. a kind of transistor latch prevention system of dynamic RAM, which is characterized in that powered on including electrification circuit, first
Driver and the second powered on drive, the multiple power on signal of electrification circuit generation, including the first power on signal, second
Power on signal and third power on signal, first powered on drive drive first voltage signal to the trap end of transistor,
As one or more power on signal, second powered on drive sends second voltage signal to the drain electrode of transistor,
As one or more power on signal, wherein first power on signal is greater than the second power on signal.
2. the transistor latch prevention system of dynamic RAM according to claim 1, which is characterized in that described
First power on signal is generated by the first internal power source voltage Vdd1 of memory；Second power on signal is by telecommunications on first
Number and memory the second internal power source voltage Vdd2 generate；The third power on signal is by the second power on signal and memory
The second internal power source voltage Vdd2 generate.
3. the transistor latch prevention system of dynamic RAM according to claim 2, which is characterized in that described
First internal power source voltage Vdd1 is greater than the second internal power source voltage Vdd2.
4. the transistor latch prevention system of dynamic RAM according to claim 1, which is characterized in that described
First powered on drive includes clamp circuit, the first phase inverter, the first PMOS transistor, the second PMOS transistor, the first NMOS
Transistor, the second NMOS transistor and first resistor, the clamp circuit input multiple power on signal, deep-sleep signal and
Outer power voltage exports a clamp signal to the first phase inverter, and the output of first phase inverter is enter into first
The grid end of PMOS transistor and the second NMOS transistor, first PMOS transistor, the first NMOS transistor and second
For PMOS transistor using serial connection, the first resistor is connected to the grid end and external power supply electricity of the first NMOS transistor
Pressure, second PMOS transistor is connected to the second internal power source voltage Vdd2 and drain terminal is connected to the first PMOS transistor
The drain terminal of drain terminal, first PMOS transistor and the second PMOS transistor provides first voltage signal Vccp.
5. the transistor latch prevention system of dynamic RAM according to claim 4, which is characterized in that described
There are two branches, including the first branch and the second branch for clamp circuit；First branch by the second phase inverter, first with it is non-
What door, third phase inverter, the 4th phase inverter and the 5th phase inverter were connected in series；Second branch is by the second NAND gate,
Hex inverter, the 7th phase inverter, the 8th phase inverter and a NMOS transistor serial connection.
6. the transistor latch prevention system of dynamic RAM according to claim 5, which is characterized in that described
Second powered on drive include voltage detector, the 9th phase inverter, the tenth phase inverter, the 11st phase inverter, third NAND gate and
Third PMOS transistor, the output of the voltage detector are connected to the input of the 9th phase inverter, the 9th phase inverter
It is output to first input of third NAND gate, the tenth phase inverter is output to second input of third NAND gate, institute
The output for the third NAND gate stated is connected to the grid end of the 3rd PMOS, and the drain terminal of the 3rd PMOS is connected to the second internal power source voltage
The source of Vdd2, the third PMOS transistor generate second voltage signal Vcca, and second voltage signal Vcca feeds back to electricity
Press detector.
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| CN201910274706.XA CN110060720A (en) | 2019-04-08 | 2019-04-08 | The transistor latch prevention system of dynamic RAM |
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| CN201910274706.XA CN110060720A (en) | 2019-04-08 | 2019-04-08 | The transistor latch prevention system of dynamic RAM |
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