CN110085619B - A vertical high-voltage light-emitting diode chip and its manufacturing method - Google Patents
A vertical high-voltage light-emitting diode chip and its manufacturing method Download PDFInfo
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- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
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Abstract
本发明公开了一种垂直高压发光二极管芯片及其制作方法，其中。通过垂直高压发光二极管芯片的设计，将第一芯片区处的背面电极通过开孔和键合层与导电基板电连接，进而无需在第一芯片区进行刻蚀而裸露其背面电极，保证垂直高压发光二极管芯片的有效发光面积较大；以及，第一芯片区的背面电极不需要打线，节省了成本，提高了可靠性；另外，每一芯片区电流扩展都为垂直方向，且第一芯片区的背面电极与第N芯片区的正面电极形成垂直结构，使得垂直高压发光二极管芯片的电流扩展较好，进而能够避免电流拥堵而提高电流耐受能力；此外，垂直高压发光二极管芯片的光型较好，符合朗伯分布而更易于配光。
The invention discloses a vertical high-voltage light-emitting diode chip and a manufacturing method thereof, wherein. Through the design of the vertical high voltage light emitting diode chip, the back electrode at the first chip area is electrically connected to the conductive substrate through the opening and the bonding layer, so that the back electrode is exposed without etching in the first chip area, so as to ensure the vertical high voltage light emitting diode. The effective light-emitting area of the chip is large; and, the back electrode of the first chip area does not need to be wired, which saves costs and improves reliability; in addition, the current expansion of each chip area is in the vertical direction, and the first chip area The back electrode and the front electrode of the Nth chip area form a vertical structure, so that the current of the vertical high-voltage light-emitting diode chip expands better, thereby avoiding current congestion and improving the current tolerance; in addition, the vertical high-voltage light-emitting diode chip has a better light type , which conforms to the Lambertian distribution and is easier to light distribution.
Description
Technical Field
The invention relates to the technical field of light emitting diodes, in particular to a vertical high-voltage light emitting diode chip and a manufacturing method thereof.
Background
The Light Emitting Diode (LED) is a new product with great influence in the photoelectronic industry, has the characteristics of small volume, long service life, rich and colorful colors, low energy consumption, energy conservation, environmental protection, high safety and the like, is a leap after incandescent lamps and fluorescent lamps in the human lighting history, is driving the upgrading and updating of the industries such as traditional lighting, display and the like, and is widely applied to the fields of lighting, display screens, signal lamps, backlight sources, toys and the like.
The traditional light emitting diode generally works under direct current, and the voltage of a single LED chip is generally between 2 and 4V. In practical applications, especially in high-power light sources, the light source is generally implemented in a series-parallel manner, for example, in a packaging process, one lamp bead adopts a plurality of LED chips in series-parallel connection, or in a lamp assembly process, one light emitting module adopts a plurality of lamp beads in series-parallel connection. But these approaches add bulk, processing and cost. In order to solve these problems, a serial design at a chip level is generally adopted, which can effectively reduce a package volume and a process. However, most of the current chip-level serial designs are used for manufacturing led chips with horizontal electrode structures, and the effective light-emitting area of the led chips with horizontal structures is small under the condition of the led chips with the same size.
Disclosure of Invention
In view of the above, the present invention provides a vertical high voltage light emitting diode chip and a method for manufacturing the same, which effectively solve the problems in the prior art, and the design of the vertical high voltage light emitting diode chip electrically connects the back electrode at the first chip region with the conductive substrate through the opening and the bonding layer, so that the back electrode is exposed without etching the first chip region, thereby ensuring that the effective light emitting area of the vertical high voltage light emitting diode chip is large; the back electrode of the first chip area does not need routing, so that the cost is saved, and the reliability is improved; in addition, the current expansion of each chip area is in the vertical direction, and the back electrode of the first chip area and the front electrode of the Nth chip area form a vertical structure, so that the current expansion of the vertical high-voltage light-emitting diode chip is better, and the current congestion can be avoided to improve the current tolerance; in addition, the light type of the vertical high-voltage light-emitting diode chip is better, and the light distribution is easier due to the fact that the light type of the vertical high-voltage light-emitting diode chip accords with Lambert distribution.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a method for manufacturing a vertical high-voltage light emitting diode chip comprises the following steps:
providing a substrate and an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially overlapped on the substrate;
forming a back electrode on the side of the second type semiconductor, which faces away from the substrate;
forming a second insulating layer on one side of the back electrode, which is far away from the substrate;
forming at least one opening in the second insulating layer;
depositing a bonding layer on the side, away from the substrate, of the second insulating layer, wherein the bonding layer is in contact with the back electrode through the opening;
bonding a conductive substrate on the side of the bonding layer away from the substrate;
removing the substrate;
etching and separating a first chip area to an Nth chip area from the first type semiconductor layer, wherein the second insulating layer is exposed in an area between any two adjacent chip areas, and the second chip area to the Nth chip area are provided with connecting parts which expose corresponding back electrodes of the second chip area to the Nth chip area respectively, wherein the opening is positioned in the first chip area, and N is an integer not less than 2;
depositing a first insulating layer on one side, away from the conductive substrate, of the epitaxial structure, wherein the first insulating layer covers the exposed surface of one side, away from the conductive substrate, of the epitaxial structure;
forming a first hollow opening to an Nth hollow opening and a second connecting opening to an Nth connecting opening on the first insulating layer, wherein the ith hollow opening is positioned at the first type semiconductor of the ith chip area, the jth connecting opening is positioned at the connecting part of the jth chip area, i is a positive integer not greater than N, and j is a positive integer not less than 2 and not greater than N;
and forming a first connecting electrode, an N & lt-1 & gt connecting electrode and a front electrode on one side, which is far away from the conductive substrate, of the first insulating layer, wherein the kth connecting electrode is in contact with the first type conductive layer of the kth chip area and the back electrode of the kth +1 chip area through the kth hollow-out opening and the kth + 1-th connecting opening, the front electrode is in contact with the first type conductive layer of the Nth chip area through the Nth hollow-out opening, and k is a positive integer not greater than N & lt-1 & gt.
Optionally, an unintentionally doped semiconductor layer is further formed between the substrate and the epitaxial structure, wherein after removing the substrate and before etching and separating the first chip region to the nth chip region, the method further includes:
removing the unintentionally doped semiconductor layer.
Optionally, the first chip region to the nth chip region are separated by etching the first type semiconductor layer, the region between any adjacent chip regions is exposed out of the second insulating layer, and the second chip region to the nth chip region are all exposed out of the connecting portion of the back electrode, including:
etching and separating a first chip area to an Nth chip area from the first type semiconductor layer, wherein the second insulating layer is exposed in an area between any two adjacent chip areas;
and etching the second chip region to the Nth chip region by adopting a step etching process to form connecting parts with respective exposed corresponding back electrodes.
Optionally, the connecting portion of the jth chip region is located at a side of the jth chip region close to the jth-1 chip region.
Optionally, the first insulating layer further covers a side surface of the epitaxial structure.
Correspondingly, the invention also provides a vertical high-voltage light-emitting diode chip, which comprises:
a conductive substrate;
a bonding layer on the conductive substrate;
the second insulating layer is positioned on one side, away from the conductive substrate, of the bonding layer, and at least one opening is formed in the second insulating layer;
the back electrode is positioned on one side, away from the conductive substrate, of the second insulating layer, and the back electrode is in contact with the bonding layer through the opening;
the epitaxial structure is positioned on one side, away from the conductive substrate, of the back electrode, the epitaxial structure is divided into a first chip area to an Nth chip area, the second insulating layer is exposed in an area between any two adjacent chip areas, the second chip area to the Nth chip area are provided with connecting parts which expose the back electrodes, the connecting parts respectively correspond to the second chip area and the Nth chip area, the opening is positioned in the first chip area, and N is an integer not less than 2;
a first insulating layer covering an exposed surface of the epitaxial structure on one side away from the conductive substrate, wherein first to nth hollowed-out openings and second to nth connection openings are formed in the first insulating layer, the ith hollowed-out opening is located at a first type semiconductor of the ith chip area, the jth connection opening is located at a connection portion of the jth chip area, i is a positive integer not greater than N, and j is a positive integer not less than 2 and not greater than N;
and the first connecting electrode, the (N-1) th connecting electrode and the front electrode are positioned on one side, away from the conductive substrate, of the first insulating layer, wherein the kth connecting electrode is in contact with the first type conductive layer of the kth chip area and the back electrode of the kth +1 th chip area through the kth hollow-out opening and the kth +1 th connecting opening, the front electrode is in contact with the first type conductive layer of the Nth chip area through the Nth hollow-out opening, and k is a positive integer not greater than N-1.
Optionally, the connecting portion of the jth chip region is located at a side of the jth chip region close to the jth-1 chip region.
Optionally, the first insulating layer further covers a side surface of the epitaxial structure.
Optionally, the conductive substrate is a conductive heat dissipation substrate.
Optionally, the first type semiconductor layer is an N-type semiconductor layer, and the second type semiconductor layer is a P-type semiconductor layer.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a vertical high-voltage light-emitting diode chip and a manufacturing method thereof. Through the design of the vertical high-voltage light-emitting diode chip, the back electrode at the first chip area is electrically connected with the conductive substrate through the opening and the bonding layer, so that the back electrode of the first chip area is exposed without etching, and the effective light-emitting area of the vertical high-voltage light-emitting diode chip is ensured to be larger; the back electrode of the first chip area does not need routing, so that the cost is saved, and the reliability is improved; in addition, the current expansion of each chip area is in the vertical direction, and the back electrode of the first chip area and the front electrode of the Nth chip area form a vertical structure, so that the current expansion of the vertical high-voltage light-emitting diode chip is better, and the current congestion can be avoided to improve the current tolerance; in addition, the light type of the vertical high-voltage light-emitting diode chip is better, and the light distribution is easier due to the fact that the light type of the vertical high-voltage light-emitting diode chip accords with Lambert distribution.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a vertical high voltage light emitting diode chip according to an embodiment of the present disclosure;
fig. 2 is a flowchart of another method for manufacturing a vertical high voltage light emitting diode chip according to an embodiment of the present disclosure.
Fig. 3 to 13 are schematic structural diagrams corresponding to the steps in fig. 2.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As mentioned in the background, conventional LEDs typically operate on direct current, with a single LED chip typically operating at between 2-4V. In practical applications, especially in high-power light sources, the light source is generally implemented in a series-parallel manner, for example, in a packaging process, one lamp bead adopts a plurality of LED chips in series-parallel connection, or in a lamp assembly process, one light emitting module adopts a plurality of lamp beads in series-parallel connection. But these approaches add bulk, processing and cost. In order to solve these problems, a serial design at a chip level is generally adopted, which can effectively reduce a package volume and a process. However, most of the current chip-level serial designs are used for manufacturing led chips with horizontal electrode structures, and the effective light-emitting area of the led chips with horizontal structures is small under the condition of the led chips with the same size.
Based on this, the embodiment of the application provides a vertical high-voltage light emitting diode chip and a manufacturing method thereof, which effectively solve the problems existing in the prior art, and by the design of the vertical high-voltage light emitting diode chip, the back electrode at the first chip area is electrically connected with the conductive substrate through the opening and the bonding layer, so that the back electrode is exposed without etching in the first chip area, and the effective light emitting area of the vertical high-voltage light emitting diode chip is ensured to be larger; the back electrode of the first chip area does not need routing, so that the cost is saved, and the reliability is improved; in addition, the current expansion of each chip area is in the vertical direction, and the back electrode of the first chip area and the front electrode of the Nth chip area form a vertical structure, so that the current expansion of the vertical high-voltage light-emitting diode chip is better, and the current congestion can be avoided to improve the current tolerance; in addition, the light type of the vertical high-voltage light-emitting diode chip is better, and the light distribution is easier due to the fact that the light type of the vertical high-voltage light-emitting diode chip accords with Lambert distribution. In order to achieve the above object, the technical solutions provided by the embodiments of the present application are described in detail below, specifically with reference to fig. 1 to 13.
Referring to fig. 1, a flowchart of a method for manufacturing a vertical high voltage light emitting diode chip is provided in an embodiment of the present application, where the method includes:
s1, providing a substrate and an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially overlapped on the substrate;
s2, forming a back electrode on the side, away from the substrate, of the second type semiconductor;
s3, forming a second insulating layer on the side, facing away from the substrate, of the back electrode;
s4, forming at least one opening on the second insulating layer;
s5, depositing a bonding layer on the side, away from the substrate, of the second insulating layer, wherein the bonding layer is in contact with the back electrode through the opening;
s6, bonding a conductive substrate on the side of the bonding layer, which is far away from the substrate;
s7, removing the substrate;
s8, etching and separating a first chip area to an Nth chip area from the first type semiconductor layer, wherein the second insulating layer is exposed in an area between any two adjacent chip areas, and the second chip area to the Nth chip area are provided with connecting parts which expose corresponding back electrodes of the second chip area to the Nth chip area respectively, wherein the opening is located in the first chip area, and N is an integer not less than 2;
s9, depositing a first insulating layer on one side, away from the conductive substrate, of the epitaxial structure, wherein the first insulating layer covers the exposed surface of one side, away from the conductive substrate, of the epitaxial structure;
s10, forming a first hollow opening to an Nth hollow opening and a second connecting opening to an Nth connecting opening on the first insulating layer, wherein the ith hollow opening is located at the first type semiconductor of the ith chip area, the jth connecting opening is located at the connecting part of the jth chip area, i is a positive integer not more than N, and j is a positive integer not less than 2 and not more than N;
s11, forming a first connecting electrode, an N-1 connecting electrode and a front electrode on one side, away from the conductive substrate, of the first insulating layer, wherein the kth connecting electrode is in contact with the first type conductive layer of the kth chip region and the back electrode of the kth +1 chip region through the kth hollow-out opening and the kth +1 connecting opening, the front electrode is in contact with the first type conductive layer of the Nth chip region through the Nth hollow-out opening, and k is a positive integer not greater than N-1.
It can be understood that, in the technical scheme provided in the embodiment of the present application, through the design of the vertical high voltage light emitting diode chip, the back electrode at the first chip region is electrically connected to the conductive substrate through the opening and the bonding layer, and thus the back electrode is exposed without etching the first chip region, which ensures that the effective light emitting area of the vertical high voltage light emitting diode chip is large;
moreover, the back electrode of the first chip area provided by the embodiment of the application does not need routing, so that the cost is saved, and the reliability is improved; in addition, the current expansion of each chip area is in the vertical direction, and the back electrode of the first chip area and the front electrode of the Nth chip area form a vertical structure, so that the current expansion of the vertical high-voltage light-emitting diode chip is better, and the current congestion can be avoided to improve the current tolerance;
in addition, the light type of the vertical high-voltage light-emitting diode chip provided by the embodiment of the application is better, and the light distribution is easier due to the fact that the light type accords with Lambert distribution.
Furthermore, an unintentional doped semiconductor layer can be grown between the substrate and the epitaxial structure, so that the quality of the grown epitaxial structure can be improved; when an unintentionally doped semiconductor layer is further formed between the substrate and the epitaxial structure, wherein after the substrate is removed and before the first chip region is separated by etching to the nth chip region, the method further includes:
removing the unintentionally doped semiconductor layer.
Referring to fig. 2 in detail, a flowchart of another method for manufacturing a vertical high voltage light emitting diode according to an embodiment of the present disclosure is shown, where the method includes:
s1, providing a substrate and an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially overlapped on the substrate, and an unintended doped semiconductor layer is formed between the substrate and the epitaxial structure;
s2, forming a back electrode on the side, away from the substrate, of the second type semiconductor;
s3, forming a second insulating layer on the side, facing away from the substrate, of the back electrode;
s4, forming at least one opening on the second insulating layer;
s5, depositing a bonding layer on the side, away from the substrate, of the second insulating layer, wherein the bonding layer is in contact with the back electrode through the opening;
s6, bonding a conductive substrate on the side of the bonding layer, which is far away from the substrate;
s7, removing the unintentional doped semiconductor layer after removing the substrate;
s8, etching and separating a first chip area to an Nth chip area from the first type semiconductor layer, wherein the second insulating layer is exposed in an area between any two adjacent chip areas, and the second chip area to the Nth chip area are provided with connecting parts which expose corresponding back electrodes of the second chip area to the Nth chip area respectively, wherein the opening is located in the first chip area, and N is an integer not less than 2;
s9, depositing a first insulating layer on one side, away from the conductive substrate, of the epitaxial structure, wherein the first insulating layer covers the exposed surface of one side, away from the conductive substrate, of the epitaxial structure;
s10, forming a first hollow opening to an Nth hollow opening and a second connecting opening to an Nth connecting opening on the first insulating layer, wherein the ith hollow opening is located at the first type semiconductor of the ith chip area, the jth connecting opening is located at the connecting part of the jth chip area, i is a positive integer not more than N, and j is a positive integer not less than 2 and not more than N;
s11, forming a first connecting electrode, an N-1 connecting electrode and a front electrode on one side, away from the conductive substrate, of the first insulating layer, wherein the kth connecting electrode is in contact with the first type conductive layer of the kth chip region and the back electrode of the kth +1 chip region through the kth hollow-out opening and the kth +1 connecting opening, the front electrode is in contact with the first type conductive layer of the Nth chip region through the Nth hollow-out opening, and k is a positive integer not greater than N-1.
The manufacturing method provided by the embodiment of the present application is described in more detail with reference to fig. 3 to 13, wherein fig. 3 to 13 are schematic structural diagrams corresponding to the steps in fig. 2. In the following description, N is 2 as an example.
As shown in fig. 3, corresponding to step S1, a substrate 10 and an epitaxial structure are provided, the epitaxial structure includes a first type semiconductor layer 110, an active region 120 and a second type semiconductor layer 130 stacked in sequence on the substrate, and an unintentionally doped semiconductor layer 20 is further formed between the substrate 10 and the epitaxial structure.
It can be understood that, after the substrate is provided, the light-emitting semiconductor material layer is grown on the substrate in sequence, that is, an epitaxial structure composed of the first type semiconductor layer, the active layer and the second type semiconductor layer is grown. Further, in order to improve the growth quality of the epitaxial structure, an unintentionally doped semiconductor layer may also be grown on the substrate before the epitaxial structure is grown on the substrate.
In an embodiment of the present application, the first type semiconductor layer provided in the present application may be an N-type semiconductor layer, and the second type semiconductor layer may be a P-type semiconductor layer.
It should be noted that the epitaxial structure provided in the embodiments of the present application is not limited to include the first type semiconductor layer, the active layer, and the second type semiconductor layer, and may further include other material layers for optimizing light emission, and the present application is not limited in particular.
As shown in fig. 4, corresponding to step S2, a back electrode 140 is formed on the side of the second type semiconductor 130 facing away from the substrate 10.
In an embodiment of the present application, the back electrode provided in the present application may be a single metal layer, or may be a stack of a plurality of metal layers, and the present application is not limited in particular.
As shown in fig. 5, corresponding to step S3, a second insulating layer 220 is formed on the side of the back electrode 140 facing away from the substrate.
In the embodiment of the application, through the arrangement of the second insulating layer, the back electrodes of different chip areas are prevented from being electrically connected with the bonding layer, so that the chip areas are mistakenly connected on the conductive substrate.
It should be noted that, in the embodiment of the present application, the material and the thickness of the second insulating layer are not particularly limited, and the second insulating layer needs to be specifically designed according to the actual application.
As shown in fig. 6, at least one opening 221 is formed in the second insulating layer 220, corresponding to step S4.
In an embodiment of the present application, the opening provided in the present application may be formed by a photolithography process, that is, a mask layer is formed on a side of the second insulating layer away from the substrate, the mask layer has a hollow portion exposing the opening, and then the hollow portion is etched to form the opening in the second insulating layer, so as to finally remove the mask layer.
As shown in fig. 7, corresponding to step S5, a bonding layer 300 is deposited on the second insulating layer 220 on the side facing away from the substrate 10, and the bonding layer 300 is in contact with the back electrode 140 through the opening 221.
As shown in fig. 8, corresponding to step S6, a conductive substrate 400 is bonded to the side of the bonding layer 300 facing away from the substrate 10.
In an embodiment of the present application, the conductive substrate provided by the present application can be a conductive heat dissipation substrate, so as to improve the heat dissipation capability of the vertical high voltage light emitting diode chip.
As shown in fig. 9, corresponding to step S7, after removing the substrate 10, the unintentionally doped semiconductor layer 20 is removed.
In an embodiment of the present application, the substrate and the unintentional doped semiconductor layer may be removed by using laser lift-off, dry etching, wet etching, and other processes, which are not limited in this application.
As shown in fig. 10, corresponding to step S8, a first chip region to an nth chip region are etched and separated from the first type semiconductor layer 110, the second insulating layer 220 is exposed in a region between any two adjacent chip regions, and each of the second chip region to the nth chip region has a connecting portion 141 exposing a corresponding one of the back electrodes 140, wherein the opening is located in the first chip region, and N is an integer not less than 2;
in an embodiment of the present application, the first chip region to the nth chip region are separated by etching the first type semiconductor layer, and the region between any adjacent chip regions is exposed out of the second insulating layer, and the second chip region to the nth chip region are exposed to the connecting portion of the back electrode, including:
etching and separating a first chip area to an Nth chip area from the first type semiconductor layer, wherein the second insulating layer is exposed in an area between any two adjacent chip areas;
and etching the second chip region to the Nth chip region by adopting a step etching process to form connecting parts with respective exposed corresponding back electrodes.
In order to increase the effective light emitting area of the vertical high voltage light emitting diode, the connection portion of the jth chip region provided by the embodiment of the application is located at the side edge of the jth chip region close to the jth-1 chip region.
In an embodiment of the present application, the first chip region to the second chip region provided in the present application may be arranged in a straight line, or arranged in a ring, or arranged in an end-to-end arch, which is not limited in this application.
As shown in fig. 11, corresponding to step S9, a first insulating layer 210 is deposited on a side of the epitaxial structure facing away from the conductive substrate 400, and the first insulating layer 210 covers an exposed surface of the epitaxial structure facing away from the conductive substrate 400.
It should be noted that the first insulating layer covering epitaxial structure provided in the embodiment of the present application deviates from the exposed surface of one side of the conductive substrate, that is, the first insulating layer covers the surface of the first type semiconductor layer exposed in all the chip regions, the side surface between adjacent chip regions, the connecting portion exposed in the back electrode, and the exposed surface of one side of the second insulating layer deviating from the conductive substrate.
Furthermore, the first insulating layer provided by the embodiment of the application also covers the side face of the epitaxial structure, so that the condition of electric leakage of the vertical high-voltage light-emitting diode is avoided.
As shown in fig. 12, corresponding to step S10, first to nth hollow openings (hollow openings 211) and second to nth connection openings (connection openings 212) are formed on the first insulating layer 210, the ith hollow opening is located at the first type semiconductor of the ith chip region, and the jth connection opening is located at the connection portion of the jth chip region, i is a positive integer not greater than N, and j is a positive integer not less than 2 and not greater than N.
In an embodiment of the present application, the hollow opening and the connecting opening provided in the present application can be formed by a photolithography process.
As shown in fig. 13, corresponding to step S11, a first to N-1 connection electrode (connection electrode 510) and a front electrode 520 are formed on a side of the first insulating layer 210 away from the conductive substrate 400, wherein the kth connection electrode is in contact with both the first type conductive layer of the kth chip region and the back electrode of the kth chip region through the kth hollow opening and the kth +1 connection opening, and the front electrode is in contact with the first type conductive layer of the nth chip region through the nth hollow opening, k is a positive integer not greater than N-1.
Correspondingly, this application embodiment still provides a vertical high voltage light emitting diode chip, includes:
a conductive substrate;
a bonding layer on the conductive substrate;
the second insulating layer is positioned on one side, away from the conductive substrate, of the bonding layer, and at least one opening is formed in the second insulating layer;
the back electrode is positioned on one side, away from the conductive substrate, of the second insulating layer, and the back electrode is in contact with the bonding layer through the opening;
the epitaxial structure is positioned on one side, away from the conductive substrate, of the back electrode, the epitaxial structure is divided into a first chip area to an Nth chip area, the second insulating layer is exposed in an area between any two adjacent chip areas, the second chip area to the Nth chip area are provided with connecting parts which expose the back electrodes, the connecting parts respectively correspond to the second chip area and the Nth chip area, the opening is positioned in the first chip area, and N is an integer not less than 2;
a first insulating layer covering an exposed surface of the epitaxial structure on one side away from the conductive substrate, wherein first to nth hollowed-out openings and second to nth connection openings are formed in the first insulating layer, the ith hollowed-out opening is located at a first type semiconductor of the ith chip area, the jth connection opening is located at a connection portion of the jth chip area, i is a positive integer not greater than N, and j is a positive integer not less than 2 and not greater than N;
and the first connecting electrode, the (N-1) th connecting electrode and the front electrode are positioned on one side, away from the conductive substrate, of the first insulating layer, wherein the kth connecting electrode is in contact with the first type conductive layer of the kth chip area and the back electrode of the kth +1 th chip area through the kth hollow-out opening and the kth +1 th connecting opening, the front electrode is in contact with the first type conductive layer of the Nth chip area through the Nth hollow-out opening, and k is a positive integer not greater than N-1.
In an embodiment of the present application, the connection portion of the jth chip region provided by the present application is located at a side edge of the jth chip region close to the jth-1 chip region.
And the first insulating layer provided by the application also covers the side face of the epitaxial structure.
Further, the conductive substrate provided by the embodiment of the present application is a conductive heat dissipation substrate, so as to improve the heat dissipation performance of the vertical high voltage light emitting diode.
In an embodiment of the present application, the first type semiconductor layer provided in the present application is an N-type semiconductor layer, and the second type semiconductor layer is a P-type semiconductor layer.
The embodiment of the application provides a vertical high-voltage light-emitting diode chip and a manufacturing method thereof. Through the design of the vertical high-voltage light-emitting diode chip, the back electrode at the first chip area is electrically connected with the conductive substrate through the opening and the bonding layer, so that the back electrode of the first chip area is exposed without etching, and the effective light-emitting area of the vertical high-voltage light-emitting diode chip is ensured to be larger; the back electrode of the first chip area does not need routing, so that the cost is saved, and the reliability is improved; in addition, the current expansion of each chip area is in the vertical direction, and the back electrode of the first chip area and the front electrode of the Nth chip area form a vertical structure, so that the current expansion of the vertical high-voltage light-emitting diode chip is better, and the current congestion can be avoided to improve the current tolerance; in addition, the light type of the vertical high-voltage light-emitting diode chip is better, and the light distribution is easier due to the fact that the light type of the vertical high-voltage light-emitting diode chip accords with Lambert distribution.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention should not be limited to the embodiments shown herein, but rather
Is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
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| CN114122214A (en) * | 2022-01-25 | 2022-03-01 | 北京芯海视界三维科技有限公司 | Light-emitting devices and display devices |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972374A (en) * | 2013-01-25 | 2014-08-06 | 台积固态照明股份有限公司 | Multi-Vertical LED Packaging Structure |
| CN204538029U (en) * | 2015-02-10 | 2015-08-05 | 大连德豪光电科技有限公司 | A kind of flip LED chips |
| CN105552180A (en) * | 2016-02-02 | 2016-05-04 | 映瑞光电科技(上海)有限公司 | Fabrication method of novel high-voltage LED |
| CN105762246A (en) * | 2016-04-25 | 2016-07-13 | 厦门乾照光电股份有限公司 | Vertical structure light emitting diode and manufacturing method thereof |
| CN107170856A (en) * | 2017-04-25 | 2017-09-15 | 淮安澳洋顺昌光电技术有限公司 | The preparation method of upside-down mounting high voltage LED chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9666764B2 (en) * | 2012-04-09 | 2017-05-30 | Cree, Inc. | Wafer level packaging of multiple light emitting diodes (LEDs) on a single carrier die |
-
2019
- 2019-04-30 CN CN201910360845.4A patent/CN110085619B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972374A (en) * | 2013-01-25 | 2014-08-06 | 台积固态照明股份有限公司 | Multi-Vertical LED Packaging Structure |
| CN204538029U (en) * | 2015-02-10 | 2015-08-05 | 大连德豪光电科技有限公司 | A kind of flip LED chips |
| CN105552180A (en) * | 2016-02-02 | 2016-05-04 | 映瑞光电科技(上海)有限公司 | Fabrication method of novel high-voltage LED |
| CN105762246A (en) * | 2016-04-25 | 2016-07-13 | 厦门乾照光电股份有限公司 | Vertical structure light emitting diode and manufacturing method thereof |
| CN107170856A (en) * | 2017-04-25 | 2017-09-15 | 淮安澳洋顺昌光电技术有限公司 | The preparation method of upside-down mounting high voltage LED chip |
Non-Patent Citations (1)
| Title |
|---|
| 利用次级变压器串联均流的多路LED驱动器电路设计;董方珉;《蚌埠学院学报》;20150820;24-28 * |
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