CN110097919B - Storage system, method of determining error thereof, and electronic device including the same - Google Patents

Abstract

A storage system, a method of determining an error thereof, and an electronic device including the same are provided. The storage system includes: a memory device including a buffer die, a core die disposed on the buffer die, a plurality of channels, and a through silicon via configured to transmit signals between the buffer die and at least one core die; a memory controller configured to output a command signal and an address signal to the memory device, output a data signal to the memory device, and receive a data signal from the memory device; and an interposer including a plurality of channel paths for connecting the memory controller and the plurality of channels, wherein the memory device further includes a path selector for changing a connection state between the plurality of channels and the plurality of channel paths, the path selector changing the first connection state to the second connection state when an error is detected in the first connection state between the plurality of channels and the plurality of channel paths.

Description

Storage system, method for determining error thereof, and electronic device including the same

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2018-0012200 filed on January 31, 2018 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Exemplary embodiments of the inventive concept relate to a memory system, a method of determining an error of the memory system, and an electronic device including the memory system.

Background technique

Generally, a high bandwidth memory (HBM) includes a multi-channel memory and a channel path connecting the multi-channel memory and a memory controller.

When an error occurs in a storage system including a multi-channel memory, it may be difficult to determine where the error occurs. For example, the error may occur in the storage system or in a channel path connecting the multi-channel memory and a storage controller.

In addition, when the storage system is transferred to an independent error determination system instead of the real workload system for error detection, the error is not reproduced, and thus the location of the error may not be determined.

Summary of the invention

In an exemplary embodiment of a storage system conceived according to the present invention, the storage system includes: a storage device, the storage device including a buffer die, a plurality of core dies arranged on the buffer die, a plurality of channels and a through-silicon via, the through-silicon via being configured to send signals between the buffer die and at least one of the plurality of core dies; a storage controller, the storage controller being configured to output command signals and address signals to the storage device, output data signals to the storage device, and receive data signals from the storage device; and an interposer, the interposer including a plurality of channel paths for connecting the storage controller and the plurality of channels, wherein the storage device also includes a path selector for changing a connection state between the plurality of channels and the plurality of channel paths, wherein when an error of the storage system is detected in a first connection state between the plurality of channels and the plurality of channel paths, the path selector changes the first connection state between the plurality of channels and the plurality of channel paths to a second connection state.

In an exemplary embodiment of a method for determining an error of a storage system including a storage device and a storage controller according to the present invention, the method includes: detecting an error of the storage system in a first connection state between multiple channels of the storage device and multiple channel paths of the storage system, the multiple channel paths connecting the multiple channels to the storage controller, the storage device including a buffer die, a plurality of core dies arranged on the buffer die, and a through-silicon via, the through-silicon via being configured to send a signal between at least one core die of the plurality of core dies and the buffer die; when an error of the storage system is detected, changing the connection state between the plurality of channels and the plurality of channel paths from the first connection state to a second connection state; and detecting an error of the storage system in the second connection state.

In an exemplary embodiment of an electronic device according to the concept of the present invention, the electronic device includes an application processor; a storage system, the storage system is configured to be operated by the application processor. The storage system includes: a storage device, the storage device includes a buffer die, a plurality of core dies arranged on the buffer die, a plurality of channels and a through-silicon path, the through-silicon path is configured to send signals between at least one of the plurality of core dies and the buffer die; a storage controller, the storage controller is configured to output command signals and address signals to the storage device, output data signals to the storage device, and receive data signals from the storage device; and an interposer, the interposer includes a plurality of channel paths for connecting the storage controller and the plurality of channels, wherein the storage device further includes a path selector for changing the connection state between the plurality of channels and the plurality of channel paths, wherein when an error of the storage system is detected in a first connection state between the plurality of channels and the plurality of channel paths, the path selector changes the first connection state between the plurality of channels and the plurality of channel paths to a second connection state.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept; FIG.

FIG. 2 is a diagram illustrating the memory system of FIG. 1 according to an exemplary embodiment of the inventive concept; FIG.

FIG. 3 is a diagram illustrating the storage device of FIG. 2 according to an exemplary embodiment of the inventive concept; FIG.

4 is a diagram illustrating a core die of the memory device of FIG. 2 according to an exemplary embodiment of the inventive concept;

5 is a block diagram illustrating a core die of FIG. 2 according to an exemplary embodiment of the inventive concept;

6A is a diagram illustrating a first connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

6B is a diagram illustrating a second connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

7A is a diagram illustrating a first connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

7B is a diagram illustrating a second connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

8A is a diagram illustrating a first connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

8B is a diagram illustrating a second connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

9A is a diagram illustrating a first connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

9B is a diagram illustrating a second connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

10A is a diagram illustrating a first connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

10B is a diagram illustrating a second connection state of a path selector provided on the buffer die of FIG. 2 according to an exemplary embodiment of the inventive concept;

FIG. 11 is a diagram illustrating a memory system according to an exemplary embodiment of the inventive concept; FIG.

12A is a diagram illustrating a first connection state of a path selector provided on the buffer die of FIG. 11 according to an exemplary embodiment of the inventive concept;

12B is a diagram illustrating a second connection state of a path selector provided on the buffer die of FIG. 11 according to an exemplary embodiment of the inventive concept;

12C is a diagram illustrating a third connection state of a path selector provided on the buffer die of FIG. 11 according to an exemplary embodiment of the inventive concept; and

FIG. 13 is a block diagram illustrating an electronic device including a memory system according to an exemplary embodiment of the inventive concept.

Detailed ways

The exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments described herein. Throughout this application, the same reference numerals may refer to the same elements.

FIG1 is a block diagram illustrating a memory system 1000 according to an exemplary embodiment of the inventive concept. FIG2 is a diagram illustrating the memory system 1000 of FIG1 according to an exemplary embodiment of the inventive concept.

1 and 2, the memory system 1000 includes a memory controller 1100 and a memory device 1200. The memory system 1000 may further include an interposer 1300 disposed between the memory controller 1100 and the memory device 1200. The memory controller 1100 and the memory device 1200 may be disposed on the interposer 1300, for example. For example, the interposer 1300 may be a silicon interposer. For example, the memory controller 1100 and the memory device 1200 may be disposed on the same plane. The memory system 1000 may further include a packaging substrate 1400. The interposer 1300 may be disposed on the packaging substrate 1400.

The first bump BP1 may be disposed between the interposer 1300 and the memory controller 1100. The second bump BP2 may be disposed between the interposer 1300 and the memory device 1200. The third bump BP3 may be disposed between the package substrate 1400 and the interposer 1300. The size of the third bump BP3 may be greater than that of each of the first bump BP1 and the second bump BP2.

The memory device 1200 may include a buffer die BD and at least one core die (eg, CD1 , CD2 , CD3 , and CD4 ) disposed on the buffer die BD.

The buffer die BD may include a plurality of buffers. The buffers are connected to channel paths CP1, CP2, CP3, CP4, CP5, CP6, CP7, CP8, CP9, CP10, CP11, CP12, CP13, CP14, CP15, and CP16, and output data signals DQ transmitted through channel paths CP1 to CP16 to channels CH1, CH2, CH3, CH4, CH5, CH6, CH7, CH8, CH9, CH10, CH11, CH12, CH13, CH14, CH15, and CH16.

The memory device 1200 may include channels CH1 to CH16. For example, the first core die CD1 disposed on the buffer die BD may include the first channel CH1 to the fourth channel CH4. For example, the second core die CD2 disposed on the first core die CD1 may include the fifth channel CH5 to the eighth channel CH8. For example, the third core die CD3 disposed on the second core die CD2 may include the ninth channel CH9 to the twelfth channel CH12. For example, the fourth core die CD4 disposed on the third core die CD3 may include the thirteenth channel CH13 to the sixteenth channel CH16. For example, the memory device 1200 may be a dynamic random access memory (DRAM) device.

Signals may be sent between the buffer die BD and the core dies CD1 to CD4 through through silicon vias.

The interposer 1300 may include channel paths CP1 to CP16 connecting the channels CH1 to CH16 of the memory device 1200 and the memory controller 1100. The channels CH1 to CH16 of the memory device 1200 may be connected to the memory controller 1100 through the channel paths CP1 to CP16. Although FIG. 2 shows only two channel paths CP1 and CP2 for clarity, it should be understood that the remaining channel paths CP3 to CP16 are connected to the first bump BP1 of the memory controller 1100 in a similar manner. The interposer 1300 may also include at least one repair channel path RP connecting the channels CH1 to CH16 of the memory device 1200 and the memory controller 1100. When an error occurs at one of the channel paths CP1 to CP16, the memory controller 1100 may communicate with the channels CH1 to CH16 of the memory device 1200 through the repair channel path RP.

The memory controller 1100 may output a command signal CMD and an address signal ADDR to the memory device 1200 through channel paths CP1 to CP16. The memory controller 1100 may output a data signal DQ to the memory device 1200 through channel paths CP1 to CP16, and receive the data signal DQ from the memory device 1200 through channel paths CP1 to CP16.

FIG. 3 is a diagram illustrating the memory device 1200 of FIG. 2 according to an exemplary embodiment of the inventive concept.

1 to 3 , the buffer die BD and the core dies CD1 to CD4 may be stacked. The buffer die BD and the core dies CD1 to CD4 may be connected to each other through through silicon vias.

The through silicon via is electrically connected to the internal circuits of the core dies CD1 to CD4 and the internal circuits of the buffer die BD. For example, the electrical connection between the through silicon via and the internal circuits of the core dies CD1 to CD4 and the internal circuits of the buffer die BD can be formed by selectively cutting an electrical fuse or selectively opening and closing a switch circuit in response to a control signal.

The second core die CD2 may be directly disposed on the first core die CD1. The third core die CD3 may be directly disposed on the second core die CD2. The fourth core die CD4 may be directly disposed on the third core die CD3. For example, a through-silicon path for sending a first common chip select signal CS1 may be electrically connected to an internal circuit of the first core die CD1 and an internal circuit of the third core die CD3. A through-silicon path for sending a second common chip select signal CS2 may be electrically connected to an internal circuit of the second core die CD2 and an internal circuit of the fourth core die CD4. A through-silicon path for sending a command address signal CA may be electrically connected to an internal circuit of each core die in the first core die CD1 to the fourth core die CD4. A through-silicon path for sending a data signal DQ may be electrically connected to an internal circuit of each core die in the first core die CD1 to the fourth core die CD4.

FIG. 4 is a diagram illustrating core dies CD1 to CD4 of the memory device 1200 of FIG. 2 according to an exemplary embodiment of the inventive concept.

1 to 4 , the memory device 1200 may include a plurality of core dies or core layers CD1 to CDK. Here, K is a positive integer equal to or greater than 2.

The core dies CD1 to CDK (also referred to as the first core die to the Kth core die) transmit signals through through silicon vias TSV. A plurality of through silicon vias TSV are provided. The first core die CD1 can communicate with the memory controller 1100 through the buffer die BD.

The first core die CD1 to the Kth core die CDK respectively include peripheral circuits 1220 for driving the memory cell array region (or memory region) 1210. For example, the peripheral circuits 1220 may include: a row driver (e.g., an X-driver) for driving the word lines of the memory cell array region 1210; a column driver (e.g., a Y-driver) for driving the bit lines of the memory cell array region 1210; a data input and output portion for controlling the input and output of data signals; a command buffer for receiving a command signal CMD and for buffering the command signal CMD; and an address buffer for receiving an address signal ADDR and for buffering the address signal ADDR. The command signal CMD and the address signal ADDR may be received from the outside of the first core die CD1 to the Kth core die CDK.

The first core die CD1 may further include a control logic circuit that controls access to the memory area 1210 based on the command signal CMD and the address signal ADDR and generates a control signal for accessing the memory area 1210. Alternatively, the control logic circuit may be provided on the buffer die BD.

FIG. 5 is a block diagram illustrating the core die CD1 of FIG. 2 according to an exemplary embodiment of the inventive concept.

1 to 5 , the core die CD1 includes a control logic circuit 210, a refresh control circuit 215, an address register 220, a memory bank control logic circuit 230, a row address multiplexer (RA MUX) 240, a column address latch 250, a row decoder (e.g., 260 a to 260 d), a column decoder (e.g., 270 a to 270 d), a memory cell array (e.g., 280 a to 280 d), a sense amplifier unit (e.g., 285 a to 285 d), an input/output (I/O) selection circuit 290, and a data I/O buffer 295.

The memory cell array (e.g., 280a to 280d) may include a plurality of memory cell arrays, e.g., a first memory cell array 280a, a second memory cell array 280b, a third memory cell array 280c, and a fourth memory cell array 280d. The row decoder may include a plurality of memory cell row decoders, e.g., a first memory cell row decoder 260a, a second memory cell row decoder 260b, a third memory cell row decoder 260c, and a fourth memory cell row decoder 260d connected to the first memory cell array 280a, the second memory cell array 280b, the third memory cell array 280c, and the fourth memory cell array 280d, respectively. The column decoder may include a plurality of bank column decoders, for example, a first bank column decoder 270a, a second bank column decoder 270b, a third bank column decoder 270c, and a fourth bank column decoder 270d, respectively connected to the first bank array 280a, the second bank array 280b, the third bank array 280c, and the fourth bank array 280d. The sense amplifier unit may include a plurality of bank sense amplifiers, for example, a first bank sense amplifier 285a, a second bank sense amplifier 285b, a third bank sense amplifier 285c, and a fourth bank sense amplifier 285d, respectively connected to the first bank array 280a, the second bank array 280b, the third bank array 280c, and the fourth bank array 280d. The first memory bank array 280a to the fourth memory bank array 280d, the first memory bank row decoders 260a to the fourth memory bank row decoders 260d, the first memory bank column decoders 270a to the fourth memory bank column decoders 270d, and the first memory bank readout amplifiers 285a to the fourth memory bank readout amplifiers 285d can respectively form a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank. For example, the first memory bank array 280a, the first memory bank row decoder 260a, the first memory bank column decoder 270a and the first memory bank sense amplifier 285a can form a first memory bank; the second memory bank array 280b, the second memory bank row decoder 260b, the second memory bank column decoder 270b and the second memory bank sense amplifier 285b can form a second memory bank; the third memory bank array 280c, the third memory bank row decoder 260c, the third memory bank column decoder 270c and the third memory bank sense amplifier 285c can form a third memory bank; the fourth memory bank array 280d, the fourth memory bank row decoder 260d, the fourth memory bank column decoder 270d and the fourth memory bank sense amplifier 285d can form a fourth memory bank. Although FIG. 5 shows a core die CD1 including four memory banks, the core die CD1 can include any number of memory banks. For example, the core die CD1 can include less than four memory banks or more than four memory banks.

The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller (e.g., the memory controller 1100 in FIG. 1 ). The address register 220 may provide the received bank address BANK_ADDR to the bank control logic circuit 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

The bank control logic circuit 230 may generate a bank control signal in response to receiving the bank address BANK_ADDR. In response to the bank control signal generated by the bank control logic circuit 230, a bank row decoder corresponding to the received bank address BANK_ADDR among the first bank row decoder 260a to the fourth bank row decoder 260d may be activated. In addition, in response to the bank control signal generated by the bank control logic circuit 230, a bank column decoder corresponding to the received bank address BANK_ADDR among the first bank column decoder 270a to the fourth bank column decoder 270d may be activated.

The refresh control circuit 215 may generate a refresh address REF_ADDR in response to receiving a refresh command. For example, the refresh control circuit 215 may include a refresh counter configured to sequentially change the refresh address REF_ADDR from the first address of the memory cell array (e.g., 280a to 280d) to the last address of the memory cell array (e.g., 280a to 280d).

The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220, and may receive a refresh address REF_ADDR from the refresh control circuit 215. The row address multiplexer 240 may selectively output a row address ROW_ADDR or a refresh address REF_ADDR. The row address (e.g., row address ROW_ADDR or refresh address REF_ADDR) output from the row address multiplexer 240 may be applied to the first to fourth bank row decoders 260a to 260d.

The activated bank row decoder among the first bank row decoder 260a to the fourth bank row decoder 260d may decode the row address output from the row address multiplexer 240 and may activate a word line corresponding to the row address. For example, the activated bank row decoder (e.g., 260a) may apply a word line driving voltage to the word line corresponding to the row address.

The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or received column address COL_ADDR to the first to fourth bank column decoders 270a to 270d.

An activated bank column decoder among the first to fourth bank column decoders 270 a to 270 d may decode the column address COL_ADDR output from the column address latch 250 and may control the I/O gating circuit 290 to output data corresponding to the column address COL_ADDR.

The I/O gating circuit 290 may include a circuit for gating I/O data. For example, the I/O gating circuit 290 may include an input data masking logic, a read data latch for storing data output from the first memory bank array 280a to the fourth memory bank array 280d, and a write driver for writing data to the first memory bank array 280a to the fourth memory bank array 280d.

Data to be read out from one of the first to fourth memory arrays 280a to 280d may be sensed by a sense amplifier (e.g., 285a) coupled to the one memory array (e.g., 280a) and may be stored in a read data latch. The data stored in the read data latch may be provided to the memory controller 1100 via the data I/O buffer 295 and the data bus/data terminal DQ. Data to be written to one of the first to fourth memory arrays 280a to 280d may be provided to the data I/O buffer 295 via the data bus/data terminal DQ from the memory controller 1100. The data provided to the data I/O buffer 295 received through the data bus/data terminal DQ may be written to one of the memory arrays (e.g., 280a) by a write driver.

The control logic circuit 210 may control the operation of the core die CD1. For example, the control logic circuit 210 may generate a control signal for the core die CD1 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes the command CMD received from the storage controller 1100, and a mode register 212 that sets the operation mode of the core die CD1. For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal (e.g., /WE), a row address strobe signal (e.g., /RAS), a column address strobe signal (e.g., /CAS), a chip select signal (e.g., /CS), etc. The control logic circuit 210 may also receive a clock signal (e.g., CLK) and a clock enable signal (e.g., /CKE) for operating the core die CD1 in a synchronous manner.

6A is a diagram showing a first connection state of a path selector disposed on the buffer die BD of FIG. 2 according to an exemplary embodiment of the inventive concept. FIG. 6B is a diagram showing a second connection state of a path selector disposed on the buffer die BD of FIG. 2 according to an exemplary embodiment of the inventive concept.

1 to 6B, the buffer die BD may include a plurality of buffers. The buffer is connected to the channel paths CP1 to CP16, and outputs the data signal DQ transmitted through the channel paths CP1 to CP16 to the channels CH1 to CH16. The buffer die BD may include path selectors MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, MUX7, and MUX8 for changing the connection between the channels CH1 to CH16 and the channel paths CP1 to CP16. For example, the path selectors MUX1 to MUX8 may be multiplexers. The storage controller 1100 may output a connection control signal for changing the state of the path selectors MUX1 to MUX8 to the path selectors MUX1 to MUX8.

The path selectors MUX1 to MUX8 can set the connection between the channels CH1 to CH16 and the channel paths CP1 to CP16 to the first connection state in the normal operation mode. In other words, the path selectors MUX1 to MUX8 can set the connection between the channels CH1 to CH16 and the channel paths CP1 to CP16 to the first connection state in the first operation mode.

When an error of the memory system 1000 occurs in the first connection state, the memory controller 1100 detects the error of the memory system 1000 .

Then, the storage controller 1100 outputs a connection control signal to the path selectors MUX1 to MUX8 so that the connection between the channels CH1 to CH16 and the channel paths CP1 to CP16 is changed from the first connection state to the second connection state. In other words, when an error occurs, the connection state is changed. The storage controller 1100 detects an error of the storage system 1000 in the second connection state of the channels CH1 to CH16 and the channel paths CP1 to CP16.

When an error is detected at the same channel path in the first connection state and the second connection state, the memory controller 1100 may determine that the error of the memory system 1000 is an error of the channel path. In other words, when an error occurs in the first channel path CP1 in both the first connection state and the second connection state, it is determined that the error occurs in the first channel path CP1.

When errors are detected at different channel paths in the first connection state and the second connection state, the memory controller 1100 may determine that the error of the memory system 1000 is an error of a channel of the memory device 1200 .

2, 6A, and 6B, in the present exemplary embodiment, the memory device 1200 may include four core dies CD1 to CD4, and each of the core dies CD1 to CD4 may include four channels among channels CH1 to CH16. In addition, in the present exemplary embodiment, each of the path selectors MUX1 to MUX8 may be connected to two channels, and each of the path selectors MUX1 to MUX8 may be connected to two channels adjacent to each other in the same core die. Therefore, the memory device 1200 may include eight path selectors MUX1 to MUX8.

Although the memory device 1200 includes four core dies in the present exemplary embodiment, the inventive concept is not limited thereto. In addition, although each core die includes four channels in the present exemplary embodiment, the inventive concept is not limited thereto.

For example, the first core die CD1 includes a first channel CH1 and a second channel CH2. The first path selector MUX1 is connected to the first channel CH1 and the second channel CH2. Referring to FIG6A , the first path selector MUX1 connects the first channel CH1 to the first channel path CP1 in a first connection state, and connects the second channel CH2 to the second channel path CP2. Referring to FIG6B , the first path selector MUX1 connects the first channel CH1 to the second channel path CP2 in a second connection state, and connects the second channel CH2 to the first channel path CP1.

When a first error is detected at the first channel path CP1 connected to the first channel CH1 in the first connection state and the first error is detected at the first channel path CP1 connected to the second channel CH2 in the second connection state, the memory controller 1100 may determine that an error occurs at the first channel path CP1.

In other words, when an error is detected in the same channel path, even though the channel path is switched to a different channel in real time, it can be determined that the error occurs at the channel path (not the channel).

For example, the channel path error may be caused by an error in the data signal sent to the channel of the storage device 1200, or by distortion of the data signal caused by crosstalk between adjacent channel paths. For example, the channel path error may also be caused by distortion of the data signal caused by bridging between adjacent channel paths. For example, the channel path error may be caused by distortion of the data signal caused by an error in the pin between the storage controller 1100 and the channel path.

When an error occurs at a channel path, the error of the channel path can be repaired using the repair channel path RP in the inserter 1300.

When a second error is detected at a first channel path CP1 connected to the first channel CH1 in a first connection state, and the second error is detected at a second channel path CP2 connected to the first channel CH1 in a second connection state, the storage controller 1100 may determine that an error occurs at a channel of the storage device 1200 .

In other words, when an error is detected at a different channel path due to real-time switching of the channel path, it is determined that the error occurs at the channel (not the channel path).

For example, the error of the channel may be a read error and/or a write error generated at a storage cell of the channel. For example, the error of the channel may be a retention error generated at a storage cell of the channel. For example, the error of the channel may be a signal transmission error generated at a storage cell of the channel.

When an error occurs at a channel, the error of the channel may be repaired using a repair cell and a repair line formed in the channel.

For example, the first core die CD1 includes a third channel CH3 and a fourth channel CH4. The second path selector MUX2 is connected to the third channel CH3 and the fourth channel CH4. As shown in FIG6A , the second path selector MUX2 connects the third channel CH3 to the third channel path CP3 in the first connection state, and connects the fourth channel CH4 to the fourth channel path CP4. As shown in FIG6B , the second path selector MUX2 connects the third channel CH3 to the fourth channel path CP4 in the second connection state, and connects the fourth channel CH4 to the third channel path CP3.

When a first error is detected at the third channel path CP3 connected to the third channel CH3 in the first connection state, and the first error is detected at the third channel path CP3 connected to the fourth channel CH4 in the second connection state, the storage controller 1100 can determine that the error occurs at the third channel path CP3.

When a second error is detected at the third channel path CP3 connected to the third channel CH3 in the first connection state, and the second error is detected at the fourth channel path CP4 connected to the third channel CH3 in the second connection state, the storage controller 1100 can determine that an error occurs at a channel of the storage device 1200.

As shown in FIGS. 6A and 6B , the third to eighth path selectors MUX3 to MUX8 may operate in the same manner as the first and second path selectors MUX1 and MUX2 .

According to the present exemplary embodiment, when an error of the storage system 1000 is detected in a first connection state of the channels CH1 to CH16 and the channel paths CP1 to CP16 of the storage device 1200, the connection state of the channels CH1 to CH16 and the channel paths CP1 to CP16 is changed from the first connection state to the second connection state, and the error of the storage system 1000 is detected again in the second connection state of the channels CH1 to CH16 and the channel paths CP1 to CP16. Therefore, it can be determined whether the error of the storage system is an error of the channels or an error of the channel paths of the storage device 1200. In addition, the error of the storage system 1000 can be determined in an actual workload system without transferring the storage system 1000 to an independent error determination system.

Fig. 7A is a diagram showing a first connection state of path selectors MUX1 to MUX8 provided on the buffer die BD of Fig. 2 according to an exemplary embodiment of the inventive concept. Fig. 7B is a diagram showing a second connection state of path selectors MUX1 to MUX8 provided on the buffer die BD of Fig. 2 according to an exemplary embodiment of the inventive concept.

1 to 5, 7A, and 7B, in the present exemplary embodiment, the memory device 1200 may include four core dies CD1 to CD4, and each of the core dies CD1 to CD4 may include four channels among channels CH1 to CH16. In addition, in the present exemplary embodiment, each of the path selectors MUX1 to MUX8 may be connected to two channels, and each of the path selectors MUX1 to MUX8 may be connected to two channels located in different core dies. Therefore, the memory device 1200 may include eight path selectors MUX1 to MUX8.

For example, the first core die CD1 includes a first channel CH1, and the second core die CD2 includes a fifth channel CH5. The first path selector MUX1 is connected to the first channel CH1 and the fifth channel CH5. As shown in FIG7A, the first path selector MUX1 connects the first channel CH1 to the first channel path CP1 in a first connection state, and connects the fifth channel CH5 to the fifth channel path CP5. As shown in FIG7B, the first path selector MUX1 connects the first channel CH1 to the fifth channel path CP5 in a second connection state, and connects the fifth channel CH5 to the first channel path CP1.

When a first error is detected at the first channel path CP1 connected to the first channel CH1 in the first connection state and the first error is detected at the first channel path CP1 connected to the fifth channel CH5 in the second connection state, the memory controller 1100 may determine that an error occurs at the first channel path CP1.

When a second error is detected at the first channel path CP1 connected to the first channel CH1 in the first connection state, and the second error is detected at the fifth channel path CP5 connected to the first channel CH1 in the second connection state, the storage controller 1100 can determine that an error occurs at a channel of the storage device 1200.

For example, the third core die CD3 includes a ninth channel CH9, and the fourth core die CD4 includes a thirteenth channel CH13. The second path selector MUX2 is connected to the ninth channel CH9 and the thirteenth channel CH13. As shown in FIG7A , the second path selector MUX2 connects the ninth channel CH9 to the ninth channel path CP9 in a first connection state, and connects the thirteenth channel CH13 to the thirteenth channel path CP13. As shown in FIG7B , the second path selector MUX2 connects the ninth channel CH9 to the thirteenth channel path CP13 in a second connection state, and connects the thirteenth channel CH13 to the ninth channel path CP9.

When a first error is detected at a ninth channel path CP9 connected to a ninth channel CH9 in a first connection state, and the first error is detected at a ninth channel path CP9 connected to a thirteenth channel CH13 in a second connection state, the storage controller 1100 may determine that an error occurs at the ninth channel path CP9.

When a second error is detected at a ninth channel path CP9 connected to a ninth channel CH9 in a first connection state, and the second error is detected at a thirteenth channel path CP13 connected to the ninth channel CH9 in a second connection state, the storage controller 1100 may determine that an error occurs at a channel of the storage device 1200.

As shown in FIGS. 7A and 7B , the third to eighth path selectors MUX3 to MUX8 may operate in the same manner as the first and second path selectors MUX1 and MUX2 .

According to the present exemplary embodiment, an error of the storage system 1000 is detected in the first connection state and the second connection state, so that it is possible to determine whether the error of the storage system is an error of a channel or an error of a channel path of the storage device 1200. In addition, the error of the storage system 1000 can be determined in an actual workload system without transferring the storage system 1000 to an independent error determination system.

In addition, the path selectors MUX1 to MUX8 may be connected to channels of different core dies CD1 to CD4 and the connection states may be switched, so that the reliability of error determination may be improved.

Fig. 8A is a diagram showing a first connection state of path selectors MUX1 to MUX4 disposed on the buffer die BD of Fig. 2 according to an exemplary embodiment of the inventive concept. Fig. 8B is a diagram showing a second connection state of path selectors MUX1 to MUX4 disposed on the buffer die BD of Fig. 2 according to an exemplary embodiment of the inventive concept.

1 to 5, 8A, and 8B, in the present exemplary embodiment, the memory device 1200 may include four core dies CD1 to CD4, and each of the core dies CD1 to CD4 may include four channels among channels CH1 to CH16. In addition, in the present exemplary embodiment, each of the path selectors MUX1 to MUX4 may be connected to four channels, and each of the path selectors MUX1 to MUX4 may be connected to four channels located in the same core die. Therefore, the memory device 1200 may include four path selectors MUX1 to MUX4.

For example, the first core die CD1 includes a first channel CH1 to a fourth channel CH4. The first path selector MUX1 is connected to the first channel CH1 to the fourth channel CH4. As shown in FIG8A , the first path selector MUX1 connects the first channel CH1 to the first channel path CP1, the second channel CH2 to the second channel path CP2, the third channel CH3 to the third channel path CP3, and the fourth channel CH4 to the fourth channel path CP4 in a first connection state. As shown in FIG8B , the first path selector MUX1 connects the first channel CH1 to the fourth channel path CP4, the second channel CH2 to the third channel path CP3, the third channel CH3 to the second channel path CP2, and the fourth channel CH4 to the first channel path CP1 in a second connection state.

Using the above-described path selectors MUX1 to MUX4 , it is determined whether the error of the storage system 1000 is an error of a channel of the storage device 1200 or an error of a channel path.

It should be understood that in order to improve the reliability of error determination, the first path selector MUX1 can form a third connection state different from the first connection state and the second connection state. For example, the first path selector MUX1 can connect the first channel CH1 to the second channel path CP2, connect the second channel CH2 to the third channel path CP3, connect the third channel CH3 to the fourth channel path CP4, and connect the fourth channel CH4 to the first channel path CP1 in the third connection state.

As shown in FIGS. 8A and 8B , the second to fourth path selectors MUX2 to MUX4 may operate in the same manner as the first path selector MUX1 .

According to the present exemplary embodiment, an error of the storage system 1000 is detected in the first connection state and the second connection state, so that it is possible to determine whether the error of the storage system 1000 is an error of a channel or an error of a channel path of the storage device 1200. In addition, the error of the storage system 1000 can be determined in an actual workload system without transferring the storage system 1000 to an independent error determination system.

In addition, the path selector (eg, MUX1, MUX2, MUX3, or MUX4) may also detect an error of the storage system 1000 in the third connection state, thereby improving reliability of error determination.

9A is a diagram showing a first connection state of path selectors MUX1 and MUX2 disposed on the buffer die BD of FIG. 2 according to an exemplary embodiment of the inventive concept. FIG. 9B is a diagram showing a second connection state of path selectors MUX1 and MUX2 disposed on the buffer die BD of FIG. 2 according to an exemplary embodiment of the inventive concept.

1 to 5, 9A and 9B, in the present exemplary embodiment, the memory device 1200 may include four core dies CD1 to CD4, and each of the core dies CD1 to CD4 may include four channels among channels CH1 to CH16. In addition, in the present exemplary embodiment, each of the path selectors MUX1 and MUX2 may be connected to eight channels, and each of the path selectors MUX1 and MUX2 may be connected to four adjacent channels in the same core die and four adjacent channels in an adjacent core die. Therefore, the memory device 1200 may include two path selectors MUX1 and MUX2.

For example, the first core die CD1 includes the first channel CH1 to the fourth channel CH4, and the second core die CD2 includes the fifth channel CH5 to the eighth channel CH8. The first path selector MUX1 is connected to the first channel CH1 to the eighth channel CH8. As shown in FIG9A , the first path selector MUX1 connects the first channel CH1 to the first channel path CP1, connects the second channel CH2 to the second channel path CP2, connects the third channel CH3 to the third channel path CP3, connects the fourth channel CH4 to the fourth channel path CP4, connects the fifth channel CH5 to the fifth channel path CP5, connects the sixth channel CH6 to the sixth channel path CP6, connects the seventh channel CH7 to the seventh channel path CP7, and connects the eighth channel CH8 to the eighth channel path CP8 in the first connection state.

As shown in FIG. 9B , the first path selector MUX1 connects the first channel CH1 to the eighth channel path CP8, connects the second channel CH2 to the seventh channel path CP7, connects the third channel CH3 to the sixth channel path CP6, connects the fourth channel CH4 to the fifth channel path CP5, connects the fifth channel CH5 to the fourth channel path CP4, connects the sixth channel CH6 to the third channel path CP3, connects the seventh channel CH7 to the second channel path CP2, and connects the eighth channel CH8 to the first channel path CP1 in the second connection state.

Using the above-described path selectors MUX1 and MUX2 , it can be determined whether the error of the storage system 1000 is an error of a channel of the storage device 1200 or an error of a channel path.

It should be understood that in order to improve the reliability of error determination, the first path selector MUX1 may form a third connection state different from the first connection state and the second connection state.

As shown in FIGS. 9A and 9B , the second path selector MUX2 may operate in the same manner as the first path selector MUX1 .

According to the present exemplary embodiment, an error of the storage system 1000 is detected in the first connection state and the second connection state, so that it is possible to determine whether the error of the storage system 1000 is an error of a channel or an error of a channel path of the storage device 1200. In addition, the error of the storage system 1000 can be determined in an actual workload system without transferring the storage system 1000 to an independent error determination system.

In addition, the path selector (eg, MUX1 or MUX2) may also detect an error of the storage system 1000 in the third connection state, thereby improving the reliability of error determination.

In addition, path selectors (eg, MUX1 and MUX2) may be connected to channels of different core dies and may switch connection states, thereby making it possible to improve reliability of error determination.

Fig. 10A is a diagram illustrating a first connection state of a path selector MUX1 disposed on a buffer die BD of Fig. 2 according to an exemplary embodiment of the inventive concept. Fig. 10B is a diagram illustrating a second connection state of a path selector MUX1 disposed on a buffer die BD of Fig. 2 according to an exemplary embodiment of the inventive concept.

1 to 5, 10A, and 10B, in the present exemplary embodiment, the memory device 1200 may include four core dies CD1 to CD4, and each of the core dies CD1 to CD4 may include four channels of channels CH1 to CH16. In addition, the path selector MUX1 may be connected to all channels CH1 to CH16. Therefore, the memory device 1200 may include one path selector MUX1.

For example, the first path selector MUX1 is connected to the first to sixteenth channels CH1 to CH16. As shown in FIG. 10A, the first path selector MUX1 may sequentially connect the first to sixteenth channels CH1 to CH16 to the first to sixteenth channel paths CP1 to CP16 in a first connection state.

As shown in FIG. 10B , the first path selector MUX1 may sequentially connect the first to sixteenth channels CH1 to CH16 to the sixteenth channel path CP16 to the first channel path CP1 in the second connection state.

By using the path selector MUX1, it can be determined whether the error of the storage system 1000 is an error of a channel of the storage device 1200 or an error of a channel path.

It should be understood that in order to improve the reliability of error determination, the first path selector MUX1 may form various connection states different from the first connection state and the second connection state.

According to the present exemplary embodiment, an error of the storage system 1000 is detected in the first connection state and the second connection state, so that it can be determined whether the error of the storage system 1000 is an error of a channel or an error of a channel path of the storage device 1200. In addition, the error of the storage system 1000 can be determined in an actual workload system without transferring the storage system 1000 to an independent error determination system.

In addition, the path selector MUX1 can also detect errors of the storage system 1000 in various connection states different from the first connection state and the second connection state, so that the reliability of error determination can be improved.

In addition, the path selector MUX1 may be connected to channels of different core dies and may switch a connection state, so that reliability of error determination may be improved.

FIG. 11 is a diagram showing a storage system 1000 according to an exemplary embodiment of the inventive concept. FIG. 12A is a diagram showing a first connection state of path selectors MUX1 to MUX16 disposed on a buffer die BD of FIG. 11 according to an exemplary embodiment of the inventive concept. FIG. 12B is a diagram showing a second connection state of path selectors MUX1 to MUX16 disposed on a buffer die BD of FIG. 11 according to an exemplary embodiment of the inventive concept. FIG. 12C is a diagram showing a third connection state of path selectors MUX1 to MUX16 disposed on a buffer die BD of FIG. 11 according to an exemplary embodiment of the inventive concept.

The storage system according to the present exemplary embodiment is substantially the same as the storage system of the aforementioned exemplary embodiment described with reference to FIGS. 1 to 10B , except that the storage device of the present exemplary embodiment further includes a reference channel. Therefore, the same reference numerals will be used to represent the same or similar components as those described in the exemplary embodiment of FIGS. 1 to 10B . Any repeated description of the above elements may be omitted.

11 to 12C , the memory system 1000 includes a memory controller 1100 and a memory device 1200. The memory system 1000 may further include an interposer 1300 for connecting the memory controller 1100 and the memory device 1200.

The memory device 1200 may include a plurality of channels CH1 to CH16. The memory device 1200 may further include a reference channel. The interposer 1300 may further include a reference channel path for connecting the reference channel to the memory controller 1100. For example, the memory device 1200 may include a plurality of reference channels RCH1, RCH2, RCH3, and RCH4. For example, each of the core dies CD1 to CD4 includes a reference channel. For example, the first core die CD1 disposed on the buffer die BD may include the first channel CH1 to the fourth channel CH4 and the first reference channel RCH1. For example, the second core die CD2 disposed on the first core die CD1 may include the fifth channel CH5 to the eighth channel CH8 and the second reference channel RCH2. For example, the third core die CD3 disposed on the second core die CD2 may include the ninth channel CH9 to the twelfth channel CH12 and the third reference channel RCH3. For example, the fourth core die CD4 disposed on the third core die CD3 may include the thirteenth channel CH13 to the sixteenth channel CH16 and the fourth reference channel RCH4.

The error rate of the reference channels RCH1 to RCH4 may be lower than that of the channels CH1 to CH16. For example, the reference channels RCH1 to RCH4 may pass a stricter reliability test in a manufacturing step of the memory device 1000 than the channels CH1 to CH16.

In the present exemplary embodiment, the memory device 1200 may include four core dies CD1 to CD4, and each of the core dies CD1 to CD4 may include four channels of channels CH1 to CH16. Each of the core dies CD1 to CD4 may include reference channels RCH1, RCH2, RCH3, or RCH4, respectively. In addition, in the present exemplary embodiment, each of the path selectors MUX1 to MUX16 may be connected to one channel and one reference channel, and each of the path selectors MUX1 to MUX16 may be connected to one channel and one reference channel in the same core die. Therefore, the memory device 1200 may include sixteen path selectors MUX1 to MUX16.

Although the storage device 1200 includes four core dies CD1 to CD4 in the present exemplary embodiment, the inventive concept is not limited thereto. In addition, although each of the core dies CD1 to CD4 includes four channels in the present exemplary embodiment, the inventive concept is not limited thereto. In addition, although each of the core dies CD1 to CD4 includes one reference channel in the present exemplary embodiment, the inventive concept is not limited thereto. Alternatively, at least one of the core dies CD1 to CD4 may include a plurality of reference channels. Alternatively, the number of reference channels may be less than the number of core dies, and therefore, at least one of the core dies may not include a reference channel.

For example, the first core die CD1 includes the first channel CH1 to the fourth channel CH4. The first path selector MUX1 is connected to the first channel CH1 and the first reference channel RCH1. As shown in FIG12A, the first path selector MUX1 connects the first channel CH1 to the first channel path CP1 in a first connection state, and connects the first reference channel RCH1 to the first reference channel path RCP1. As shown in FIG12B, the first path selector MUX1 connects the first channel CH1 to the first reference channel path RCP1 in a second connection state, and connects the first reference channel RCH1 to the first channel path CP1.

The second path selector MUX2 is connected to the second channel CH2 and the first reference channel RCH1. As shown in FIG12A, the second path selector MUX2 connects the second channel CH2 to the second channel path CP2 and connects the first reference channel RCH1 to the first reference channel path RCP1 in the first connection state. As shown in FIG12C, the second path selector MUX2 connects the second channel CH2 to the first reference channel path RCP1 and connects the first reference channel RCH1 to the second channel path CP2 in the third connection state.

Using the above path selectors MUX1 and MUX2, it can be determined whether the error of the memory system 1000 is an error of a channel or a channel path of the memory device 1200. In this exemplary embodiment, the error of the memory system 1000 is determined using reference channels RCH1 to RCH4 having higher reliability than channels CH1 to CH16.

As shown in FIGS. 12A and 12B , the third to sixteenth path selectors MUX3 to MUX16 may operate in the same manner as the first and second path selectors MUX1 and MUX2 .

According to the present exemplary embodiment, an error of the storage system 1000 is detected in the first connection state and the second connection state, so that it is possible to determine whether the error of the storage system 1000 is an error of a channel or an error of a channel path of the storage device 1200. In addition, the error of the storage system 1000 can be determined in an actual workload system without transferring the storage system 1000 to an independent error determination system.

In addition, the memory device 1200 uses the reference channels RCH1 to RCH4 having higher data reliability than the channels CH1 to CH16 , so that the reliability of error determination can be improved.

FIG. 13 is a block diagram illustrating an electronic device 2000 including a memory system according to an exemplary embodiment of the inventive concept.

1 to 13 , the electronic device 2000 includes an application processor 2100, a connection circuit 2200, a memory system (VM) 2300, a nonvolatile memory system (NVM) 2400, a user interface 2500, and a power supply 2600 that communicate via a bus. For example, the electronic device 2000 may be a mobile device.

The application processor 2100 may execute applications such as a web browser, a game application, a video player, etc. The connection circuit 2200 may perform wired or wireless communication with an external device. The non-volatile storage system 2400 may store a startup image for starting the electronic device 2000. The user interface 2500 may include at least one input device (e.g., a keyboard, a touch screen, etc.) and at least one output device (e.g., a speaker, a display device, etc.). The power supply 2600 may provide a power supply voltage to the electronic device 2000. The storage system 2300 may store data processed by the application processor 2100, or may be used as a working memory. As described above with reference to the exemplary embodiments of the inventive concept, the storage system 2300 may change the connection state between the channel and the channel path in real time, thereby performing error determination.

The above-mentioned embodiments can be used in storage systems, various devices or systems including storage systems, such as mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable camcorders, digital televisions, set-top boxes, music players, portable game consoles, navigation devices, personal computers (PCs), server computers, workstations, tablet computers, notebook computers, smart cards, printers, wearable systems, Internet of Things (IoT) systems, virtual reality (VR) systems, augmented reality (AR) systems, etc.

In a storage system, a method for determining an error of a storage system, and an electronic device including the storage system according to exemplary embodiments of the present invention, an error of the storage system is detected in a first connection state between a channel of a storage device and a channel path connecting the channel of the storage device to a storage controller; the first connection state between the channel and the channel path is changed to a second connection state; and an error of the storage system is detected in the second connection state between the channel and the channel path, so that it can be determined whether the error occurs in the storage device or in the channel path.

In addition, the storage system according to the exemplary embodiment of the inventive concept does not need to be transferred to an independent error determination system. The error of the storage system can be determined in the actual workload system without transferring the storage system to an independent error determination system.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made to these exemplary embodiments without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims (20)

1. A storage system, comprising:

A memory device including a buffer die, a plurality of core dies disposed on the buffer die, a plurality of channels, and a through silicon via configured to transmit signals between the buffer die and at least one core die of the plurality of core dies;

A memory controller configured to output command signals and address signals to the memory device, output data signals to the memory device, and receive data signals from the memory device; and

An interposer including a plurality of channel paths for connecting the memory controller and the plurality of channels,

Wherein the memory device further comprises a path selector for changing a connection state between the plurality of channels and the plurality of channel paths,

Wherein when an error of the memory system is detected in a first connection state between the plurality of channels and the plurality of channel paths, the path selector changes the first connection state between the plurality of channels and the plurality of channel paths to a second connection state, and detects an error of the memory system in the second connection state to determine whether the error of the memory system is an error of a channel or an error of a channel path, and

Wherein all connections between the plurality of channels and the plurality of channel paths in the first connection state are different from all connections between the plurality of channels and the plurality of channel paths in the second connection state.

2. The storage system of claim 1, further comprising a package substrate,

Wherein the memory device and the memory controller are disposed on the interposer, an

Wherein the interposer is disposed on the package substrate.

3. The memory system of claim 1, wherein the buffer die is connected to the plurality of channel paths,

Wherein the buffer die comprises a plurality of buffers, wherein the plurality of buffers are configured to output data signals transmitted through at least one of the plurality of channel paths to at least one of the plurality of channels, and

Wherein the plurality of core dies includes the plurality of channels.

4. The memory system of claim 3, wherein the path selector is disposed on the buffer die.

5. The memory system of claim 3, wherein a first core die disposed on the buffer die comprises a first channel and a second channel,

Wherein the path selector is configured to connect the first channel to a first channel path and the second channel to a second channel path in the first connection state, and

Wherein the path selector is configured to connect the first channel to the second channel path and connect the second channel to the first channel path in the second connection state.

6. The memory system of claim 3, wherein a first core die disposed on the buffer die comprises a first channel and a second core die disposed on the first core die comprises a second channel,

Wherein the path selector is configured to connect the first channel to a first channel path and the second channel to a second channel path in the first connection state, and

Wherein the path selector is configured to connect the first channel to the second channel path and connect the second channel to the first channel path in the second connection state.

7. The memory system of claim 3, wherein the first core die disposed on the buffer die comprises a first channel, a second channel, a third channel, and a fourth channel,

Wherein the path selector is configured to connect the first channel to a first channel path, the second channel to a second channel path, the third channel to a third channel path, and the fourth channel to a fourth channel path in the first connection state, and

Wherein the path selector is configured to connect the first channel to the fourth channel path, the second channel to the third channel path, the third channel to the second channel path, and the fourth channel to the first channel path in the second connection state.

8. The memory system of claim 3, wherein the path selector is connected to all of the plurality of channels of the plurality of core dies.

9. The memory system of claim 3, wherein the memory device further comprises a reference channel having an error rate that is less than the error rates of the plurality of channels, and

Wherein the interposer further comprises a reference channel path.

10. The storage system of claim 9, wherein the path selector comprises:

A first path selector connected to a first channel and the reference channel; and

A second path selector connected to the second channel and the reference channel.

11. The memory system of claim 10, wherein the first path selector is configured to connect the first channel to a first channel path and the reference channel to the reference channel path in the first connection state,

Wherein the first path selector is configured to connect the first channel to the reference channel path and connect the reference channel to the first channel path in the second connection state,

Wherein the second path selector is configured to connect the second channel to a second channel path and the reference channel to the reference channel path in the first connection state, and

Wherein the second path selector is configured to connect the second channel to the reference channel path and connect the reference channel to the second channel path in the second connection state.

12. A method of determining an error of a storage system comprising a storage device and a storage controller, the method comprising:

Detecting an error of the memory system in a first connection state between a plurality of channels of the memory device and a plurality of channel paths of the memory system, the plurality of channel paths connecting the plurality of channels to the memory controller, the memory device including a buffer die, a plurality of core dies disposed on the buffer die, and a through-silicon via configured to send a signal between at least one of the plurality of core dies and the buffer die;

Changing a connection state between the plurality of channels and the plurality of channel paths from the first connection state to a second connection state when an error of the storage system is detected; and

Detecting an error of the memory system in the second connection state to determine whether the error of the memory system is an error of a channel or an error of a channel path,

Wherein all connections between the plurality of channels and the plurality of channel paths in the first connection state are different from all connections between the plurality of channels and the plurality of channel paths in the second connection state.

13. The method of claim 12, the method further comprising: when a first error is detected at a first channel path connected to a first channel in the first connection state and the first error is detected at the first channel path connected to a second channel in the second connection state, it is determined that the error of the storage system is an error of the first channel path.

14. The method of claim 13, the method further comprising: when a second error is detected at the first channel path connected to the first channel in the first connection state and the second error is detected at the second channel path connected to the first channel in the second connection state, determining that the error of the storage system is an error of the first channel.

15. The method of claim 12, wherein the buffer die is connected to the plurality of channel paths,

Wherein the buffer die comprises a plurality of buffers, wherein the plurality of buffers are configured to output data signals transmitted through at least one of the plurality of channel paths to at least one of the plurality of channels, and

Wherein the plurality of core dies are disposed on the buffer die, wherein the plurality of core dies include the plurality of channels.

16. The method of claim 15, wherein a path selector configured to change a connection state between the plurality of channels and the plurality of channel paths is disposed on the buffer die.

17. The method of claim 16, wherein a first core die disposed on the buffer die includes a first channel and a second channel,

Wherein the path selector is configured to connect the first channel to a first channel path and the second channel to a second channel path in the first connection state, and

Wherein the path selector is configured to connect the first channel to the second channel path and connect the second channel to the first channel path in the second connection state.

18. The method of claim 16, wherein a first core die disposed on the buffer die includes a first channel and a second core die disposed on the first core die includes a second channel,

Wherein the path selector is configured to connect the first channel to a first channel path and the second channel to a second channel path in the first connection state, and

Wherein the path selector is configured to connect the first channel to the second channel path and connect the second channel to the first channel path in the second connection state.

19. The method of claim 16, wherein the memory device further comprises a reference channel having an error rate that is less than the error rates of the plurality of channels, the memory system further comprising a reference channel path,

Wherein the path selector comprises:

A first path selector connected to a first channel and the reference channel; and

A second path selector connected to the second channel and the reference channel,

Wherein the first path selector is configured to connect the first channel to a first channel path and the reference channel to the reference channel path in the first connection state,

Wherein the first path selector is configured to connect the first channel to the reference channel path and connect the reference channel to the first channel path in the second connection state,

Wherein the second path selector is configured to connect the second channel to a second channel path and the reference channel to the reference channel path in the first connection state, and

Wherein the second path selector is configured to connect the second channel to the reference channel path and connect the reference channel to the second channel path in the second connection state.

20. An electronic device, comprising:

an application processor; and

A storage system configured to be operated by the application processor,

Wherein the storage system comprises:

A memory device including a buffer die, a plurality of core dies disposed on the buffer die, a plurality of channels, and a through silicon via configured to transmit signals between at least one of the plurality of core dies and the buffer die;

A memory controller configured to output command signals and address signals to the memory device, output data signals to the memory device, and receive data signals from the memory device; and

An interposer including a plurality of channel paths for connecting the memory controller and the plurality of channels,

Wherein the memory device further comprises a path selector for changing a connection state between the plurality of channels and the plurality of channel paths,

Wherein when an error of the memory system is detected in a first connection state between the plurality of channels and the plurality of channel paths, the path selector changes the first connection state between the plurality of channels and the plurality of channel paths to a second connection state, and detects an error of the memory system in the second connection state to determine whether the error of the memory system is an error of a channel or an error of a channel path, and

Wherein all connections between the plurality of channels and the plurality of channel paths in the first connection state are different from all connections between the plurality of channels and the plurality of channel paths in the second connection state.