CN110108919A - The measurement method of PPD pinning voltage in a kind of pixel - Google Patents

Abstract

The invention discloses a method for measuring the PPD pinning voltage in a pixel, which is implemented on a 4T pixel structure, n+ is doped at the TD node position on the side of the pixel PPD away from the FD node to change the potential distribution in the pixel, and the M1 tube is set as a charge injection gate. Tube, during the pinning voltage test process, in the charge injection stage, the M1 tube is gated, by injecting charge at the TD node, adjusting the injection voltage V _inj to measure the output voltage V _out , obtaining the V _out ‑V _inj curve and extracting the pinning voltage from it, by The injected voltage V _inj achieves the measured pinnig voltage V _pin . The invention overcomes the problems existing in the JFET PPD test structure. During the pinnig voltage test process, the charge is injected into the TD node to extract the pinning voltage. Compared with the injection from the FD node, the test process will not be affected by the TG voltage.

Description

A method for measuring PPD pinning voltage in a pixel

technical field

The invention relates to the technical field of integrated circuits, in particular to a method for measuring PPD pinning voltage in a pixel.

Background technique

The pinning voltage in the pixel PPD is usually defined as the maximum potential of the PPD under the condition of complete depletion, which is one of the important parameters reflecting the pixel performance of the CMOS image sensor. Extracting the pinnig voltage provides a reference for correctly adjusting transfer gate potential, FD node to optimize full well capacity and charge transfer efficiency.

Existing methods for extracting the pinnig voltage mainly include using an isolated JFET PPD test structure and an in-pixel test method of injecting charge from the FD node. The JFET PPD test method uses an isolated test structure, but the structure is quite different from the actual pixel structure, which reduces the reliability of the test results; the method of injecting charges from the FD node, the test results are easily affected by the TG voltage.

Contents of the invention

The purpose of the present invention is to provide a method for measuring the PPDpinning voltage in the pixel in view of the technical defects in the prior art. This test method will not be affected by the TG voltage during the charge injection process, and under the designed timing, This pixel structure can work like a normal 4T pixel.

The technical scheme adopted for realizing the purpose of the present invention is:

A method for measuring the PPD pinning voltage in a pixel, implemented on a 4T pixel structure, doping n+ at the TD node on the side of the pixel PPD away from the FD node to change the potential distribution in the pixel, setting the M1 tube as a charge injection gate tube, and M2 The tube is the reset tube RST of the FD node, the M3 tube is the source follower SF, and the M4 tube is the pixel selection tube SEL; the source terminal of the M1 tube is connected to the TD node, and the drain terminal is connected to the V _DD power supply; the source terminal of the M2 tube is connected to the FD The node is connected to the gate of the M3 tube, the drain terminal is connected to the power supply voltage V _DD , the drain terminal of the M3 tube is connected to the power supply VDD, and the source terminal is connected to the drain terminal of the M4 tube;

During the pinning voltage test, in the charge injection stage, the M1 tube is gated, and by injecting charge at the TD node, adjusting the injection voltage V _inj to measure the output voltage V _out to obtain the V _out -V _inj curve and extract the pinning voltage from it, through the injection voltage _Vinj implements the measured pinnig voltage V _pin .

When the output voltage V _out is exactly 0, the corresponding injection voltage V _inj is the pinnig voltage V _pin .

Compared with prior art, the beneficial effect of the present invention is:

The present invention overcomes the problems existing in the JFET PPD test structure; and during the pinnig voltage test process, charge injection is performed at the TD node on the side away from the FD node, and by adjusting the injection voltage V _inj and measuring the corresponding output, V _out -V is obtained _inj curve, and extract the pinning voltage from it. Compared with the method of injecting from the FD node, the pixel test structure will not be affected by the TG voltage during the test.

Description of drawings

Figure 1 shows the pixel test structure;

Figure 2 shows a schematic diagram of the potential distribution;

Figure 3 shows the timing sequence of the pinnig voltage test, where V _inj is the injection voltage during the charge injection stage during the pinnig voltage test;

FIG. 4 shows the normal operation timing of the pixel, wherein, V _inj0 is the injection voltage during the charge injection stage during the normal operation of the pixel, V _inj0 =V _pin ;

Figures 5a-5c are schematic diagrams of potentials of signal charges in three stages of charge injection, charge transmission and signal readout under the conditions of V _inj >V _pin , V _inj =V _pin and V _inj <V _pin respectively;

Fig. 6 shows the V _out -V _inj curve, wherein V _pin is the value of V _inj when V _out happens to be 0.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

The present invention is realized on the basis of the 4T pixel structure, n+ doping (TD node) is performed on the side of the pixel PPD away from the FD node to change the potential distribution in the pixel, and an M1 tube is added as a gate tube for charge injection. The specific structure of the pixel is shown in the figure As shown in 1, in the case of complete depletion, the potential distribution in the pixel is shown in Figure 2. The connections of the tubes in the pixel are as follows: M1 is the switch tube SW, M2 is the reset tube RST of the FD node, and M3 is the source follower SF, M4 is the pixel gate tube SEL. The source terminal of M1 is connected to the TD node (the test diode node test diode, which is used to store the injected charge for measuring the pinning voltage), the drain terminal is connected to the V _DD power supply, the source terminal of M2 is connected to the FD node and the gate of M3, and the drain terminal connected to the power supply voltage V _DD , the drain terminal of M3 is connected to the power supply VDD, and the source terminal is connected to the drain terminal of M4.

The pinning voltage test timing and the pixel normal working timing are shown in Figure 3 and Figure 4 respectively. During the test, the M1 tube is gated during the charge injection stage. By adjusting the injection voltage V _inj and measuring the corresponding output voltage V _out , the V _out -V _inj curve is obtained as shown in Figure 6. In the curve, when V _out is exactly 0 , and the corresponding V _inj is the pinnig voltage V _pin .

(1) pinnig voltage test process:

As shown in Figure 2, in the charge injection phase, V _DD is reduced to V _inj , during the pinnig voltage test process, the M1 tube is gated, and the charge is injected into the TD node; in the readout phase, during the M4 tube gating process, M2 Tube and M3 tubes are respectively gated to read the signal charge in the FD area; in the reset phase, the M2 tube is gated to reset the FD area, and the M1 tube is gated to reset the TD area and the PPD area.

During the test, under a certain injection time, V _inj is changed, and the corresponding output voltage is measured. The transfer process of charge in the pixel is divided into three cases, as shown in Fig. 5a-5c.

When V _inj >V _pin , as shown in Figure 5a, the TD potential is greater than the PPD potential and cannot enter the PPD. During the turn-on process of the transmission tube TG, the charge cannot be transferred from the PPD and TD regions to the FD, so the output voltage is 0;

When V _inj =V _pin , as shown in Figure 5b, the TD potential is exactly equal to the PPD potential, and the charge cannot be transferred to the FD region during the turn-on process of the transmission tube TG, so the output voltage is still 0;

When V _inj < V _pin , as shown in Figure 5c, the TD potential is less than the maximum potential of PPD. During the turn-on process of the transfer tube TG, the charge with potential less than V pin is transferred from the PPD and TD regions to FD, so the output voltage is not 0. .

Therefore, in FIG. 6 , in the V _out -V _inj curve, when V _out is exactly 0, the corresponding V _inj is the pinnig voltage V _pin .

(2) Normal working process:

As shown in FIG. 3 , in the charge injection stage, V _DD is set to V _inj0 (V _inj0 =V _pin ), during which the M1 transistor is turned on, and charges are injected into the TD node. At this time, the TD area is just filled with charges, the situation is the same as that in Figure 5b. The injection is only performed at the initial stage, and the exposure, readout, and reset processes are the same as the traditional 4T pixel working process. In the readout phase, during the selection process of the M4 tube, the M2 tube and the M3 tube are respectively selected to read out the signal charges in the FD area; in the reset phase, the M2 tube and the transmission tube TG are simultaneously selected to reset the PPD and FD areas.

The pixel test structure can work like a normal pixel under the design timing, which overcomes the problems existing in the JFET PPD test structure; and during the pinnig voltage test process, the charge injection is performed at the TD node on the side away from the FD node, and by adjusting the injection Voltage V _inj and measure the corresponding output to obtain the V _out -V _inj curve, and extract the pinning voltage from it. Compared with the method of injecting from the FD node, the pixel test structure will not be affected by the transmission tube TG voltage during the test influences.

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, these improvements and Retouching should also be regarded as the protection scope of the present invention.

Claims (2)

1. the measurement method of PPD pinning voltage in a kind of pixel, which is characterized in that realized on 4T dot structure, in picture Plain PPD is adulterated far from FD node side TD node location n+ to change the distribution of pixel built-in potential, and setting M1 pipe is injected as charge Gate tube, M2 pipe are that reset transistor RST, the M3 pipe of FD node is source level follower SF, and M4 pipe is pixel gate tube SEL；M1 pipe Source connects TD node, and drain terminal meets V_DDPower supply；The source of M2 pipe connects FD node and M3 tube grid, and drain terminal meets supply voltage V_DD, M3 pipe Drain terminal meet power vd D, source connects the drain terminal of M4 pipe；

During pinning voltage tester, in charge injection stage, M1 pipe gating adjusts note by injecting charge in TD node Enter voltage V_injMeasure output voltage V_out, obtain V_out-V_injCurve simultaneously therefrom extracts pinning voltage, passes through injecting voltage V_inj Realize measurement pinnig voltage V_pin。

2. the measurement method of PPD pinning voltage in pixel as described in claim 1, which is characterized in that as output voltage V_out Exactly 0 when corresponding injecting voltage V_injAs pinnig voltage V_pin。