CN110118599B

CN110118599B - Integrated single photon detection device

Info

Publication number: CN110118599B
Application number: CN201810124836.0A
Authority: CN
Inventors: 惠辉; 刘建宏; 代云启
Original assignee: Quantumctek Co Ltd
Current assignee: Quantumctek Co Ltd
Priority date: 2018-02-07
Filing date: 2018-02-07
Publication date: 2024-07-02
Anticipated expiration: 2038-02-07
Also published as: CN110118599A

Abstract

The utility model provides an integrate single photon detection device, including refrigerating module, temperature sensor module, avalanche photodiode module, narrow pulse signal produces the module, avalanche signal discriminates the module, the IO module, the heat sink, delay circuit, sealed thermal-insulated encapsulation module, the heat sink sets up in refrigerating module's top, avalanche photodiode module sets up in refrigerating module's below and hugs closely refrigerating module, temperature sensor module sets up the side at avalanche photodiode module, delay circuit, narrow pulse signal produces the module, avalanche signal discriminates the module left and right sides and sets gradually and be located avalanche photodiode module's below, IO module sets up the left and right sides at delay circuit and avalanche signal discriminates the module. The integrated single photon detection device has the advantages that: after integration, the microminiaturization of the detector equipment is promoted, and the parasitic parameters of each module of the original independent element scheme are removed through integration, so that the signal quality is improved.

Description

Integrated single photon detection device

Technical Field

The invention relates to the technical field of quantum communication, in particular to an integrated single photon detection device.

Background

In the field of quantum communications, light is used as an information carrier. For improved security, the transmitted light is in the quantum state, i.e. single photon. A single photon detection function module is an essential module of such a communication device. The existing single photon detection scheme is as follows:

1. The avalanche photodiode module requires a low temperature environment for single photon detection. Provided using an aluminum seal box. The box body is sealed, and foam or other heat preservation and insulation materials are filled. Conventional refrigeration modules are used to extract heat from the interior of the cartridge to the cartridge body. A fan is used outside the box body to exchange heat on the box body into air.

2. The avalanche photodiode module needs to operate in an appropriate state to detect single photons. The avalanche photodiode module comprises a driving circuit and a diode D1, wherein a driving plate welded with the driving circuit is positioned in the box body, and the avalanche photodiode D1 is directly welded on the driving plate of the avalanche photodiode module. The driving board inputs an external driving signal and outputs the detected original photon signal. The drive board outputs the temperature signal of the temperature sensor module attached to the avalanche photodiode module housing.

3. And the avalanche signal screening circuit board receives photon signals output by the avalanche photodiode module through the cable and screens the photon signals.

4. The temperature of the diode D1 in the avalanche photodiode module is detected by a thermistor attached to its surface.

5. The avalanche signal discrimination circuit board generates the drive analog signals required by the avalanche photodiode module.

6. And the avalanche signal discrimination circuit board acquires the temperature signal of the avalanche photodiode module and controls the power supply to supply power to the refrigeration module through a PI algorithm.

To sum up, the existing single photon detection functional module has the following main disadvantages:

1. The volume is large.

2. The parts are more, suppliers are different, and the process difference is large.

3. The overall power consumption is large.

4. The installation and the debugging are complex, and the process is complex.

5. The signal interfaces are more, the signal transmission paths are long, the signal types are more, and the loss in the transmission process is large.

Disclosure of Invention

The invention aims to solve the problems of more parts, large volume and complex installation and debugging of a single photon detection device in the prior art, and provides an integrated single photon detection device which is miniaturized and simple to install and debug.

In order to achieve the above object, the technical scheme of the present invention is as follows:

The utility model provides an integrate single photon detection device, including refrigerating module, temperature sensor module, avalanche photodiode module, narrow pulse signal produces the module, avalanche signal discriminates the module, IO module, the heat sink, delay circuit, sealed thermal-insulated encapsulation module, the heat sink sets up in refrigerating module's top, avalanche photodiode module sets up in refrigerating module's below and hugs closely refrigerating module, temperature sensor module sets up in avalanche photodiode module's side, delay circuit, narrow pulse signal produces the module, avalanche signal discriminates the module left and right sides sets gradually and is located avalanche photodiode module's below, IO module sets up in the left and right sides of delay circuit and avalanche signal discriminator module, refrigerating module, temperature sensor module, avalanche photodiode module, narrow pulse signal produces the module, avalanche signal discriminates the module, the heat sink, delay circuit all sets up in sealed thermal-insulated encapsulation module.

The IO module comprises an input end and an output end, wherein the input end comprises a power supply end, a photon synchronous signal a input end, a discrimination threshold input end, an optical signal input end, a delay chip time control end and a delay interval control end; the output end comprises a temperature sensor signal output end and an avalanche count output end.

Preferably, the temperature sensor module comprises a temperature sensor and a digital-to-analog conversion circuit, the avalanche photodiode module comprises a diode driving circuit and a diode D1, and a detection end of the temperature sensor is arranged on the side edge of the diode D1.

Preferably, an optical fiber is arranged on the sealed heat-insulating packaging module shell, and photons input by the optical fiber irradiate on the diode D1.

Optimally, the input end of the delay circuit comprises a photon synchronizing signal a input end, a time control end passing through a delay chip and a delay interval control end, the output end of the delay circuit is connected with the input end of a narrow pulse signal generating module, the narrow pulse signal generating module comprises a first signal output end and a second signal output end, an avalanche signal discriminating module comprises a first discrimination input end, a second discrimination input end and a second discrimination output end, the first signal output end is connected with the input end of the avalanche photodiode module, the other input end of the avalanche photodiode module is an optical signal input end, the output end of the avalanche photodiode module is connected with the first discrimination input end, the second signal output end is connected with the second discrimination input end, the avalanche signal discriminating module further comprises a threshold discrimination input end, and the discrimination output end is used as the output end of the whole device.

Preferably, the delay circuit comprises an or gate chip, a first delay chip, a selection chip and a control and selection circuit, the first delay chip further comprises a delay interval control end, the or gate chip, the first delay chip and the selection chip are sequentially and electrically connected, one input end of the or gate chip serves as the input end of the whole delay circuit and inputs the photon synchronization signal a, the output end of the selection chip comprises two output ends, one output end serves as the output end of the delay circuit, the other output end is connected with the other input end of the or gate chip, the selection chip comprises a selection control end, and the output end of the control and selection circuit is connected with the selection control end.

Preferably, the control and selection circuit comprises a counter and a comparator, wherein the counter comprises a reset end, a clock signal end and an output end, the reset end is connected with the input end of an OR gate for inputting a photon synchronizing signal a, the clock signal end is connected with the output end of the first delay chip, the output end of the counter is connected with one input end of the comparator, the other input end of the comparator is used as a time control end of the delay chip, the time control end of the delay chip is connected, and the output end of the comparator is connected with the selection control end.

The narrow pulse signal generating module comprises a first driving component, a second delay chip, a third delay chip, a first NAND gate chip and a second NAND gate chip; the first driving component comprises a driving first input end, a driving first output end and a driving second output end, the second driving component comprises a driving second input end, a driving third output end and a driving fourth output end, the driving first input end and the driving second input end are respectively connected with the output end of the delay circuit, namely, input delay output signals b, the driving first output end is connected with the input end of a second delay chip, the output end of the second delay chip is connected with one input end of the first NAND gate chip, the driving second output end is directly connected with the other input end of the first NAND gate chip, and the output end of the first NAND gate chip outputs gate signals c; the driving third output end is connected with the input end of the third delay chip, the output end of the third delay chip is connected with one input end of the second NAND gate chip, the driving fourth output end is directly connected with the other input end of the second NAND gate chip, and the output end of the second NAND gate chip outputs a coincidence gate signal d.

Optimally, the avalanche photodiode module comprises a diode D1, a triode Q1, a resistor R2, a resistor R3, a capacitor C1, a first level end and a second level end, wherein one end of the resistor R1 is an input end of the avalanche photodiode module and is connected with the output end of the narrow pulse signal generating module, a gate signal C with a specific width generated by the narrow pulse signal generating module is received, the other end of the resistor R1 is connected with a base electrode of the triode Q1, the first level end is connected with a collector electrode of the triode Q1 through the resistor R2, the collector electrode of the triode Q1 is also connected with a negative electrode of the diode D1, an anode of the diode D1 is connected with the second level end through the resistor R3, and the anode of the diode D1 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is used as an output end of the avalanche photodiode module.

Optimally, the avalanche signal discrimination module comprises a triode Q2, a triode Q3, a triode Q4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C2, a first power supply VCC, a discrimination threshold input end Vth and a current source, wherein a base electrode of the triode Q2 is connected with an output end of the narrow pulse signal generation module, and is used for receiving a coincidence gate signal d with a specific width, and the first power supply VCC is connected with a collector electrode of the triode Q2 through the resistor R4; the output end of the avalanche photodiode module is connected with the base electrode of the triode Q3 through a resistor R5; the screening threshold input end Vth is also connected with the base electrode of the triode Q3 through a resistor R6, the first power supply is connected with the collector electrode of the triode Q3 through a resistor R7, the collector electrode of the triode Q3 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is used as an avalanche count output end; the screening threshold input end Vth is connected with the base electrode of the triode Q4 through a resistor R8, and the first power supply VCC is directly connected with the collector electrode of the triode Q4; the three ends of the emitter of the triode Q2, the emitter of the triode Q3 and the emitter of the triode Q4 are connected with the ground after passing through a current source.

The invention has the advantages that:

(1) The invention provides an integrated single photon detection device, which removes parasitic parameters of each module of the original independent element scheme after integration and improves signal quality. The physical size of the circuit through which the whole signal flow passes is greatly shortened, and the interference of the outside world to the whole device is reduced under the condition that the interference in unit area is the same, so that the performance of the whole device is improved. The integration also promotes the microminiaturization of the detector device.

(2) According to the invention, the gate signal c passes through the avalanche photodiode module and then enters the avalanche signal discrimination module, and the coincidence gate signal d is directly enters the avalanche signal discrimination module, when the avalanche photodiode module is not integrated, the optical cable has a certain length, impedance matching is needed in the avalanche photodiode module, the front of two input ends of the NAND gate in the narrow pulse signal generation module is connected with the delay chip, but after the integration, the relative positions of the integration gate signal c and the coincidence gate signal d are fixed and can be calculated due to the short distance, so that the delay chip in front of one of the two input ends of the NAND gate can be removed, the number of parts is reduced, the power consumption is reduced, and the dynamic delay range is increased. And after integration, the diode D1 in the avalanche photodiode module is directly coupled with the triode for control, so that impedance matching is not needed, and the power consumption is reduced. Because the distance between the modules is reduced, the delay chip is saved, and thus the working efficiency and the working speed of the whole device are improved.

(3) After integration, the number of signal interfaces is reduced, so that the device is connected with external equipment simply and conveniently.

Drawings

Fig. 1 is an internal layout diagram of an integrated single photon detection device according to an embodiment of the present invention.

Fig. 2 is a diagram showing the connection of internal circuit modules of an integrated single photon detection device according to the present invention.

Fig. 3 is a circuit diagram of a delay circuit in an integrated single photon detection device according to the present invention.

FIG. 4 is a timing diagram of a delay circuit of an integrated single photon detection device according to the present invention.

Fig. 5 is a circuit diagram of a narrow pulse signal generating module in an integrated single photon detection device according to the present invention.

Fig. 6 is a timing diagram of a narrow pulse signal generating module in an integrated single photon detection device according to the present invention.

Fig. 7 is a circuit diagram of an avalanche photodiode module in an integrated single photon detection device in accordance with the present invention.

Fig. 8 is a circuit diagram of the snow collapse signal discrimination module in the integrated single photon detection device of the present invention.

Detailed Description

Example 1

This embodiment is a description of the internal layout of the integrated single photon detection device.

As shown in fig. 1, the integrated single photon detection device comprises a refrigeration module 1, a temperature sensor module 2, an avalanche photodiode module 3, a narrow pulse signal generation module 4, an avalanche signal discrimination module 5, an IO module 6, a heat sink 7, a delay circuit 9 and a sealed heat insulation packaging module 8, wherein the heat sink 7 is arranged above the refrigeration module 1, the avalanche photodiode module 3 is arranged below the refrigeration module 1 and clings to the refrigeration module 1, the temperature sensor module 2 is arranged on the side edge of the avalanche photodiode module 3, the delay circuit 9, the narrow pulse signal generation module 4 and the avalanche signal discrimination module 5 are sequentially arranged left and right and are positioned below the avalanche photodiode module 3, and the IO module 6 is arranged on the left side and the right side of the delay circuit 9 and the avalanche signal discrimination module 5. The refrigerating module 1, the temperature sensor module 2, the avalanche photodiode module 3, the narrow pulse signal generating module 4, the avalanche signal discriminating module 5, the heat sink 7 and the delay circuit 9 are all arranged in the sealed heat insulation packaging module 8. The sealed heat-insulating packaging module 8 can increase the anti-interference capability of the whole receiving device, thereby improving the performance of the whole machine. Because each module in the device is integrated and sealed in the sealed and isolated packaging module after being distributed, the whole device is reduced in size, and the microminiaturization of detector equipment can be promoted.

In detail, the refrigeration module 1 is a TEC refrigerator.

The IO module 6 comprises an input end and an output end, wherein the input end comprises a power supply end, a photon synchronous signal a input end, a discrimination threshold input end, an optical signal input end, a time delay chip passing frequency control end and a time delay interval control end. The output end comprises a temperature sensor signal output end and an avalanche count output end.

The temperature sensor module 2 comprises a temperature sensor and a digital-to-analog conversion circuit, the avalanche photodiode module 3 comprises a diode driving circuit and a diode D1, the detection end of the temperature sensor is arranged on the side edge of the diode D1, the signal output end of the temperature sensor is connected with the input end of the digital-to-analog conversion circuit, and the output end of the digital-to-analog conversion circuit is used as the signal output end of the temperature sensor and is output from the IO module 6. The temperature sensor signal output end outputs an 8-bit or 16-bit digital signal.

The refrigerating module 1, the avalanche photodiode module 3 and other components are all miniaturized components, and the connection mode and the arranged structure not only enable the single photon detection photoelectric module in the quantum communication field to be miniaturized; and the single photon detection equipment in the quantum communication field is miniaturized. The modularized arrangement enhances the working stability of the device, increases the anti-interference capability, and further improves the performance of the whole machine. The number of parts in the whole system is reduced through encapsulation, and the whole integrated single photon detection device and the manufacturing process are unified.

Example 2

This embodiment is a description of the connection of the internal circuit blocks of the integrated single photon detection device.

As shown in fig. 2, the input end of the delay circuit 9 includes a photon synchronization signal a input end, a delay chip number control end and a delay interval control end, the output end of the delay circuit 9 is connected with the input end of the narrow pulse signal generating module 4, the narrow pulse signal generating module 4 includes a signal first output end and a signal second output end, the avalanche signal discriminating module 5 includes a first discriminating input end, a second discriminating input end and a discriminating output end, the signal first output end of the narrow pulse signal generating module 4 is connected with one input end of the avalanche photodiode module 3, the other input end of the photodiode module 3 is an optical signal input end, the output end of the avalanche photodiode module 3 is connected with the first discriminating input end, the signal second output end of the narrow pulse signal generating module 4 is connected with the second discriminating input end of the avalanche signal discriminating module 5, the avalanche signal discriminating module 5 further has a discriminating threshold input end, and the discriminating output end of the avalanche signal discriminating module 5 is an avalanche count output end. The working process of the circuit module adopting the connection mode is as follows:

The photon synchronous signal a input from the outside firstly passes through the delay circuit 9 to generate a delay output signal b, the delay output signal b is input into the narrow pulse signal generating module 4, and the narrow pulse signal generating module 4 generates a gate signal c with a specific width and a coincidence gate signal d with a specific width. The gate signal c is fed to the avalanche photodiode module 3, and an avalanche signal e is generated and fed to a screening first input of the avalanche signal screening module 5. The coincidence gate signal d is input to a discrimination second input terminal of the avalanche signal discrimination module 5, and the avalanche signal discrimination module 5 outputs an avalanche count pulse signal f to the outside according to a discrimination threshold set externally.

Example 3

This embodiment is a description of the delay circuit 9.

As shown in fig. 3 to 4, the delay circuit 9 includes an or gate chip 91, a first delay chip 95, a selection chip 94, and a control selection circuit, where the or gate chip 91, the first delay chip 95, and the selection chip 94 are electrically connected in sequence, one input end of the or gate chip 91 serves as an input end of the whole delay circuit 9 and inputs the photon synchronization signal a, two output ends of the selection chip 94 are included, one of the output ends serves as an output end of the delay circuit 9 to output the delay output signal b, the other output end is connected with the other input end of the or gate chip 91 to form a delay loop, the selection chip 94 includes a selection control end, and the output end of the control selection circuit is connected with the selection control end.

The first delay chip 95 further comprises a delay interval control end, the control and selection circuit comprises a counter 92 and a comparator 93, the counter 92 comprises a reset end, a clock signal end and an output end, the reset end is connected with the input end of an OR gate for inputting the photon synchronizing signal a, the clock signal end is connected with the output end of the first delay chip 95, the output end is connected with one input end of the comparator 93, the other input end of the comparator 93 serves as a time control end of a time passing delay chip, the time control end of the time passing delay chip is connected with the time control device of the time passing delay chip, and the output end of the comparator 93 is connected with the selection control end.

The delay circuit 9 mainly serves to delay the signal. The core component is a first delay chip 95. The number of delay chips is reduced by multiplexing the delay chips, the overall power consumption is reduced, and the dynamic delay range is increased.

The signal input by the input end of the photon synchronizing signal a is a signal to be delayed, the delay time can be set by passing through the delay chip number control device and the delay interval control end, and the selection chip 94 switches whether the delayed photon synchronizing signal a is directly used as the delay output signal b or is input into the first delay chip 95 again according to the judgment condition.

The number of times the signal passes through the delay chip is set by the number-of-times-through-delay-chip control means as an input parameter of the comparator 93.

When the value inputted from the delay interval control terminal is equal to the value inputted from the delay chip number control device, the selection chip 94 selects to output the delay output signal from the delay circuit 9. In fig. 4, when the count value (the value input from the delay interval control terminal) is equal to the value set by the delay (the value input from the delay chip number control device), that is, H4, the selection chip 94 selects to output the delay output signal b.

Example 4

This embodiment is a description of the narrow pulse signal generating module 4.

As shown in fig. 5-6, the narrow pulse signal generating module 4 includes a first driving unit 41, a second driving unit 42, a second delay chip 43, a third delay chip 44, a first nand chip 45, and a second nand chip 46.

The first driving part 41 includes a driving first input terminal, a driving first output terminal, and a driving second output terminal, and the second driving part 42 includes a driving second input terminal, a driving third output terminal, and a driving fourth output terminal.

The driving first input end and the driving second input end are respectively connected with the output end of the delay circuit 9, namely, the delayed output signal b is input.

The first output end of the driving is connected with the input end of the second delay chip 43, the output end of the second delay chip 43 is connected with one input end of the first nand chip 45, the second output end of the driving is directly connected with the other input end of the first nand chip 45, and the output end of the first nand chip 45 outputs the gate signal c. The third output end of the driving is connected to the input end of the third delay chip 44, the output end of the third delay chip 44 is connected to one input end of the second nand chip 46, the fourth output end of the driving is directly connected to the other input end of the second nand chip 46, and the output end of the second nand chip 46 outputs the coincidence gate signal d.

In the above-described embodiments, the first driving member 41 and the second driving member 42 function to prevent the shortage of power and the waveform from being deformed. Since integration has a certain requirement on power consumption of the electronic circuit inside the module, the second delay chip 43 and the third delay chip 44 are integrated in one dual-channel delay chip, and accordingly, the first driving part 41 and the second driving part 42 are replaced by one dual-channel driving device or multiple-channel driving device.

In fig. 6, timing charts of two input terminals of the first nand chip 45 and two input terminals of the second nand chip 46 are shown as timing a, timing B, timing E, and timing D in the drawing.

Example 5

This embodiment is a description of the avalanche photodiode module 3.

As shown in fig. 7, the avalanche photodiode module 3 includes a diode D1, a triode Q1, a resistor R2, a resistor R3, a capacitor C1, a first level end, and a second level end, where one end of the resistor R1 is an input end of the avalanche photodiode module 3, and is connected to an output end of the first nand chip 45 in the narrow pulse signal generating module 4, receives a gate signal C with a specific width generated by the narrow pulse signal generating module 4, the other end of the resistor R1 is connected to a base of the triode Q1, the first level end is connected to a collector of the triode Q1 through the resistor R2, the collector of the triode Q1 is further connected to a negative electrode of the diode D1, the positive electrode of the diode D1 is connected to the second level end through the resistor R3, and the positive electrode of the diode D1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is used as an output end of the avalanche photodiode module 3. The voltage value of the first level terminal is 5V, the voltage difference range is plus or minus 2V, the voltage value of the second level terminal is-60V, and the voltage difference range is plus or minus 10V. An optical fiber is arranged on the shell of the sealed heat-insulating packaging module 8, and photons input by the optical fiber are used as optical signals to be irradiated on the diode D1. Because the device is high in integration level, direct coupling control between the triode Q1 and the diode D1 can be realized without considering impedance matching, and because the impedance matching needs to use a larger resistor, the loss is reduced after integration.

Example 6

This embodiment is a description of the avalanche signal discrimination module 5.

As shown in fig. 8, the avalanche signal discriminating module 5 includes a triode Q2, a triode Q3, a triode Q4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C2, a first power VCC, a discriminating threshold input terminal Vth, and a current source, wherein a base electrode of the triode Q2 is connected with an output terminal of the second nand gate chip 46 in the narrow pulse signal generating module 4, and receives a coincidence gate signal d with a specific width output by the second nand gate chip 46. The first power supply VCC is connected to the collector of the transistor Q2 via a resistor R4. The output end of the avalanche photodiode module 3 is connected with the base electrode of the triode Q3 through a resistor R5. The screening threshold input terminal Vth is also connected with the base electrode of the triode Q3 through a resistor R6, the first power supply VCC is connected with the collector electrode of the triode Q3 through a resistor R7, the collector electrode of the triode Q3 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is used as an avalanche count output terminal. The screening threshold input terminal Vth is connected with the base of the triode Q4 through a resistor R8, and the first power supply VCC is directly connected with the collector of the triode Q4. The three ends of the emitter of the triode Q2, the emitter of the triode Q3 and the emitter of the triode Q4 are connected with the ground after passing through a current source. The resistance of the resistor R8 in the scheme is smaller than that of the resistor R6. The avalanche signal discrimination module 5 outputs an avalanche count pulse signal f when the avalanche signal level is higher than a discrimination threshold in accordance with the gate signal d time.

The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. The utility model provides an integrate single photon detection device, a serial communication port, including refrigerating module, temperature sensor module, the avalanche photodiode module, narrow pulse signal produces the module, avalanche signal discriminates the module, the IO module, the heat sink, delay circuit, sealed thermal-insulated encapsulation module, the heat sink sets up in refrigerating module's top, avalanche photodiode module sets up in refrigerating module's below and hugs closely refrigerating module, temperature sensor module sets up in avalanche photodiode module's side, delay circuit, narrow pulse signal produces the module, avalanche signal discriminates the module left and right sides sets gradually and is located avalanche photodiode module's below, the IO module sets up in the left and right sides of delay circuit and avalanche signal discriminator module, refrigerating module, temperature sensor module, avalanche photodiode module, narrow pulse signal produces the module, avalanche signal discriminates the module, the heat sink, delay circuit all sets up in sealed thermal-insulated encapsulation module.

2. The integrated single photon detection device according to claim 1, wherein the IO module comprises an input end and an output end, the input end comprises a power supply end, a photon synchronization signal a input end, a discrimination threshold input end, an optical signal input end, a delay chip number control end and a delay interval control end; the output end comprises a temperature sensor signal output end and an avalanche count output end.

3. The integrated single photon detection device according to claim 1, wherein the temperature sensor module comprises a temperature sensor and a digital-to-analog conversion circuit, the avalanche photodiode module comprises a diode driving circuit and a diode D1, and a detection end of the temperature sensor is arranged at a side of the diode D1.

4. An integrated single photon detection device according to claim 3, wherein an optical fiber is disposed on the sealed heat-insulating package module housing, and photons inputted by the optical fiber are irradiated on the diode D1.

5. The integrated single photon detection device according to claim 1, wherein the input end of the delay circuit comprises a photon synchronization signal a input end, a delay chip time control end and a delay interval control end, the output end of the delay circuit is connected with the input end of the narrow pulse signal generating module, the narrow pulse signal generating module comprises a signal first output end and a signal second output end, the avalanche signal discriminating module comprises a first discrimination input end, a second discrimination input end and a discrimination output end, the signal first output end is connected with the input end of the avalanche photodiode module, the other input end of the avalanche photodiode module is an optical signal input end, the output end of the avalanche photodiode module is connected with the first discrimination input end, the second signal output end is connected with the second discrimination input end, the avalanche signal discriminating module further comprises a discrimination threshold input end, and the discrimination output end is used as the output end of the whole device.

6. The integrated single photon detection device according to claim 1, wherein the delay circuit comprises an or gate chip, a first delay chip, a selection chip and a control and selection circuit, the first delay chip further comprises a delay interval control end, the or gate chip, the first delay chip and the selection chip are electrically connected in sequence, one input end of the or gate chip serves as an input end of the whole delay circuit and inputs photon synchronization signals a, the output ends of the selection chip comprise two output ends, one output end serves as an output end of the delay circuit, the other output end is connected with the other input end of the or gate chip, the selection chip comprises a selection control end, and the output end of the control and selection circuit is connected with the selection control end.

7. The integrated single photon detection device according to claim 6, wherein the control and selection circuit comprises a counter and a comparator, the counter comprises a reset end, a clock signal end and an output end, the reset end is connected with an input end of an or gate inputting a photon synchronization signal a, the clock signal end is connected with an output end of the first delay chip, the output end of the counter is connected with one input end of the comparator, the other input end of the comparator is used as a time control end of a time passing delay chip, the time control end of the time passing delay chip is connected with the time control device of the time passing delay chip, and the output end of the comparator is connected with the selection control end.

8. The integrated single photon detection device according to any one of claims 1 to 7, wherein the narrow pulse signal generating module comprises a first driving part, a second delay chip, a third delay chip, a first nand gate chip, and a second nand gate chip; the first driving component comprises a driving first input end, a driving first output end and a driving second output end, the second driving component comprises a driving second input end, a driving third output end and a driving fourth output end, the driving first input end and the driving second input end are respectively connected with the output end of the delay circuit, namely, input delay output signals b, the driving first output end is connected with the input end of a second delay chip, the output end of the second delay chip is connected with one input end of the first NAND gate chip, the driving second output end is directly connected with the other input end of the first NAND gate chip, and the output end of the first NAND gate chip outputs gate signals c; the driving third output end is connected with the input end of the third delay chip, the output end of the third delay chip is connected with one input end of the second NAND gate chip, the driving fourth output end is directly connected with the other input end of the second NAND gate chip, and the output end of the second NAND gate chip outputs a coincidence gate signal d.

9. The integrated single photon detection device according to claim 1, wherein the avalanche photodiode module comprises a diode D1, a triode Q1, a resistor R2, a resistor R3, a capacitor C1, a first level end and a second level end, one end of the resistor R1 is an input end of the avalanche photodiode module, the input end of the resistor R1 is connected with an output end of the narrow pulse signal generating module, a gate signal C with a specific width generated by the narrow pulse signal generating module is received, the other end of the resistor R1 is connected with a base electrode of the triode Q1, the first level end is connected with a collector electrode of the triode Q1 through the resistor R2, the collector electrode of the triode Q1 is also connected with a negative electrode of the diode D1, the positive electrode of the diode D1 is connected with the second level end through the resistor R3, the positive electrode of the diode D1 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is used as an output end of the avalanche photodiode module.

10. The integrated single photon detection device according to claim 1, wherein the avalanche signal discrimination module comprises a triode Q2, a triode Q3, a triode Q4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C2, a first power supply VCC, a discrimination threshold input Vth, and a current source, wherein a base of the triode Q2 is connected with an output end of the narrow pulse signal generation module, and receives a coincidence gate signal d with a specific width, and the first power supply VCC is connected with a collector of the triode Q2 through the resistor R4; the output end of the avalanche photodiode module is connected with the base electrode of the triode Q3 through the resistor R5; the screening threshold input end Vth is also connected with the base electrode of the triode Q3 through the resistor R6, the first power supply is connected with the collector electrode of the triode Q3 through the resistor R7, the collector electrode of the triode Q3 is connected with one end of the capacitor C2, and the other end of the capacitor C2 is used as an avalanche counting output end; the screening threshold input end Vth is connected with the base electrode of the triode Q4 through the resistor R8, and the first power supply VCC is directly connected with the collector electrode of the triode Q4; the three ends of the emitter of the triode Q2, the emitter of the triode Q3 and the emitter of the triode Q4 are connected and then connected with the ground after passing through the current source.