CN110119331A - Clock-switching method, device, server and clock system - Google Patents

Abstract

Embodiments of the present application provide a clock switching method, device, server, and clock system. The method includes, when an abnormality is detected in the main clock signal, receiving the standby clock signal through the standby clock signal input port of the switching circuit; The phase is reconstructed, and the reconstructed clock signal is generated. The phase of the reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality; the phase of the reconstructed clock signal is compensated according to the standby clock signal and the preset phase adjustment speed , and generate a compensated clock signal, output the compensated clock signal through the clock signal output port of the switching circuit, and the phase of the compensated clock signal is consistent with the phase of the standby clock signal. The clock switching method provided in the embodiment of the present application can ensure that the phases of the clock signals provided to the TSCs of each processor are consistent, and ensure the normal operation of the operating system of the server.

Description

Clock switching method, device, server and clock system

technical field

The present application relates to the computer field, in particular to a clock switching method, device, server and clock system.

Background technique

The server includes a processor, and a time stamp counter (Time Stamp Counter, TSC) is located inside the processor, and is used to provide a clock signal for an operating system running on the server. In the clock system, the clock source of the TSC adopts a redundant design, and the clock source is provided for the TSC through the main clock board and the backup clock board. When the main clock board fails, the switching circuit corresponding to the processor will switch the clock source of the TSC provided to the processor to the standby clock board, and the standby clock board will continue to work instead of the main clock board, so as to avoid affecting the server's business processing. Because there may be a phase difference between the clock signal provided by the standby clock board and the clock signal provided by the master clock board, the clock signal provided by the TSC for the server operating system is unstable, which affects the stable running of the server. In order to solve the problem of phase inconsistency between the main and standby clock signals, the switching circuit usually reconstructs the phase of the standby clock signal provided by the standby clock board according to the phase difference between the clock signals provided by the main and standby clock boards, and the reconstructed clock signal The phase of the main clock signal is consistent with that of the main clock signal provided by the main clock board.

For a multi-processor server, the TSCs of each processor provide a high-precision clock signal for the same operating system kernel. The operating system of the multiprocessor server can work normally only when the counting frequency and phase of the TSCs in each processor are consistent. Therefore, it is necessary to ensure that the phase and frequency of the clock signal provided to the TSC of each processor in the clock system are consistent. In a multiprocessor server, different switching circuits have different processing deviations when reconstructing the same clock signal, so there is a phase deviation between the clock signals obtained after different switching circuits reconstruct the phase of the standby clock signal, and the phase may be The deviations are also different, resulting in inconsistent phases of the clock signals provided to the TSCs of the processors, thereby affecting the normal operation of the operating system of the server.

Contents of the invention

The embodiments of the present application provide a clock switching method, device, server and clock system, which can ensure that the clock signals provided to the TSCs of each processor in the multiprocessor server are consistent, and ensure that the operating system on the server can work normally.

In the first aspect, the embodiment of the present application provides a clock switching method, including: when the main clock signal is normal, the first circuit provides the main clock signal to the first load after receiving the main clock signal, and the main clock A signal is provided by a master clock circuit connected to said first circuit. When the main clock signal is abnormal, the first circuit receives a backup clock signal, and the backup clock signal is provided by a backup clock circuit connected to the first circuit. The first circuit reconstructs the phase of the standby clock signal to generate a first reconstructed clock signal, and the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality. The first circuit provides the first reconstructed clock signal to the first load. The first circuit continuously adjusts the phase of the first reconstruction clock signal according to the backup clock signal and a preset phase adjustment speed to generate a plurality of adjustment clock signals, and the last generated adjustment clock signal among the plurality of adjustment clock signals is The phase of the clock signal is equal to the phase of the standby clock signal, except for the last generated adjustment clock signal, the phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phases of the first reconstructed clock signal and between the phases of the standby clock signal. The first circuit provides the adjusted clock signal generated after adjustment to the first load after each adjustment.

By adjusting the phase of the reconstructed clock signal according to the preset phase adjustment speed, a clock signal with a phase consistent with that of the standby clock signal is generated, which ensures that the phases of the clock signals adjusted by multiple first circuits change slowly and are consistent, so that each The phases of the clock signals provided by the first circuit to the TSCs of the processors are consistent, avoiding the unstable operation of the multi-processor operating system and avoiding the possible cumulative error caused by multiple clock switching.

In a possible implementation manner, the value range of the preset phase adjustment speed is 1-10 microseconds/second.

In a possible implementation manner, the clock switching method further includes: when the main clock signal is normal, the second circuit provides the main clock signal to the second load after receiving the main clock signal, and the main clock signal is determined by The master clock circuit connected to the second circuit provides. When the main clock signal is abnormal, the second circuit receives a backup clock signal, and the backup clock signal is provided by the backup clock circuit connected to the second circuit. The second circuit reconstructs the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality. The second circuit provides the second reconstructed clock signal to the second load. The second circuit continuously adjusts the phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, and the last of the plurality of compensation clock signals is generated The phase of the compensated clock signal is equal to the phase of the standby clock signal, except for the last generated compensated clock signal, the phases of other compensated clock signals in the plurality of compensated clock signals are between that of the second reconstructed clock signal phase and the phase of the standby clock signal. The second circuit provides the adjusted and generated compensation clock signal to the second load after each adjustment.

Due to the processing deviation between the first circuit and the second circuit when performing phase reconstruction, there is a phase deviation between the first reconstruction clock signal and the second reconstruction clock signal. By adjusting the phases of the first reconstruction clock signal and the second reconstruction clock signal respectively , so that the phases of the finally generated compensation clock signal and the adjustment clock signal are consistent with the phases of the standby clock signal, and the phases of the two are consistent without deviation.

In a possible implementation manner, the structure of the second circuit is the same as that of the first circuit; the first load may include one or more processors, and the second load may also include one or more processors.

In a possible implementation manner, the first circuit includes a first control circuit and a first phase-locked loop circuit, and the first control circuit is connected to the first phase-locked loop circuit. The clock switching method further includes: when the main clock signal is abnormal, the first control circuit sets the working state of the first phase-locked loop circuit to a phase reconstruction state. The first circuit reconstructs the phase of the standby clock signal to generate a first reconstructed clock signal, including: when the first phase-locked loop circuit is in the phase rebuilding state, reconfiguring the phase of the standby clock signal Perform reconstruction to generate a first reconstruction clock signal. The clock switching method further includes: the first control circuit determines that the first phase-locked loop circuit generates the first reconstruction clock signal, and sets the working state of the first phase-locked loop circuit to a phase compensation state. The first circuit continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, including: the first phase-locked loop circuit When the working state is the phase compensation state, the phase of the first reconstruction clock signal is continuously adjusted according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals.

The first circuit includes a first control circuit and a first phase-locked loop circuit, by first controlling the first phase-locked loop circuit to work in the phase reconstruction state to perform phase reconstruction on the standby clock signal to generate a first reconstruction clock signal, and then controlling the first phase-locked loop The loop circuit works in the phase compensation state to adjust the phase of the first reconstructed clock signal, so that the phase of the finally generated adjusted clock signal is equal to the phase of the standby clock signal, which simplifies the circuit structure of the first circuit.

In a possible implementation manner, when the main clock signal is abnormal, the first control circuit writes phase reconstruction configuration information to a working status register in the first phase-locked loop circuit. The phase reconstruction configuration information is used to indicate that the first phase-locked loop circuit works in a phase reconstruction state. After determining that the first phase-locked loop circuit generates the first reconstruction clock signal, the first control circuit writes phase compensation configuration information into a working state register in the first phase-locked loop circuit. The phase compensation configuration information is used to indicate that the first phase locked loop circuit works in a phase compensation state.

In a possible implementation manner, the first circuit provides a clock signal to the first load through a clock signal output port of the first circuit, and the clock signal output port of the first circuit is connected to the first The feedback clock signal input port of the circuit is connected, and the feedback clock signal input port of the first circuit is connected with the feedback input port of the first phase-locked loop circuit. The clock switching method further includes: before the first phase-locked loop circuit rebuilds the phase of the standby clock signal, closing the feedback input port of the first phase-locked loop circuit and stopping the output from the first phase-locked loop circuit The feedback input port of the first circuit receives the clock signal output by the clock signal output port of the first circuit. The clock switching method further includes: before the first phase-locked loop circuit continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, Close the oscillator feedback port of the first phase-locked loop circuit, stop receiving the clock signal provided by the oscillator from the oscillator feedback port of the first phase-locked loop circuit, and open the first phase-locked loop circuit feedback input port. The first phase-locked loop circuit continuously adjusts the phase of the first reconstruction clock signal according to the backup clock signal and the preset phase adjustment speed to generate a plurality of adjustment clocks when the working state is the phase compensation state Signals, including: when the first phase-locked loop circuit is in the phase compensation state, according to the standby clock signal, the clock feedback signal received from the feedback input port of the phase-locked loop circuit and the preset phase The adjustment speed continuously adjusts the phase of the first reconstruction clock signal to generate a plurality of adjustment clock signals.

In the phase compensation process, the phase of the reconstructed clock signal is compensated according to the standby clock signal and the feedback clock signal output by the clock signal output port of the first circuit, so that the final generated adjustment of the clock signal output port of the first circuit The phase of the clock signal is consistent with the phase of the standby clock signal, thereby ensuring that the phases of the clock signals provided by all the first circuits to the processors are completely consistent.

In a possible implementation manner, when the working state of the first phase-locked loop circuit is a phase reconstruction state, the phase of the standby clock signal is reconstructed to generate a first reconstruction clock signal, including: the first When the phase-locked loop circuit is in the phase reconstruction state, the phase of the standby clock signal is reconstructed according to the phase difference to generate the first reconstruction clock signal, and the phase difference is the difference between the standby clock signal and the abnormality before Phase difference between master clock signals.

In a possible implementation manner, the phase difference is a phase difference between the standby clock signal and the main clock signal finally determined by the first circuit before the abnormality.

In a possible implementation manner, the frequency of the standby clock signal is determined according to an average frequency of the main clock signal provided by the main clock circuit within a preset time period.

By using two clock circuits to supply power to the processors in the multi-processor server system, the stability of the clock source is improved, and it is avoided to use a single stable and accurate clock source to provide clock signals to each processor at the same time through two active and standby clock circuits. The clock cost of the clock system is reduced.

In the second aspect, the embodiment of the present application further provides a clock switching device, configured to implement the clock switching method in the first aspect above, and has the same technical features and technical effects. This application will not repeat this.

A second aspect of the embodiments of the present application provides a clock switching device, including a first circuit, and the first circuit is respectively connected to a main clock circuit, a backup clock circuit, and a first load.

The first circuit is configured to, when the main clock signal is normal, provide the main clock signal to the first load after receiving the main clock signal, and the main clock signal is provided by the main clock circuit;

The first circuit is further configured to receive a backup clock signal when the main clock signal is abnormal, and the backup clock signal is provided by the backup clock circuit.

The first circuit is further configured to reconstruct the phase of the standby clock signal to generate a first reconstructed clock signal, where the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality.

The first circuit is further configured to provide the first reconstruction clock signal to the first load.

The first circuit is further configured to continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjusted clock signals, among the plurality of adjusted clock signals The phase of the last generated adjustment clock signal is equal to the phase of the standby clock signal, except for the last generated adjustment clock signal, the phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phases of the first reconstruction clock between the phase of the signal and the phase of the standby clock signal;

The first circuit is further configured to provide the adjusted clock signal generated after adjustment to the first load after each adjustment.

In a possible implementation manner, the value range of the preset phase adjustment speed is 1-10 microseconds/second.

In a possible implementation manner, the clock switching device further includes: a second circuit; the second circuit is respectively connected to the main clock circuit, the backup clock circuit and a second load;

The second circuit is configured to, when the main clock signal is normal, provide the main clock signal to the second load after receiving the main clock signal, and the main clock signal is provided by the main clock circuit;

The second circuit is further configured to receive a backup clock signal when the main clock signal is abnormal, and the backup clock signal is provided by the backup clock circuit;

The second circuit is further configured to reconstruct the phase of the standby clock signal to generate a second reconstructed clock signal, where the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality;

The second circuit is further configured to provide the second reconstruction clock signal to the second load;

The second circuit is further configured to continuously adjust the phase of the second reconstruction clock signal according to the backup clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, and the plurality of compensation clock signals The phase of the last generated compensation clock signal in the signal is equal to the phase of the standby clock signal, except for the last generated compensation clock signal, the phases of other compensation clock signals in the plurality of compensation clock signals are between the second Between the phase of the reconstructed clock signal and the phase of the standby clock signal;

The second circuit is further configured to provide the adjusted and generated compensation clock signal to the second load after each adjustment.

In a possible implementation manner, the structure of the second circuit is the same as that of the first circuit; the first load may include one or more processors, and the second load may also include one or more processors.

In a possible implementation manner, the first circuit includes a first control circuit and a first phase-locked loop circuit, and the first control circuit is connected to the first phase-locked loop circuit;

The first control circuit is configured to set the working state of the first phase-locked loop circuit to a phase reconstruction state when the main clock signal is abnormal;

The first phase-locked loop circuit is configured to, when the working state is a phase reconstruction state, reconstruct the phase of the standby clock signal to generate a first reconstruction clock signal;

The first control circuit is further configured to determine that the first phase-locked loop circuit generates the first reconstruction clock signal, and set the working state of the first phase-locked loop circuit to a phase compensation state;

The first phase-locked loop circuit is further configured to continuously adjust the phase of the first reconstruction clock signal according to the standby clock signal and the preset phase adjustment speed when the working state is the phase compensation state to generate Multiple adjustment clock signals.

In a possible implementation manner, the first circuit provides a clock signal to the first load through a clock signal output port of the first circuit, and the clock signal output port of the first circuit is connected to the first The feedback clock signal input port of the circuit is connected, and the feedback clock signal input port of the first circuit is connected to the feedback input port of the first phase-locked loop circuit;

The first phase-locked loop circuit is also used to close the feedback input port of the first phase-locked loop circuit and stop the feedback from the first phase-locked loop circuit before rebuilding the phase of the standby clock signal. The feedback input port receives the clock signal output by the clock signal output port of the first circuit;

The first phase-locked loop circuit is further configured to, before continuously adjusting the phase of the first reconstruction clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals, turn off The oscillator feedback port of the first phase-locked loop circuit stops receiving the clock signal provided by the oscillator from the oscillator feedback port of the first phase-locked loop circuit, and opens the Feedback input port;

The first phase-locked loop circuit is also used to, when the working state is a phase compensation state, according to the standby clock signal, the clock feedback signal received from the feedback input port of the phase-locked loop circuit and the preset phase The adjustment speed continuously adjusts the phase of the first reconstruction clock signal to generate a plurality of adjustment clock signals.

In a possible implementation manner, the first phase-locked loop circuit is specifically configured to, when the working state is the phase reconstruction state, reconstruct the phase of the standby clock signal according to the phase difference to generate the first reconstruction clock signal , the phase difference is a phase difference between the standby clock signal and the main clock signal before the abnormality.

In a possible implementation manner, the phase difference is a phase difference between the standby clock signal and the main clock signal finally determined by the first circuit before the abnormality.

In a possible implementation manner, the frequency of the standby clock signal is determined according to an average frequency of the main clock signal provided by the main clock circuit within a preset time period.

In the third aspect, the embodiment of the present application further provides a clock switching device, configured to implement the clock switching method in the first aspect above, and has the same technical features and technical effects. This application will not repeat this.

A third aspect of the embodiment of the present application provides a clock switching device, including:

The first clock signal acquisition module is configured to provide the main clock signal to the first load after receiving the main clock signal when the main clock signal is normal, and the main clock signal is obtained by the first clock signal acquisition module. The connected master clock circuit provides;

The first clock signal acquisition module is further configured to receive a backup clock signal when the main clock signal is abnormal, and the backup clock signal is provided by a backup clock circuit connected to the first clock signal acquisition module;

The first reconstruction module is configured to reconstruct the phase of the standby clock signal to generate a first reconstruction clock signal, the phase of the first reconstruction clock signal is consistent with the phase of the main clock signal before the abnormality; The first load provides the first reconstruction clock signal;

The first adjustment module is configured to continuously adjust the phase of the first reconstruction clock signal according to the backup clock signal and a preset phase adjustment speed to generate a plurality of adjustment clock signals, and the last generated among the plurality of adjustment clock signals The phase of the adjusted clock signal is equal to the phase of the standby clock signal, except for the last generated adjusted clock signal, the phases of other adjusted clock signals in the plurality of adjusted clock signals are between that of the first reconstructed clock signal Between the phase and the phase of the standby clock signal; after each adjustment, the adjusted clock signal generated after adjustment is provided to the first load.

In a possible implementation manner, the value range of the preset phase adjustment speed is 1-10 microseconds/second.

In a possible implementation manner, the clock switching device further includes:

The second clock signal acquisition module is configured to provide the main clock signal to the second load after receiving the main clock signal when the main clock signal is normal, and the main clock signal is obtained by the second clock signal acquisition module. The connected master clock circuit provides;

The second clock signal acquisition module is further configured to receive a backup clock signal when the main clock signal is abnormal, and the backup clock signal is provided by a backup clock circuit connected to the second clock signal acquisition module;

The second reconstruction module is configured to reconstruct the phase of the standby clock signal to generate a second reconstruction clock signal, the phase of the second reconstruction clock signal is consistent with the phase of the main clock signal before the abnormality; a second load provides the second reconstruction clock signal;

The second adjustment module is configured to continuously adjust the phase of the second reconstruction clock signal according to the backup clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, among the plurality of compensation clock signals The phase of the last generated compensation clock signal is equal to the phase of the standby clock signal, except for the last generated compensation clock signal, the phases of other compensation clock signals in the plurality of compensation clock signals are between the phases of the second reconstruction clock Between the phase of the signal and the phase of the standby clock signal; providing the adjusted and generated compensated clock signal to the second load after each adjustment.

In a possible implementation manner, the second reconstruction module is the same as the first reconstruction module, and the second adjustment module is the same as the first adjustment module; the first load may include one or more processors, and the second load may also include a or multiple processors.

In a possible implementation manner, the clock switching device further includes:

A first control module, configured to set the first reconstruction module to a working state when the main clock signal is abnormal;

The first control module is further configured to set the first adjustment module to a working state after determining that the first reconstruction module generates the first reconstruction clock signal.

In a possible implementation manner, the clock switching device provides a clock signal to the first load through a clock signal output port of the clock switching device, and the clock signal output port of the clock switching device is connected to the clock switching device. The feedback clock signal input port of the device is connected, and the feedback clock signal input port of the clock switching device is connected to the feedback input port of the first adjustment module;

The first control module is further configured to, before the first reconstruction module rebuilds the phase of the backup clock signal, close the feedback input port of the first adjustment module, and stop the output from the first adjustment module. The feedback input port receives the clock signal output by the clock signal output port of the clock switching device;

The first control module is further configured to continuously adjust the phase of the first reconstruction clock signal according to the backup clock signal and the preset phase adjustment speed in the first adjustment module to generate a plurality of adjustment clocks Before the signal, close the adjustment feedback port of the first adjustment module, stop receiving the clock signal provided by the first adjustment module from the adjustment feedback port of the first adjustment module, and open the feedback input of the first adjustment module port;

The first adjustment module is further configured to adjust the speed of the first reconstructed clock signal according to the backup clock signal, the clock feedback signal received from the feedback input port of the first adjustment module, and the preset phase adjustment speed. The phase is continuously adjusted to generate multiple adjusted clock signals.

In a possible implementation manner, the first reconstruction module is further configured to reconstruct the phase of the standby clock signal according to a phase difference to generate a first reconstruction clock signal, the phase difference being the phase difference of the standby clock signal The phase difference from the master clock signal before the exception.

In a possible implementation manner, the phase difference is a phase difference between the standby clock signal and the main clock signal finally determined by the first circuit before the abnormality.

In a possible implementation manner, the frequency of the standby clock signal is determined according to an average frequency of the main clock signal provided by the main clock circuit within a preset time period.

In a possible implementation manner, the clock switching device further includes: a second control module, configured to set the second reconstruction module to a working state when the main clock signal is abnormal. The second control module is further configured to set the second adjustment module to a working state after determining that the second reconstruction module generates the second reconstruction clock signal. The communication mode between the second control module, the second adjustment module and the second reconstruction module is the same as the communication mode between the first control module, the first adjustment module and the first reconstruction module, and the second control module communicates with the first reconstruction module. For the communication manner between the second adjustment module and the second reconstruction module, reference may be made to the communication manner between the first control module, the first adjustment module, and the first reconstruction module, and the details will not be repeated here.

In a fourth aspect, the embodiment of the present application further provides a server, including one or more loads, and one or more clock switching devices having the same number as all loads, and all loads are connected to all clock switching devices in a one-to-one correspondence, The clock switching device is the clock switching device as described in any possible implementation manner of the second aspect above, and the clock signal output port of the clock switching device is connected to the corresponding load, which is the corresponding load Provides a clock signal.

In the fifth aspect, the embodiment of the present application also provides a clock system, including a main clock circuit, a backup clock circuit and at least one server as described in the fourth aspect above, and all clock switching devices of all servers are connected with the main clock circuit and the The standby clock circuit is connected.

In a possible implementation manner, the load of the server includes at least one processor, or the load of the server includes at least one processor and a node controller, and all processors of the load and the node The controller is connected to the clock switching device corresponding to the load, and all node controllers of all servers in the system are connected to each other.

In the sixth aspect, the embodiment of the present application also provides a clock system including a first node server, a main clock circuit and a backup clock circuit, the first node server includes a first clock switching device and a first processor; the first clock switching device is The clock switching device described in any possible implementation manner of the second aspect above. The first clock switching device is respectively connected to the main clock circuit and the backup clock circuit, and is used to receive the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The first clock switching device is also connected to the first processor for providing a clock signal to the first processor.

In a possible implementation manner, the first node server further includes a second clock switching device and a second processor; the second clock switching device is the clock described in any possible implementation manner of the second aspect above Switch device. The second clock switching device is respectively connected to the main clock circuit and the backup clock circuit, and is used to receive the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The second clock switching device is also connected to the second processor for providing a clock signal to the second processor.

In a possible implementation manner, the first node server further includes a third processor and a first node controller, and the third processor and the first node controller are respectively connected to the first clock switching device , receiving the clock signal provided by the first clock switching device. The first node server further includes a fourth processor and a second node controller, the fourth processor and the second node controller are respectively connected to the second clock switching device, and the first node controls The device is connected to the second node controller to receive the clock signal provided by the second clock switching device.

In a possible implementation manner, the clock system further includes a second node server, and the second node server includes a third clock switching device and a fifth processor; the third clock switching device is any A clock switching device described in a possible implementation manner. The third clock switching device is respectively connected to the main clock circuit and the backup clock circuit, and is used to receive the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The third clock switching device is also connected to the fifth processor for providing a clock signal to the fifth processor.

In a possible implementation manner, the second node server further includes a fourth clock switching device and a sixth processor; the fourth clock switching device is the clock described in any possible implementation manner in the second aspect above Switch device. The fourth clock switching device is respectively connected to the main clock circuit and the backup clock circuit, and is used for receiving the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The fourth clock switching device is also connected to the sixth processor for providing a clock signal to the sixth processor.

In a possible implementation manner, the second node server further includes a seventh processor and a third node controller, and the seventh processor and the third node controller are respectively switched to the fourth clock device connection. The second node server further includes an eighth processor and a fourth node controller, the eighth processor and the fourth node controller are respectively connected to the fourth clock switching device, and the first node controls controller, the second node controller, the third node controller and the fourth node controller are connected.

Description of drawings

FIG. 1 is a schematic structural diagram of a clock system provided by an embodiment of the present application;

FIG. 2 is a schematic flowchart of a clock switching method provided in Embodiment 1 of the present application;

FIG. 3 is a schematic timing diagram of a clock signal provided in Embodiment 1 of the present application;

FIG. 4 is a schematic structural diagram of a clock switching device provided in Embodiment 1 of the present application;

FIG. 5 is a schematic structural diagram of a clock switching device provided in Embodiment 2 of the present application;

FIG. 6 is a schematic flowchart of a clock switching method provided in Embodiment 2 of the present application;

FIG. 7 is a schematic structural diagram of a clock switching device provided in Embodiment 3 of the present application.

Detailed ways

The technical solutions in the embodiments of the present application are described below with reference to the drawings in the embodiments of the present application.

In the case of a clock source failure, in order to ensure that the operation of the node server is not affected, the clock system provided by the embodiment of the present application adopts a clock source redundancy design, and uses two main and standby clock circuits as the clock source of the node server. 1. Prepare two clock circuits to provide clock signals for the node server. When the clock signal provided by one of the clock circuits is abnormal, the node server receives the clock signal provided by the other clock circuit. For a specific implementation of the clock system, reference may be made to FIG. 1 , which is a schematic structural diagram of a clock system provided in an embodiment of the present application. As shown in FIG. 1 , the clock system at least includes a main clock circuit 101 , a backup clock circuit 102 and at least one node server 103 . When the clock system is normal, the node server 103 is used to obtain the main clock signal from the main clock circuit 101 , and when the main clock signal provided by the main clock circuit is detected to be abnormal, the node server is used to obtain the backup clock signal from the backup clock circuit 102 . At least one node server 103 in the clock system may be a single-processor server or a multi-processor server. The node server 103 includes one processor 105 if the node server 103 is a single processor server. If the node server 103 is a multiprocessor server, the node server 103 includes a plurality of processors 105 . If the clock system includes at least two node servers 103, all node servers 103 are combined into a multi-processor service system running an operating system.

There is a phase difference between the standby clock signal obtained by the node server from the standby clock circuit and the main clock signal before the abnormality. The operation of the node server is unstable. The node server reconstructs the phase of the switched standby clock signal through the switching circuit according to the phase difference between the standby clock signal and the main clock signal before the abnormality. The phase of the reconstructed clock signal is the same as The phases of the main clock signal supplied by the main clock circuit before the abnormality match. During specific implementation, as shown in Figure 1, the node server 103 includes a processor 105 and a switching circuit 104 corresponding to the processor 105, the processor 105 is connected to the switching circuit 104 corresponding to it, and the switching circuit 104 is connected to the master clock circuit 101 respectively. , The standby clock circuit 102 is connected. When the main clock signal provided by the main clock circuit 101 is abnormal, the node server 103 switches the clock source through the switching circuit 104 and obtains the standby clock signal from the standby clock circuit 102 . After acquiring the standby clock signal, the node server 103 determines the phase difference between the standby clock signal and the pre-abnormal master clock signal according to the pre-recorded master clock signal, and reconstructs the phase of the switched standby clock signal according to the phase difference.

The clock system may include multiple processors and at least two switching circuits, for example, the clock system includes a multiprocessor server and at least two switching circuits, wherein at least one processor in the multiprocessor server corresponds to one switching circuit; Or the clock system includes a multiprocessor service system composed of at least two node servers and at least two switch circuits, wherein at least one processor in each node server corresponds to a switch circuit in the node server. In a clock system including multiple processors, the TSCs of each processor provide a high-precision clock signal for the same operating system kernel. The operating system of the node server where the processor is located can work normally only when the counting frequency and phase of the TSC in each processor are consistent.

In an existing clock system including multiple processors and at least two switching circuits, different switching circuits have different processing deviations when reconstructing the same clock signal, so different switching circuits reconstruct the phase of the standby clock signal There is a phase deviation between the clock signals obtained later, and the phase deviation may be different, resulting in inconsistent phases of the clock signals provided to the TSCs of the processors, thereby affecting the normal operation of the operating system of the server.

In the clock system provided by the embodiment of the present application, for a clock system including multiple processors and at least two switching circuits, in order to solve the different processing deviations when different existing switching circuits reconstruct the same standby clock signal , resulting in the inconsistency of the phases of the clock signals of the TSCs provided to each processor, the switching circuit reconstructs the standby clock signal, and after generating the reconstructed clock signal, adjusts the speed according to the standby clock signal and the preset phase. The phase of the reconstructed clock signal is compensated to generate a compensated clock signal. Since the phase of the compensated clock signal is consistent with the phase of the standby clock signal, it is solved that each switching circuit performs phase reconstruction on the same standby clock signal. There is a problem of phase deviation between the obtained clock signals.

The clock system provided by the embodiment of the present application can be implemented with reference to FIG. 1 , and the node server 103 can at least include at least one switching circuit 104 and at least one processor 105 . Each switching circuit 104 is connected to one or more processors 105 . The switching circuit 104 is connected with the main clock circuit 101 and the standby clock circuit 102 respectively, and is used for receiving the main clock signal provided by the main clock circuit 101 when the main clock signal provided by the main clock circuit 101 is normal, and providing the main clock signal to The processor 105 that is connected with switching circuit 104; When the main clock signal that main clock circuit 101 provides is abnormal, will receive main clock signal from main clock circuit 101 and switch to receive standby clock signal from standby clock circuit 102, and this standby clock The phase of the signal is reconstructed and provided to the processor 105 connected to the switching circuit 104, and the phase of the reconstructed clock signal is consistent with the phase of the clock signal provided by the main clock circuit.

Exemplarily, in the clock system shown in FIG. 1 , the connection between the main clock circuit and the backup clock circuit and each switching circuit can be realized through cables or synchronous Ethernet. The main and standby clock circuits adopt a dual-plane network structure, and the standby clock circuit realizes the synchronization of the main and standby clocks through an interlocking path. The interlocking path between the main and standby clock circuits can be realized through cables, backplanes or synchronous Ethernet. . If synchronous Ethernet is used to realize the connection between the main and standby clock circuits, as well as the connection between the main and standby clock circuits and the switching circuit, problems such as complicated line management and high cost caused by cable connection can be reduced.

Exemplarily, in the clock system shown in FIG. 1 , the clock source of the main clock circuit 101 is provided by the phase-locked loop of the main clock circuit 101 from the free oscillation of the local clock included in the main clock circuit 101 circuit, and the backup clock circuit 102 is provided by the mutual The lock path tracks the frequency of the clock signal provided by the main clock circuit 101 , so that the frequency of the clock signal provided by the standby clock circuit 102 is consistent with the frequency of the clock signal provided by the main clock circuit 101 . Therefore, there is no need for additional high-precision clock source equipment in the clock system to provide clock signals for the main and backup clock circuits, but the free oscillation of the local clock oscillators of each clock circuit provides the clock source for the phase-locked loop of the clock circuit, thereby reducing Requirements for communications, computer equipment costs, and data center room deployment. And, exemplary, a node server may be a physical node server, such as a server rack group. When a node server is a server cabinet, considering the high cost of connecting all the processors in the entire cabinet to the same backplane, multiple processors can be connected to one backplane, and multiple backplanes are connected to each other. connect. A node controller and at least one processor are arranged on a backplane. Wherein, a node controller (Node Controller, NC) is used to manage and control processors on one backplane, and node controllers on different backplanes are interconnected through cables or optical fibers. By interconnecting different node servers or node controllers on different backplanes, processor remote memory access can be realized. During specific implementation, each node controller is connected with cables or optical fibers through a cross-frame high-speed interconnection bus. The clock signals provided by each switching circuit are of the same source, so that the clock frequency and phase at both ends of the interconnection bus between the interconnected node controllers are the same, reducing the transmission delay on the interconnection bus and ensuring the remote memory between different processors access performance. And, for example, the processor may be a calculation core and a control core (control unit) of a multi-processor server. A processor may include one or more processor cores (core). The processor can be a very large scale integrated circuit. It can be understood that, in the embodiment of the present application, the Core in the processor may be, for example, a central processing unit (central processing unit, CPU) or other specific integrated circuit (application specific integrated circuit, ASIC). Exemplarily, as shown in FIG. 1 , the switching circuit 104 can distribute the clock signal to different processors 105 , node controllers 106 or other devices through the fan-out expander 107 . Exemplarily, for devices belonging to one cache coherency bus domain, the same switching circuit 104 provides clock signals through the fan-out expander 107 .

As shown in FIG. 1 , the node server 103 includes at least two switching circuits 104. When the main clock signal provided by the main clock circuit 101 is abnormal, multiple switching circuits 104 simultaneously perform clock switching and phase reconstruction of the clock signal. At this time, due to the unavoidable device differences between the switching circuits 104, there is a phase deviation between the clock signals obtained after the phase reconstruction of the standby clock signal provided by the standby clock circuit 102 by each switching circuit 104, resulting in the The phases of the clock signals of the TSC of the controller 105 are inconsistent, which affects the normal operation of the operating system of the server. Further, when the clock signal provided by the standby clock circuit 102 is abnormal, the switching circuit 104 performs clock switching and phase reconstruction of the clock signal again, and the phase of the clock signal reconstructed by the switching circuit 104 this time is the same as that of the clock reconstructed by the switching circuit last time. The phases of the signals are consistent, but there are still phase deviations between different switching circuits when performing phase reconstruction. Therefore, as the number of times the switching circuits 104 perform clock switching increases, the phase deviation between the phases of the clock signals of the TSCs provided by each switching circuit 104 to each processor 105 becomes larger and larger. For example, the main clock circuit 101 provides the main clock signal clk1, and the backup clock circuit 102 provides the backup clock signal clk2. When clk1 is abnormal, the first switching circuit reconstructs the phase of clk2 according to clk1 to obtain clk2_1, and the second switching circuit performs phase reconstruction of clk2 according to clk1. clk2 performs phase reconstruction to obtain clk2_2, and there is a phase deviation Δ1 between clk2_1 and clk2_2. When clk2 is abnormal, the switching circuit receives the repaired clk1 again. At this time, the first switching circuit reconstructs the phase of clk1 according to clk2_1 to obtain clk3_1, and the second switching circuit reconstructs the phase of clk1 according to clk2_2 to obtain clk3_2. The difference between clk3_1 and clk3_2 There is a phase deviation Δ1+Δ2 between them. When clk1 is abnormal again, the switching circuit receives the repaired clk2 again. At this time, the first switching circuit reconstructs the phase of clk2 according to clk3_1 to obtain clk4_1, and the second switching circuit reconstructs the phase of clk2 according to clk3_2 to obtain clk4_2, clk4_1 and clk4_2 There is a phase deviation Δ1+Δ21+Δ3 between them.

In order to solve the above problems, the embodiment of the present application provides a clock switching method. The switching circuit 104 reconstructs the standby clock signal, and after generating the reconstructed clock signal, performs phase compensation on the reconstructed clock signal so that the compensated clock The phase of the signal is consistent with the phase of the standby clock signal, which solves the problem of phase deviation between the clock signals obtained after each switching circuit reconstructs the phase of the standby clock signal.

The clock switching method provided by the embodiment of the present application will be described in detail below in conjunction with specific embodiments. Embodiments of the present application provide, on the one hand, a clock switching method. FIG. 2 is a schematic flowchart of a clock switching method provided in Embodiment 1 of the present application. As shown in FIG. 2 , the clock switching method provided in this embodiment is applied to the node server 103 in the clock system shown in FIG. 1 , and the execution subject may be, for example, the switching circuit 104 . In this embodiment, when switching the clock signal, the switching circuit 104 firstly performs phase reconstruction on the standby clock signal provided by the standby clock circuit 102, and then performs phase compensation on the reconstructed clock signal, so that the phase of the adjusted clock signal is the same as that of the standby clock. The phases of the standby clock signals provided by the circuit 102 are consistent, thereby avoiding phase differences between the reconstructed clock signals that may be caused by device differences between different switching circuits 104 . As shown in Figure 2, the clock switching method provided in this embodiment includes:

S201. Receive a standby clock signal through a standby clock signal input port of a switching circuit when an abnormality of the main clock signal is detected.

Wherein, the main clock signal is provided by the main clock circuit connected to the switching circuit, and the backup clock signal is provided by the backup clock circuit connected to the switching circuit.

Exemplarily, when the main clock signal is normal, the first circuit provides the main clock signal to the first load after receiving the main clock signal, and the main clock signal is provided by the main clock circuit connected to the first circuit. When the main clock signal is abnormal, the first circuit receives the backup clock signal, and the backup clock signal is provided by the backup clock circuit connected to the first circuit. Wherein, the first circuit may be, for example, the switching circuit 104 in FIG. 1 , and the first load may be, for example, one or more processors 105 in FIG. 1 .

Exemplarily, when the switching circuit detects that the main clock signal is abnormal, the switching circuit starts clock switching. Exemplarily, when the switching circuit detects or receives a failure of the main clock circuit, a failure of the connection line between the main clock circuit and the switching circuit, a failure of the connection line between the standby clock circuit and the main clock circuit, or a frequency difference between the main and standby clock signals exceeds the preset When setting the range, etc., it can be considered that the main clock signal is abnormal. Exemplarily, when the switching circuit receives the clock switching instruction, it may also consider that the main clock signal is abnormal, and start clock switching. When the switching circuit performs clock switching, it receives the standby clock signal provided by the standby clock circuit. Exemplarily, the switching circuit also stops receiving the main clock signal provided by the main clock circuit, and reminds the user to perform troubleshooting on the main clock circuit. At this time, the backup clock circuit is used as the new main clock circuit, and when the main clock circuit returns to normal, it is used as the new backup clock circuit, and the clock switching processing method remains unchanged.

Exemplarily, when the main clock signal provided by the main clock circuit is normal and the backup clock signal provided by the backup clock circuit is abnormal, clock switching is not performed, and the user is only reminded to perform troubleshooting so that the backup clock circuit resumes normal operation.

S202. Reconstruct the phase of the standby clock signal, and generate a reconstructed clock signal, where the phase of the reconstructed clock signal is consistent with the phase of the primary clock signal before the abnormality.

Exemplarily, the first circuit reconstructs the phase of the standby clock signal to generate a first reconstructed clock signal, and the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality; the first circuit provides the first load with the first - Reconstruct the clock signal.

Exemplarily, FIG. 3 is a schematic timing diagram of clock signals provided in Embodiment 1 of the present application. There is a phase difference between the standby clock signal provided by the standby clock circuit and the main clock signal provided by the main clock circuit, as shown in FIG. 3 . When the switching circuit stops receiving the main clock signal provided by the main clock circuit and receives the backup clock signal provided by the backup clock circuit, there is a situation that the phase of the clock signal changes greatly. In this embodiment, the switching circuit reconstructs the phase of the received standby clock signal to generate a reconstructed clock signal. The phase of the reconstructed clock signal is consistent with the phase of the main clock signal provided by the main clock circuit before the abnormality, avoiding the Processor instability caused by the phase difference between the main and standby clock signals.

Exemplarily, in FIG. 3, the phase of the standby clock signal provided by the standby clock circuit lags behind the phase of the main clock signal provided by the main clock circuit as an example. Those skilled in the art understand that the phase of the standby clock signal provided by the standby clock circuit may also be ahead of the main clock signal. The phase of the main clock signal provided by the clock circuit is not limited in this embodiment of the present application.

Optionally, the process of switching the circuit to perform phase reconstruction may specifically include:

The switching circuit reconstructs the phase of the standby clock signal according to the phase difference, and generates the reconstructed clock signal, where the phase difference is the phase difference between the standby clock signal and the main clock signal before abnormality.

Exemplarily, when the switching circuit performs phase reconstruction, it can reconstruct the phase of the standby clock signal according to the phase difference between the main clock signal before the abnormality and the standby clock signal received by the switching circuit after the abnormality, and the reconstructed clock signal The phase of depends on the phase and phase difference of the standby clock signal. Exemplarily, when performing phase reconstruction, first, the phase difference is obtained and stored according to the main clock signal before the abnormality and the backup clock signal received by the switching circuit after the abnormality. Since it is impossible for different switching circuits to be completely consistent, there may be deviations in the calculation process of the phase difference between the switching circuits. It is possible to further expand the phase deviation.

S203. Compensate the phase of the reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed, and generate a compensated clock signal, output the compensated clock signal through the clock signal output port of the switching circuit, and the compensated clock signal The phase of the clock signal is consistent with the phase of the standby clock signal.

Exemplarily, the first circuit continuously adjusts the phase of the first reconstructed clock signal according to the backup clock signal and the preset phase adjustment speed to generate multiple adjusted clock signals, and the phase of the last generated adjusted clock signal among the multiple adjusted clock signals Equal to the phase of the standby clock signal, except for the last generated adjustment clock signal, the phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phase of the first reconstruction clock signal and the phase of the standby clock signal; the first circuit every After the second adjustment, the adjusted clock signal generated after adjustment is provided to the first load.

Exemplarily, considering that there is a phase deviation between the phases of the reconstructed clock signals obtained after phase reconstruction by different switching circuits, and the phase deviation may accumulate as the number of switching times increases, the reconstructed clock signal in this embodiment The phase of the signal is phase compensated to generate a compensated clock signal that is consistent with the phase of the standby clock signal. Since the phases of the compensated clock signals generated by different switching circuits are consistent with the phase of the standby clock signal provided by the standby clock circuit, Therefore, it is ensured that the phases of the clock signals provided by the switching circuits to the TSCs of the processors are consistent. At the same time, when the switching circuit performs multiple switching, since the switching circuit generates a clock signal consistent with the standby clock signal provided by the standby clock circuit after each clock switching, there is no deviation even if multiple clock switching is performed cumulative situation. For example, the main clock circuit provides the main clock signal clk1, and the backup clock circuit provides the backup clock signal clk2. When clk1 is abnormal, the first switching circuit reconstructs and compensates the phase of clk2 according to clk1 to obtain clk2, and the second switching circuit uses clk1 to clk2 performs phase reconstruction and compensation to obtain clk2, and there is no phase deviation between clock signals provided by the two switching circuits after clock switching. When clk2 is abnormal, the switching circuit receives the repaired clk1 again. At this time, the first switching circuit performs phase reconstruction and compensation on clk1 according to clk2 to obtain clk1, and the second switching circuit performs phase reconstruction and compensation on clk1 according to clk2 to obtain clk1. There is no phase deviation between the clock signals provided by the two switching circuits after clock switching. Exemplarily, as shown in FIG. 3 , the switching circuit adjusts the reconstructed clock signal to the standby clock signal according to the standby clock circuit and the preset phase adjustment speed. On the premise of ensuring that the phase of the clock signal does not change drastically, it also ensures that In the clock switching stage, the phase changes of the clock signals output by each switching circuit are consistent. Optionally, the value range of the preset phase adjustment speed is 1-10 microseconds/second.

The clock switching method provided by the embodiment of the present application is applied to a server including a switching circuit. When the switching circuit detects that the main clock signal is abnormal, it receives the standby clock signal through the standby clock signal input port of the switching circuit, and performs phase adjustment of the standby clock signal. Reconstruct and generate a reconstructed clock signal, the phase of the reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality; the phase of the reconstructed clock signal is compensated according to the standby clock signal and the preset phase adjustment speed, and A compensated clock signal is generated, and the compensated clock signal is output through the clock signal output port of the switching circuit, and the phase of the compensated clock signal is consistent with the phase of the standby clock signal. By performing phase compensation on the phase of the reconstructed clock signal according to the preset phase adjustment speed, a clock signal with the same phase as the standby clock signal is generated, which ensures that the phases of the clock signals compensated by multiple switching circuits change slowly and are consistent, so that each switch The phases of the clock signals provided by the circuit to the TSCs of each processor are consistent, avoiding the unstable operation of the multi-processor operating system and avoiding the cumulative error that may be caused by multiple clock switching.

Exemplarily, on the basis of the embodiment shown in FIG. 2 , this embodiment of the present application further provides a clock switching method. The method is applied to the clock system shown in Figure 1, the clock system includes a first node server, the first node server includes a first switching circuit and a second switching circuit, and loads connected to each switching circuit, the load includes at least one processor. Wherein, the first switching circuit is used to execute the clock switching method shown in FIG. 2 above, and the clock switching method performed by the second switching circuit includes:

S11. When the main clock signal is normal, the second circuit provides the main clock signal to the second load after receiving the main clock signal, and the main clock signal is provided by the main clock circuit connected to the second circuit;

S12. When the main clock signal is abnormal, the second circuit receives the backup clock signal, and the backup clock signal is provided by the backup clock circuit connected to the second circuit;

S13. The second circuit reconstructs the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality;

S14. The second circuit provides a second reconstruction clock signal to the second load;

S15. The second circuit continuously adjusts the phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate multiple compensation clock signals, and the phase of the last generated compensation clock signal among the multiple compensation clock signals is equal to the phase of the standby clock signal The phase of the clock signal, except for the last generated compensation clock signal, the phases of other compensation clock signals in the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal;

S16. The second circuit provides the adjusted and generated compensation clock signal to the second load after each adjustment.

Wherein, the second circuit may be, for example, the second switching circuit in FIG. 1 , and the second load may, for example, be the second processor and/or the fourth processor in FIG. 1 .

In the clock switching method provided in the embodiment of the present application, both switching circuits perform phase compensation on the phase of the reconstructed clock signal according to the preset phase adjustment speed, and generate a clock signal that is in phase with the standby clock signal, ensuring that the final generated clock signal is adjusted The phases of the clock signal and the compensation clock signal are consistent, ensuring that the phases of the clock signals compensated by multiple switching circuits change slowly and consistently, so that the phases of the clock signals provided by each switching circuit for the TSC of each processor are consistent, avoiding multiprocessing The unstable operation of the server operating system also avoids the cumulative error that may be caused by multiple clock switching.

Another aspect of the embodiments of the present application provides a clock switching device, which is used to implement the clock switching method in the above embodiment shown in FIG. 2 , and has the same or similar technical effects.

The clock switching device includes a first circuit such as the first switching circuit in Figure 1, and the first circuit is respectively connected to the main clock circuit 101, the backup clock circuit 102 and the first load; the first load can be exemplarily the the first processor and/or the third processor.

The first circuit is configured to, when the main clock signal is normal, provide the main clock signal to the first load after receiving the main clock signal, and the main clock signal is provided by the main clock circuit;

The first circuit is also used to receive the standby clock signal when the main clock signal is abnormal, and the standby clock signal is provided by the standby clock circuit;

The first circuit is further configured to reconstruct the phase of the standby clock signal to generate a first reconstructed clock signal, where the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality;

The first circuit is further configured to provide a first reconstruction clock signal to the first load;

The first circuit is further configured to continuously adjust the phase of the first reconstructed clock signal according to the backup clock signal and the preset phase adjustment speed to generate multiple adjusted clock signals, and the phase of the last generated adjusted clock signal among the multiple adjusted clock signals Equal to the phase of the standby clock signal, except for the last generated adjustment clock signal, the phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phase of the first reconstructed clock signal and the phase of the standby clock signal;

The first circuit is further configured to provide an adjusted clock signal generated after adjustment to the first load after each adjustment.

Optionally, the clock switching device further includes a second circuit such as the second switching circuit in FIG. 1; the second circuit is respectively connected to the main clock circuit 101, the backup clock circuit 102 and the second load, and the second load can illustratively be is the second processor and/or the fourth processor in FIG. 1 .

The second circuit is used to, when the main clock signal is normal, provide the main clock signal to the second load after receiving the main clock signal, and the main clock signal is provided by the main clock circuit;

The second circuit is also used to receive the standby clock signal when the main clock signal is abnormal, and the standby clock signal is provided by the standby clock circuit;

The second circuit is also used to reconstruct the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality;

The second circuit is also used to provide a second reconstruction clock signal to the second load;

The second circuit is further configured to continuously adjust the phase of the second reconstructed clock signal according to the backup clock signal and the preset phase adjustment speed to generate multiple compensated clock signals, and the phase of the last generated compensated clock signal among the multiple compensated clock signals Equal to the phase of the standby clock signal, except for the last generated compensation clock signal, the phases of other compensation clock signals in the multiple compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal;

The second circuit is also used for providing the adjusted and generated compensation clock signal to the second load after each adjustment.

Another aspect of the embodiments of the present application provides a clock switching device, configured to implement the clock switching method in the foregoing embodiments. FIG. 4 is a schematic structural diagram of a clock switching device provided in Embodiment 1 of the present application. The clock switching device in this embodiment may be, for example, the switching circuit 104 in FIG. 1 . As shown in Figure 4, clock switching device 400 comprises: control circuit 401 and phase-locked loop circuit 402; The input port is connected, and the output port of the phase-locked loop circuit 402 is connected with the clock signal output port of the clock switching device; the control circuit 401 is connected with the phase-locked loop circuit 402; wherein,

When the control circuit 401 detects that the main clock signal is abnormal, it receives the standby clock signal through the standby clock signal input port of the clock switching device 400, and sets the working state of the phase-locked loop circuit 402 to the phase reconstruction state;

When the phase-locked loop circuit 402 is in the phase reconstruction state, the phase of the standby clock signal is reconstructed, and a reconstructed clock signal is generated, and the phase of the reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality;

The control circuit 401 sets the working state of the phase-locked loop circuit 402 to the phase compensation state when the phase-locked loop circuit 402 generates the reconstructed clock signal;

When the phase locked loop circuit 402 is in the phase compensation state, it compensates the phase of the reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed, and generates the compensated clock signal.

Exemplarily, as shown in FIG. 4 , a clock switching device 400 includes a control circuit 401 and a phase-locked loop circuit 402 . The control circuit 401 is respectively connected to the main clock signal input port and the backup clock signal input port of the clock switching device 400, and receives the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The control circuit 401 is also connected to the reference input port of the phase-locked loop circuit 402 , and is used to select a clock signal from the main and standby clock signals to send to the reference input port of the phase-locked loop circuit 402 . The exemplary control circuit 401 is also used to monitor the main clock signal. When the main clock signal is detected to be abnormal, the control circuit 401 stops receiving the main clock signal, receives the standby clock signal through the standby clock signal input port of the clock switching device 400, and sends The standby clock signal is sent to the PLL circuit 402.

Exemplarily, when the control circuit 401 detects that the main clock signal is abnormal and needs to switch clocks, the control circuit 401 successively controls the phase-locked loop circuit 402 to be in different working states, so that the phase-locked loop circuit 402 respectively performs phase reconstruction of the clock signal and phase compensation. Exemplarily, the phase-locked loop circuit 402 is provided with a register, and the register is used to store configuration parameters of the phase-locked loop circuit 402 , and different configuration parameters correspond to different working states of the phase-locked loop circuit 402 . The control circuit 401 can control the phase-locked loop circuit 402 to be in different working states by modifying the configuration parameters in the registers of the phase-locked loop circuit 402 .

Exemplarily, when the control circuit 401 detects that the master clock signal is abnormal, it first controls the phase-locked loop circuit 402 to be in the phase reconstruction working state.

When the phase-locked loop circuit 402 was working in the phase reconstruction working state, the phase-locked loop circuit 402 received the standby clock signal through the reference input port, and at the same time, the internal oscillator of the phase-locked loop circuit 402 and the frequency discriminator/phase detector The feedback path provides the main clock signal before the abnormality to the phase-locked loop circuit 402, and the phase-locked loop circuit 402 acquires and stores the phase difference between the backup clock signal and the main clock signal before the abnormality, and receives the phase-locked loop circuit 402 according to the stored phase difference. The phase of the received standby clock signal is gradually adjusted, so that the phase of the clock signal output from the output terminal of the phase-locked loop circuit 402 is consistent with the phase of the main clock signal before the abnormality.

Exemplarily, the phase-locked loop circuit 402 detects the phase difference between the phase of the clock signal provided by the output port and the phase of the standby clock signal received by the phase-locked loop circuit 402 in real time, and determines that the phase difference obtained by the real-time detection and the main clock Whether the difference between the stored phase differences when the signal is abnormal is within a preset range, and if so, it is confirmed that the phase reconstruction is completed.

At this time, the control circuit 401 reconfigures the configuration parameters of the phase-locked loop circuit 402, and controls the phase-locked loop circuit 402 to work in a phase compensation state. When the working state of the phase-locked loop circuit 402 is the phase compensation state, the phase-locked loop circuit 402 performs phase compensation on the reconstructed clock signal fed back to the frequency/phase detector by the oscillator according to the received standby clock signal, so that The phase of the clock signal output by the oscillator is gradually approached to the phase of the standby clock signal until the phase of the clock signal output by the oscillator is the same as the phase of the standby clock signal.

The clock switching device provided in this embodiment includes a control circuit and a phase-locked loop circuit. The control circuit is used to control the working state of the phase-locked loop circuit. The clock signal and the standby clock signal perform phase reconstruction on the phase of the standby clock signal to obtain the reconstructed clock signal, which avoids the sudden change of the phase of the clock signal when the clock is switched. After the phase reconstruction is completed, the working state of the phase-locked loop circuit changes. In the phase compensation state, the phase-locked loop circuit gradually changes the phase of the reconstructed clock signal to be consistent with the standby clock signal, so that the phases of the clock signals provided by each switching circuit for the TSC of each processor are consistent, and the clock switching device adopts the control The circuit controls the way that the phase-locked loop circuit works in different working states, the phase reconstruction and phase compensation of the clock signal are realized by a phase-locked loop circuit, and the switching circuit structure is simple.

Exemplarily, on the basis of the embodiment shown in FIG. 4 , an embodiment of the present application further provides a clock switching device. FIG. 5 is a schematic structural diagram of a clock switching device provided in Embodiment 2 of the present application. As shown in Figure 5, in the clock switching device provided by this embodiment, the clock signal output port of the clock switching device is also connected to the feedback clock signal input port of the clock switching device, and the feedback clock signal input port of the clock switching device is connected to the phase-locked loop circuit The feedback input port is connected to form a zero-delay feedback path of the clock switching device. Correspondingly, in combination with the embodiment shown in FIG. 5 , on the basis of the embodiment shown in FIG. 2 , this embodiment of the present application also provides a clock switching method, in which the clock switching device receives the feedback clock signal output from the clock signal output port , performing phase compensation on the reconstructed clock signal according to the feedback clock signal, so that the phase of the clock signal output by the clock signal output port of the clock switching device is completely consistent with that of the standby clock signal. FIG. 6 is a schematic flowchart of a clock switching method provided in Embodiment 2 of the present application. As shown in Figure 6, clock switching methods include:

S601. When the control circuit detects that the main clock signal is abnormal, it receives the standby clock signal through the standby clock signal input port of the clock switching device; the phase-locked loop circuit stops receiving the feedback clock signal through the feedback input port of the phase-locked loop circuit, and the feedback clock signal It is the clock signal input by the feedback clock signal input port of the clock switching device.

Exemplarily, when the control circuit detects that the main clock signal is abnormal, the control circuit disconnects the zero-delay feedback path. Specifically, the control circuit sets the working state of the phase-locked loop circuit, so that the phase-locked loop circuit stops receiving the feedback clock signal through the feedback input port of the phase-locked loop circuit, that is, stops receiving the clock signal output by the clock signal output port of the clock switching device . Exemplarily, a register is set in the phase-locked loop circuit, and the information stored in the register is an enable signal for whether the phase-locked loop circuit enables the zero-delay feedback path. When the control circuit controls the zero-delay feedback path to be turned on, the control circuit writes the first value to the register, and when the phase-locked loop circuit reads that the value in the register is the first value, the zero-delay feedback path is enabled. Pass. When the control circuit controls the zero-delay feedback path to be disconnected, the control circuit writes the second value into the register, and when the value read by the phase-locked loop circuit in the register is the second value, the zero-delay feedback path cannot be enabled is turned on, that is, the zero-delay feedback path is turned off.

S602. The phase-locked loop circuit reconstructs the phase of the standby clock signal, and generates a reconstructed clock signal. The phase of the reconstructed clock signal is consistent with the phase of the main clock signal before the abnormality.

Exemplarily, S602 in this embodiment is the same as S202 in the embodiment shown in FIG. 2 , which will not be repeated in this application.

S603. The phase-locked loop circuit stops receiving the clock signal provided by the oscillator of the phase-locked loop circuit, and receives the feedback clock signal through the feedback input port of the phase-locked loop circuit.

Exemplarily, in an actual clock switching device, there may be devices such as deletion expanders and buffers between the output terminal of the phase-locked loop circuit and the clock signal output port of the clock switching device, so that the clock signal output port of the clock switching device outputs The phase of the clock signal is inconsistent with the phase of the clock signal output from the output terminal of the phase-locked loop circuit. Although the phase-locked loop circuits of each clock switching device can control the clock signal at the output end of each phase-locked loop circuit to be consistent with the standby clock signal after performing phase compensation, because the output end of the phase-locked loop circuit and the clock of the clock switching device The devices between the signal output ports are not exactly the same, and there may be phase inconsistencies between the clock signals output by the clock signal output ports of different clock switching devices. Therefore, after the phase-locked loop circuit generates the reconstructed clock signal, the phase-locked loop circuit disconnects the feedback path inside the phase-locked loop circuit, and after the reconstruction of the clock signal output port output of the clock switching device according to the zero-delay feedback path Phase compensation is performed on the phase of the clock signal of the clock signal, so that the phase of the clock signal output by the clock signal output port of the clock switching device is consistent with the phase of the standby clock signal, thereby ensuring that the clock signals output by the clock signal output ports of different clock switching devices are consistent with the The standby clock signals are consistent, and there is no phase inconsistency between them.

S604. The phase-locked loop circuit compensates the phase of the reconstructed clock signal according to the standby clock signal, the feedback clock signal and the preset phase adjustment speed, and generates a compensated clock signal, and passes the compensated clock signal through the clock switching device. The clock signal output port outputs, and the phase of the compensated clock signal is consistent with the phase of the standby clock signal.

Exemplarily, the phase-locked loop circuit adjusts the speed according to the standby clock signal, the feedback clock signal output by the clock signal output port of the clock switching device, and the preset phase, and adjusts the output of the reconstructed clock signal output by the clock signal output port of the clock switching device. Phase compensation is performed, and the phase of the generated compensated clock signal is consistent with the phase of the standby clock signal.

Exemplarily, when the control circuit detects that the standby clock signal is abnormal, the control circuit receives the main clock signal from the repaired main clock circuit, and disconnects the zero-delay feedback path. Exemplarily, the control circuit also controls the phase-locked loop circuit to start receiving the clock signal provided by the oscillator of the phase-locked loop circuit, so as to perform phase reconstruction again.

In the clock switching method provided by the embodiment of the present application, in the phase compensation process, the phase of the reconstructed clock signal is compensated according to the standby clock signal and the feedback clock signal output from the clock signal output port of the clock switching device, and a compensated clock is generated. signal, so that the phase of the compensated clock signal is consistent with the phase of the standby clock signal, thereby ensuring that the phases of the clock signals provided by all clock switching devices to the processor are completely consistent.

Optionally, on the basis of any of the above-mentioned embodiments, the frequency of the first clock signal provided by the standby clock circuit may be determined according to the average frequency of the clock signal provided by the main clock circuit within a preset time period.

Exemplarily, as shown in FIG. 1, the standby clock circuit monitors the frequency of the clock signal provided by the main clock circuit through an interlock path, and obtains the frequency of the clock signal provided by the main clock circuit within a preset time period with a preset time period as a cycle. Frequency average, used as the frequency of the standby clock signal. By using two clock circuits to supply power to the processors of the processors in the multi-processor server system, the stability of the clock source is improved, and it is avoided to use a single stable and accurate clock source to provide power to each processor at the same time through two active and standby clock circuits. The clock signal reduces the clock cost of the clock system.

Optionally, on the basis of any of the above-mentioned embodiments, the abnormality of the main clock signal detected by the switching circuit may be any of the following illustratively: the switching circuit receives the failure indication information of the main clock circuit sent by the standby clock circuit; Or, the switching circuit detects that the main clock signal is interrupted; or, the switching circuit receives a clock switching instruction.

Exemplarily, when the main clock circuit fails or the connection line between the main clock circuit and the switching circuit fails, the switching circuit can detect that the main clock signal sent by the main clock circuit is interrupted. Clock switching.

Optionally, when the backup clock circuit detects the loss of the clock signal on the interlock path or detects that the frequency deviation exceeds a preset threshold, it sends the main clock circuit failure indication information to the switching circuit.

Exemplarily, the standby clock circuit monitors the clock signal provided by the main clock circuit through the interlock path. When the standby clock circuit detects that there is no clock signal on the interlock path, it considers that the main clock circuit is faulty, or when the standby clock circuit detects that the main clock When the frequency deviation between the frequency of the clock signal provided by the circuit and the frequency of the clock signal provided by the standby clock circuit is greater than the preset threshold, it is also considered that the main clock circuit is faulty. At this time, the standby clock circuit sends a failure indication of the main clock circuit to the switching circuit information.

Exemplarily, the clock switching methods provided by the embodiments of the present application are also applicable to other distributed structures that need to ensure the same clock source. For example, in a multi-processor server composed of multiple ARM processors, the clock sources of different ARM processors need to be consistent. As another example, in a network memory system composed of multiple storage units, the clock sources among the storage units need to be consistent. Exemplarily, the clock switching methods provided by the various embodiments of the present application can avoid problems such as large-scale transients and phase discontinuities of the clock signal phase during the clock switching process, so it is also applicable to any clock source that requires a stable clock source and requires relatively high clock phase accuracy. High equipment, such as computers, servers, routers, base stations and other network equipment.

On the other hand, the embodiment of the present application also provides a clock switching device, which is used to implement the clock switching method in any of the above embodiments, and has the same technical effect, and the present application will not repeat it here.

An embodiment of the present application provides a clock switching device. FIG. 7 is a schematic structural diagram of a clock switching device provided in Embodiment 3 of the present application. As shown in Figure 7, the clock switching device includes:

The first clock signal acquisition module 701 is configured to provide the main clock signal to the first load after receiving the main clock signal when the main clock signal is normal, and the main clock signal is provided by the main clock circuit connected to the first clock signal acquisition module 701 ;

The first clock signal acquisition module 701 is also used to receive the backup clock signal when the main clock signal is abnormal, and the backup clock signal is provided by the backup clock circuit connected to the first clock signal acquisition module 701;

The first reconstruction module 702 is configured to reconstruct the phase of the standby clock signal to generate a first reconstruction clock signal, the phase of the first reconstruction clock signal is consistent with the phase of the main clock signal before the abnormality; provide the first reconstruction to the first load clock signal;

The first adjustment module 703 is configured to continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate multiple adjusted clock signals, and the last generated adjusted clock signal among the multiple adjusted clock signals The phase is equal to the phase of the standby clock signal, except for the last generated adjustment clock signal, the phases of other adjustment clock signals in the multiple adjustment clock signals are between the phase of the first reconstruction clock signal and the phase of the standby clock signal; each adjustment Afterwards, the adjusted clock signal generated after adjustment is provided to the first load.

Optionally, as shown in Figure 7, the clock switching device further includes:

The second clock signal acquisition module 704 is configured to provide the main clock signal to the second load after receiving the main clock signal when the main clock signal is normal, and the main clock signal is provided by the main clock circuit connected to the second clock signal acquisition module 704 ;

The second clock signal acquisition module 704 is also used to receive the backup clock signal when the main clock signal is abnormal, and the backup clock signal is provided by the backup clock circuit connected to the second clock signal acquisition module 704;

The second reconstruction module 705 is configured to reconstruct the phase of the standby clock signal to generate a second reconstruction clock signal, the phase of the second reconstruction clock signal is consistent with the phase of the main clock signal before the abnormality; provide the second reconstruction to the second load clock signal;

The second adjustment module 706 is configured to continuously adjust the phase of the second reconstruction clock signal according to the backup clock signal and the preset phase adjustment speed to generate multiple compensation clock signals, and the compensation clock signal generated last among the multiple compensation clock signals The phase is equal to the phase of the standby clock signal. Except for the last generated compensation clock signal, the phases of other compensation clock signals in the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal; each adjustment Afterwards, the adjusted and generated compensation clock signal is provided to the second load.

Optionally, as shown in FIG. 7 , the clock switching device further includes: a first control module 707 configured to set the first rebuilding module 702 to a working state when the main clock signal is abnormal. The first control module 707 is further configured to set the first adjustment module 703 to the working state after determining that the first reconstruction module 702 generates the first reconstruction clock signal.

Optionally, the clock switching device provides a clock signal to the first load through the clock signal output port of the clock switching device, the clock signal output port of the clock switching device is connected to the feedback clock signal input port of the clock switching device, and the feedback clock of the clock switching device The signal input port is connected to the feedback input port of the first adjustment module 703 .

The first control module 707 is also configured to close the feedback input port of the first adjustment module 703 and stop receiving clock switching from the feedback input port of the first adjustment module 703 before the first reconstruction module 702 reconstructs the phase of the standby clock signal The clock signal output by the clock signal output port of the device.

The first control module 707 is also used to close the first adjustment module before the first adjustment module 703 continuously adjusts the phase of the first reconstruction clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals The adjustment feedback port of 703 stops receiving the clock signal provided by the first adjustment module 703 from the adjustment feedback port of the first adjustment module 703 , and opens the feedback input port of the first adjustment module 703 .

The first adjustment module 703 is further configured to continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal, the clock feedback signal received from the feedback input port of the first adjustment module 703, and the preset phase adjustment speed to generate multiple Adjust the clock signal.

Optionally, the first reconstruction module 702 is further configured to reconstruct the phase of the standby clock signal according to the phase difference to generate the first reconstructed clock signal, where the phase difference is the phase difference between the standby clock signal and the main clock signal before the abnormality .

In a possible implementation manner, the clock switching device further includes:

A second control module, configured to set the second reconstruction module to a working state when the main clock signal is abnormal;

The second control module is further configured to set the second adjustment module to a working state after determining that the second reconstruction module generates the second reconstruction clock signal. The communication mode between the second control module, the second adjustment module and the second reconstruction module is the same as the communication mode between the first control module, the first adjustment module and the first reconstruction module, and the second control module communicates with the first reconstruction module. For the communication manner between the second adjustment module and the second reconstruction module, reference may be made to the communication manner between the first control module, the first adjustment module, and the first reconstruction module, and the details will not be repeated here.

Another aspect of the embodiment of the present application provides a server. The server includes one or more loads, and includes one or more clock switching devices with the same number as all loads, and all loads are connected to all clock switching devices in one-to-one correspondence, and the clock switching device is any one of the above-mentioned embodiments In the clock switching device, a clock signal output port of the clock switching device is connected to a corresponding load to provide a clock signal for the corresponding load.

Exemplarily, the server may be the node server 103 in FIG. 1 , the load in the server may be the processor 105 in FIG. 1 , and the clock switching device is the switching circuit 104 in FIG. 1 .

Optionally, another aspect of this embodiment of the present application also provides a clock system, as shown in FIG. 1 , including a main clock circuit 101, a backup clock circuit 102, and at least one server as in the above embodiment, and all clocks of all servers The switching device is connected to the main clock circuit 101 and the backup clock circuit 102 . Wherein, the server may be, for example, the node server 103 in FIG. 1 .

Optionally, as shown in FIG. 1, the load of the server includes at least one processor 105, or the load of the server includes at least one processor 105 and a node controller 106, and all processors 105 and node controllers 106 of the load are related to the load Corresponding clock switching devices are connected, and all node controllers 106 of all servers in the system are connected to each other.

Another aspect of the embodiment of the present application provides a clock system, as shown in Figure 1, including a first node server, a master clock circuit 101, and a backup clock circuit 102, and the first node server includes a first clock switching device and a first processor ; The first clock switching device is the clock switching device in any possible implementation manner above. The first clock switching device is respectively connected with the main clock circuit and the backup clock circuit, and is used for receiving the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The first clock switching device is also connected to the first processor for providing a clock signal to the first processor.

Optionally, the first node server further includes a second clock switching device and a second processor; the second clock switching device is the clock switching device in any possible implementation manner above. The second clock switching device is respectively connected with the main clock circuit and the backup clock circuit, and is used for receiving the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The second clock switching device is also connected to the second processor, and is used for providing a clock signal to the second processor.

Optionally, the first node server further includes a third processor and a first node controller, the third processor and the first node controller are respectively connected to the first clock switching device, and receive the clock signal provided by the first clock switching device . The first node server also includes a fourth processor and a second node controller, the fourth processor and the second node controller are respectively connected to the second clock switching device, the first node controller is connected to the second node controller, and receives The clock signal provided by the second clock switching device.

Optionally, the clock system further includes a second node server, and the second node server includes a third clock switching device and a fifth processor; the third clock switching device is the clock switching device in any possible implementation manner above. The third clock switching device is respectively connected with the main clock circuit and the backup clock circuit, and is used for receiving the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The third clock switching device is also connected to the fifth processor, and is used for providing a clock signal to the fifth processor.

Optionally, the second node server further includes a fourth clock switching device and a sixth processor; the fourth clock switching device is the clock switching device in any possible implementation manner above. The fourth clock switching device is respectively connected with the main clock circuit and the backup clock circuit, and is used for receiving the main clock signal provided by the main clock circuit and the backup clock signal provided by the backup clock circuit. The fourth clock switching device is also connected to the sixth processor, and is used for providing a clock signal to the sixth processor. Optionally, the second node server further includes a seventh processor and a third node controller, and the seventh processor and the third node controller are respectively connected to the fourth clock switching device. The second node server also includes an eighth processor and a fourth node controller, the eighth processor and the fourth node controller are respectively connected to the fourth clock switching device, the first node controller, the second node controller, the third The node controller is connected to the fourth node controller.

It should be noted that the embodiments provided in this application are only illustrative. Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above-mentioned embodiments, the descriptions of each embodiment have their own emphasis. Description of the example. The features disclosed in the embodiments of the present application and the drawings may exist independently or in combination. Features described in the form of hardware in the embodiments of the present application may be implemented by software, and vice versa. It is not limited here.

Those skilled in the art can appreciate that the method steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber) or wireless (eg, infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as an optical disk), or a semiconductor medium (such as a solid-state drive (SSD)) and other non-transitory devices that can store program codes. non-transitory machine-readable media.

In addition, it should be noted that it should be understood that the above division of each module of the main clock circuit, backup clock circuit, and clock synchronous switching circuit is only a division of logical functions. In actual implementation, there may be other division methods, such as multiple units Or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in this application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units. It should be noted that the embodiments provided in this application are only illustrative. Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above-mentioned embodiments, the descriptions of each embodiment have their own emphasis. Description of the example. The features disclosed in the embodiments of the present application and the drawings may exist independently or in combination. Features described in the form of hardware in the embodiments of the present application may be implemented by software, and vice versa. It is not limited here.

Claims (15)

1. A clock switching method, the method comprising:

when a main clock signal is normal, a first circuit receives the main clock signal and then provides the main clock signal to a first load, wherein the main clock signal is provided by a main clock circuit connected with the first circuit;

when the main clock signal is abnormal, the first circuit receives a standby clock signal, and the standby clock signal is provided by a standby clock circuit connected with the first circuit;

the first circuit reconstructs the phase of the standby clock signal to generate a first reconstructed clock signal, and the phase of the first reconstructed clock signal is consistent with the phase of the main clock signal before abnormality;

the first circuit provides the first reconstructed clock signal to the first load;

the first circuit continuously adjusts the phase of the first reestablished clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjustment clock signals, the phase of the adjustment clock signal generated last in the plurality of adjustment clock signals is equal to the phase of the standby clock signal, and except for the adjustment clock signal generated last, the phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phase of the first reestablished clock signal and the phase of the standby clock signal;

the first circuit provides the adjusted clock signal generated after adjustment to the first load after each adjustment.

2. The method of claim 1, further comprising:

when a master clock signal is normal, a second circuit receives the master clock signal and then provides the master clock signal for a second load, wherein the master clock signal is provided by the master clock circuit connected with the second circuit;

when the main clock signal is abnormal, the second circuit receives a standby clock signal, and the standby clock signal is provided by the standby clock circuit connected with the second circuit;

the second circuit reconstructs the phase of the standby clock signal to generate a second reconstructed clock signal, and the phase of the second reconstructed clock signal is consistent with the phase of the main clock signal before abnormality;

the second circuit provides the second reconstructed clock signal to the second load;

the second circuit continuously adjusts the phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, the phase of the last generated compensation clock signal in the plurality of compensation clock signals is equal to the phase of the standby clock signal, and except the last generated compensation clock signal, the phases of other compensation clock signals in the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal;

the second circuit provides the compensation clock signal generated after adjustment to the second load after each adjustment.

3. The method of claim 1 or 2, wherein the first circuit comprises a first control circuit and a first phase-locked loop circuit, the first control circuit being connected to the first phase-locked loop circuit;

the method further comprises the following steps: when the main clock signal is abnormal, the first control circuit sets the working state of the first phase-locked loop circuit to be a phase reconstruction state;

the first circuit reconstructs a phase of the standby clock signal to generate a first reconstructed clock signal, and includes:

when the working state of the first phase-locked loop circuit is a phase reconstruction state, reconstructing the phase of the standby clock signal to generate a first reconstruction clock signal;

the method further comprises the following steps: the first control circuit determines that the first phase-locked loop circuit generates the first reestablished clock signal, and sets the working state of the first phase-locked loop circuit to be a phase compensation state;

the first circuit continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, and the method comprises the following steps:

and when the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reestablished clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals.

4. The method of claim 3, wherein the first circuit provides a clock signal to the first load through a clock signal output port of the first circuit, wherein the clock signal output port of the first circuit is connected to a feedback clock signal input port of the first circuit, and wherein the feedback clock signal input port of the first circuit is connected to a feedback input port of the first phase-locked loop circuit;

the method further comprises the following steps: before the first phase-locked loop circuit reconstructs the phase of the standby clock signal, closing a feedback input port of the first phase-locked loop circuit, and stopping receiving the clock signal output by a clock signal output port of the first circuit from the feedback input port of the first phase-locked loop circuit;

the method further comprises the following steps:

before the first phase-locked loop circuit continuously adjusts the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, closing an oscillator feedback port of the first phase-locked loop circuit, stopping receiving the clock signal provided by the oscillator from the oscillator feedback port of the first phase-locked loop circuit, and opening a feedback input port of the first phase-locked loop circuit;

when the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, including:

and when the working state of the first phase-locked loop circuit is a phase compensation state, continuously adjusting the phase of the first reestablished clock signal according to the standby clock signal, the clock feedback signal received from the feedback input port of the phase-locked loop circuit and the preset phase adjustment speed to generate a plurality of adjusted clock signals.

5. The method according to claim 3 or 4, wherein the first phase-locked loop circuit reconstructs the phase of the standby clock signal to generate a first reconstructed clock signal when the operating state is a phase reconstruction state, and comprises:

and when the working state of the first phase-locked loop circuit is a phase reconstruction state, reconstructing the phase of the standby clock signal according to the phase difference to generate a first reconstruction clock signal, wherein the phase difference is the phase difference between the standby clock signal and the main clock signal before abnormality.

6. The method of any of claims 1 to 5, wherein the frequency of the standby clock signal is determined according to an average of the frequencies of the master clock signals provided by the master clock circuit over a preset time period.

7. A clock switching device is characterized by comprising a first circuit, a second circuit and a third circuit, wherein the first circuit is respectively connected with a main clock circuit, a standby clock circuit and a first load;

the first circuit is configured to provide a master clock signal to the first load after receiving the master clock signal when the master clock signal is normal, where the master clock signal is provided by the master clock circuit;

the first circuit is further configured to receive a standby clock signal when the master clock signal is abnormal, the standby clock signal being provided by the standby clock circuit;

the first circuit is further configured to reconstruct a phase of the standby clock signal to generate a first reconstructed clock signal, where the phase of the first reconstructed clock signal is consistent with a phase of the master clock signal before the abnormality;

the first circuit is further configured to provide the first reconstructed clock signal to the first load;

the first circuit is further configured to continuously adjust a phase of the first reconstructed clock signal according to the standby clock signal and a preset phase adjustment speed to generate a plurality of adjustment clock signals, where a phase of a last adjustment clock signal generated in the plurality of adjustment clock signals is equal to a phase of the standby clock signal, and except for the last adjustment clock signal generated in the plurality of adjustment clock signals, phases of other adjustment clock signals in the plurality of adjustment clock signals are between the phase of the first reconstructed clock signal and the phase of the standby clock signal;

the first circuit is further configured to provide the adjusted clock signal generated after adjustment to the first load after each adjustment.

8. The apparatus of claim 7, further comprising: a second circuit; the second circuit is respectively connected with the main clock circuit, the standby clock circuit and a second load;

the second circuit is configured to provide the master clock signal to the second load after receiving the master clock signal when the master clock signal is normal, where the master clock signal is provided by the master clock circuit;

the second circuit is further configured to receive a standby clock signal when the master clock signal is abnormal, the standby clock signal being provided by the standby clock circuit;

the second circuit is further configured to reconstruct a phase of the standby clock signal to generate a second reconstructed clock signal, where the phase of the second reconstructed clock signal is consistent with the phase of the master clock signal before the abnormality;

the second circuit is further configured to provide the second reconstructed clock signal to the second load;

the second circuit is further configured to continuously adjust a phase of the second reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of compensation clock signals, a phase of a last generated compensation clock signal of the plurality of compensation clock signals is equal to a phase of the standby clock signal, and except for the last generated compensation clock signal, phases of other compensation clock signals of the plurality of compensation clock signals are between the phase of the second reconstructed clock signal and the phase of the standby clock signal;

the second circuit is further configured to provide the compensated clock signal generated after the adjustment to the second load after each adjustment.

9. The apparatus of claim 7 or 8, wherein the first circuit comprises a first control circuit and a first phase-locked loop circuit, the first control circuit being connected to the first phase-locked loop circuit;

the first control circuit is used for setting the working state of the first phase-locked loop circuit to be a phase reconstruction state when the main clock signal is abnormal;

the first phase-locked loop circuit is used for reconstructing the phase of the standby clock signal to generate a first reconstructed clock signal when the working state is a phase reconstruction state;

the first control circuit is further configured to determine that the first phase-locked loop circuit generates the first reconstructed clock signal, and set an operating state of the first phase-locked loop circuit to a phase compensation state;

and the first phase-locked loop circuit is further configured to, when the operating state is the phase compensation state, continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjustment clock signals.

10. The apparatus of claim 9, wherein the first circuit provides a clock signal to the first load through a clock signal output port of the first circuit, wherein the clock signal output port of the first circuit is connected to a feedback clock signal input port of the first circuit, and wherein the feedback clock signal input port of the first circuit is connected to a feedback input port of the first phase-locked loop circuit;

the first phase-locked loop circuit is further configured to close a feedback input port of the first phase-locked loop circuit before reconstructing a phase of the standby clock signal, and stop receiving the clock signal output by the clock signal output port of the first circuit from the feedback input port of the first phase-locked loop circuit;

the first phase-locked loop circuit is further configured to, before continuously adjusting the phase of the first reconstructed clock signal according to the standby clock signal and the preset phase adjustment speed to generate a plurality of adjusted clock signals, close an oscillator feedback port of the first phase-locked loop circuit, stop receiving the clock signal provided by the oscillator from the oscillator feedback port of the first phase-locked loop circuit, and open a feedback input port of the first phase-locked loop circuit;

the first phase-locked loop circuit is further configured to, when the operating state is the phase compensation state, continuously adjust the phase of the first reconstructed clock signal according to the standby clock signal, a clock feedback signal received from a feedback input port of the phase-locked loop circuit, and the preset phase adjustment speed to generate a plurality of adjusted clock signals.

11. The apparatus according to claim 9 or 10, wherein the first phase-locked loop circuit is specifically configured to, when the operating state is a phase reconstruction state, reconstruct a phase of the standby clock signal according to a phase difference between the standby clock signal and the master clock signal before the abnormality to generate a first reconstructed clock signal.

12. The apparatus of any of claims 7 to 11, wherein the frequency of the standby clock signal is determined according to an average of the frequencies of the master clock signals provided by the master clock circuit over a preset time period.

13. A server, comprising one or more loads, and comprising one or more clock switching devices having the same number as that of all the loads, all the loads being connected to all the clock switching devices in a one-to-one correspondence, the clock switching devices being as claimed in any one of claims 7 to 12, a clock signal output port of the clock switching device being connected to the corresponding load to provide a clock signal to the corresponding load.

14. A clock system comprising a master clock circuit, a standby clock circuit and at least one server as claimed in claim 13, all clock switching means of all servers being connected to said master clock circuit and said standby clock circuit.

15. The system according to claim 14, wherein the load of the server comprises at least one processor, or the load of the server comprises at least one processor and one node controller, all processors and the node controllers of the load are connected to the clock switching device corresponding to the load, and all node controllers of all servers of the system are connected to each other.