CN110110472A - The power consumption optimization method of Clock Tree - Google Patents

Abstract

The invention discloses a method for optimizing power consumption of a clock tree. The method for optimizing power consumption of a clock tree is used after the layout and wiring of the clock tree is completed. The method for optimizing power consumption includes: reading in the power of the clock tree in step S1 Power consumption report, looking for the interconnection line whose node turnover rate exceeds the turnover rate threshold and the switch power consumption exceeds the power consumption threshold; in step S2, the distance between the components on the interconnection line found is shortened; Perform static timing analysis in step S3, and perform timing repair if there is a timing violation; go to step S1 after performing power consumption simulation in step S4, until the flipping rate of all the nodes traversed exceeds the flipping rate threshold and the switch Interconnects that consume more than the stated power consumption threshold. The power consumption optimization method of the clock tree can effectively reduce the waste of power consumption generated by the actually taped chip.

Description

Power Optimization Method for Clock Tree

technical field

The invention relates to the field of chip design, in particular to a power consumption optimization method of a clock tree.

Background technique

With the increasing demand for dynamic low power consumption, reducing the dynamic power consumption of the clock tree network has become the focus and difficulty of digital design front-end engineers and back-end engineers.

Common methods used by digital back-end engineers to optimize power consumption in the layout and routing phase include: using a clock tree with a mixed mode of buffer (buffer) and inverter (inverter); reducing the clock tree level; making full use of EDA (electronic design automation) tools Optimize the layout of clock trees; use saif files (switching activity interchange format files) to optimize dynamic power consumption based on data paths; reduce "clock tree consumption"; improve clock tree efficiency, etc.

The above-mentioned methods for optimizing power consumption in the prior art are all implemented in the layout and wiring stage. The inventors found that the use of EDA tools cannot fully realize the optimal design of power consumption, and the actual chip after tape-out will generate a certain amount of waste in power consumption.

The information disclosed in this Background section is only for enhancing the understanding of the general background of the present invention and should not be taken as an acknowledgment or any form of suggestion that the information constitutes the prior art that is already known to those skilled in the art.

Contents of the invention

The purpose of the present invention is to provide a method for optimizing power consumption of a clock tree, which can effectively reduce the waste of power consumption generated by actually taped-out chips.

In order to achieve the above object, the present invention provides a method for optimizing power consumption of a clock tree. The method for optimizing power consumption of a clock tree is used after the layout and wiring of the clock tree is completed. The method for optimizing power consumption includes: step S1 to step S4 . In step S1, the power consumption report of the clock tree is read, and the interconnection line whose node turnover rate exceeds the turnover rate threshold and the switching power consumption exceeds the power consumption threshold is found, wherein the switching power consumption is the logic gate on the interconnection line The power consumption generated during the switching process; in step S2, the distance between the components on the interconnection line found is shortened; in step S3, a static timing analysis is performed, and if there is a timing violation, a timing analysis is performed. Repair; after performing the power consumption simulation in step S4, go to step S1 until all the interconnection lines whose switching rate of the node exceeds the threshold of switching rate and the power consumption of the switch exceeds the threshold of power consumption are traversed.

In a preferred embodiment, between the step S2 and the step S3, it further includes: reducing the size of the driving unit on the premise of satisfying the design rules and timing rules.

Compared with the prior art, the power consumption optimization method of the clock tree according to the present invention is used to perform another optimization after the layout and wiring of the clock tree is completed, and reduce the switch power consumption of the clock tree without affecting the timing convergence. Check the switching power consumption and flip rate on the interconnection line to select the interconnection line that can optimize the load capacitance, and reduce the dynamic power consumption by shortening the length of the connection line, so that the design that can already be submitted for tape-out can further reduce power consumption. In addition, the power consumption is further reduced by reducing the size of the driving unit.

Description of drawings

FIG. 1 is a step composition of a power consumption optimization method according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of shortening the distance of nodes with high turnover rate and high power consumption according to an embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations thereof such as "includes" or "includes" and the like will be understood to include the stated elements or constituents, and not Other elements or other components are not excluded.

In order to reduce the waste of power consumption generated by the actually taped-out chips, the inventors conducted the following research.

The dynamic power consumption and static power consumption of the chip constitute the total power consumption of the chip,

P _total ＝P _dynamic +P _leakage (1)

Among them, P _leakage is the static power consumption, which refers to the power consumption when the chip is in a static state (that is, there is no signal change inside the chip) after the chip is powered on. In CMOS (Complementary Metal Oxide Semiconductor) circuits, static power dissipation is typically caused by leakage currents.

Dynamic power consumption refers to the power consumption when the chip is in the active state, that is, when the input real signal jumps. It mainly consists of two parts: one is the short-circuit power consumption P _SC generated by the short-circuit current, and the other is the dynamic switching power consumption P _SW caused by the dynamic switching current.

P _dynamic ＝P _SC +P _SW (2)

Switching power consumption is the power consumption generated during the switching process of the logic gate. When the output voltage of the logic unit undergoes logic inversion, the dynamic power consumption generated by the power supply voltage charging and discharging the output load capacitor.

Where α is the probability of the logic gate flipping per unit time, f _CLK is the clock frequency, C _L is the load capacitance of the logic gate, including the output capacitance of the logic gate itself, the interconnection capacitance between the gates and the input capacitance of the lower circuit, and V _dd is voltage.

where k=k _n ＝k _p , V _TH ＝V _TH,n ＝|V _TH,p |, τ=τ _rise ＝τ _fall , respectively represent the dielectric constant of NMOS and PMOS transistors, the threshold voltage of CMOS logic gates, Enter the rising and falling edge times of the waveform.

In EDA tools, power consumption is slightly different, divided into switching power (Switching Power), internal power consumption (Internal Power) and static power consumption (Leakage Power). The internal power consumption corresponds to the short-circuit power consumption of the standard unit itself and the switching power consumption on the internal interconnection line of the unit. You can find the corresponding internal power consumption information under the input conversion time and load capacitance at the corresponding position in the interpolation table.

It can be known from relation (2) that manual optimization of dynamic power consumption can start from two aspects of optimizing short-circuit power consumption P _SC and switching power consumption P _SW . It can be seen from relation (4) that the direct way to optimize the short-circuit power consumption is to reduce the number or size of the driving buffer.

It can be seen from the relation (3) that the optimization of switching power consumption P _SW can be achieved by reducing the operating frequency, reducing the turnover rate, reducing the operating voltage and reducing the load capacitance in four ways.

Based on the above research, the present invention provides a power consumption optimization method of a clock tree, which is used to perform another optimization after the layout and wiring of the clock tree is completed, and reduce the switching power consumption of the clock tree without affecting the timing convergence. Check the switching power consumption and flip rate on the interconnection line to select the interconnection line that can optimize the load capacitance, and reduce the dynamic power consumption by shortening the length of the connection line, so that the design that can already be submitted for tape-out can further reduce power consumption.

As shown in FIG. 1 , in an implementation manner, the method for optimizing power consumption of a clock tree includes steps S1 to S4.

In step S1, read in the power consumption report of the clock tree, and find the interconnection line whose node turnover rate exceeds the turnover rate threshold and the switching power consumption exceeds the power consumption threshold, where the switching power consumption is the logic gate switching process on the interconnection line The power consumption generated in . The flip rate refers to the number of flips of a signal (including clock, data, etc.) per unit time. The toggle rate threshold and the power consumption threshold can be selected according to actual conditions.

In step S2, the distance between the components on the selected interconnection line is shortened. FIG. 2 is a schematic diagram of shortening the distance between high-toggle-rate and high-power-consumption nodes, which includes multiple logic gate switches.

Static timing analysis is performed in step S3, and timing repair is performed if there is a timing violation.

After the power consumption simulation is performed in step S4, go to step S1 until all interconnection lines whose node turnover rate exceeds the threshold value of the switching rate and switch power consumption exceeds the threshold value of power consumption are traversed.

In one embodiment, between the above step S2 and the above step S3, it further includes: reducing the size of the driving unit (cell) on the premise of satisfying the design rules and timing rules, so that the power consumption can be further reduced.

To sum up, the power consumption optimization method of the clock tree adopted in this embodiment reduces the switching power consumption of the clock tree without affecting the timing convergence by manually optimizing the layout of the clock tree after the layout and routing are completed, and manually adjusts the corresponding power consumption of the clock tree. It is to reduce the load capacitance on the interconnection line. Since the operation of shortening the connection line is only performed, the possibility of timing violations is generally small, and it is relatively easier to repair. After the connection line is shortened, due to the load capacitance on the line At this time, reducing the size of the drive unit will further reduce power consumption. In addition, the process of this embodiment is simple and easy to implement, without dependence on specific EDA tool brands, and can be widely used in various designs.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowcharts and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling others skilled in the art to make and use various exemplary embodiments of the invention, as well as various Choose and change. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (2)

1. A power consumption optimization method of a clock tree, characterized in that, the power consumption optimization method of the clock tree is used after the clock tree layout and wiring is completed, and the power consumption optimization method comprises: Step S1, read in the power consumption report of the clock tree, and find the interconnection line whose node turnover rate exceeds the turnover rate threshold and the switch power consumption exceeds the power consumption threshold, wherein the switch power consumption is the logic gate switch on the interconnection line Power consumption generated during the process; Step S2, shortening the distance between the found components on the interconnection line; Step S3, performing static timing analysis, and performing timing repair if there is a timing violation; and Step S4, after performing the power consumption simulation, go to step S1, until all the interconnection lines whose switching rate of the node exceeds the threshold of switching rate and the power consumption of the switch exceeds the threshold of power consumption are traversed. 2. The power consumption optimization method of clock tree as claimed in claim 1, is characterized in that, also comprises between described step S2 and described step S3: On the premise of satisfying design rules and timing rules, the size of the driving unit is reduced.