CN110113048A - Clock calibration circuit and clock correcting method based on phaselocked loop - Google Patents
Clock calibration circuit and clock correcting method based on phaselocked loop Download PDFInfo
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- CN110113048A CN110113048A CN201910411571.7A CN201910411571A CN110113048A CN 110113048 A CN110113048 A CN 110113048A CN 201910411571 A CN201910411571 A CN 201910411571A CN 110113048 A CN110113048 A CN 110113048A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The present invention provides a kind of clock calibration circuits based on phaselocked loop, including clock generating unit, clock modulation unit, clock feedback unit, clock processing unit and clock division unit.The clock calibration circuit of the invention increases the clock modulation unit, the clock modulation unit is modulated processing to frequency dividing ratio before the modulation according to the feedback clock frequency, frequency dividing ratio after being modulated, to increase reference clock frequency and flexibility, conversion processing, filtration treatment and oscillation treatment are carried out to the reference clock frequency and the feedback clock frequency by the clock processing unit simultaneously, to improve the accuracy and transmission quality of clock frequency, while lowering the interaction time between clock to reduce power consumption.The present invention also provides the clock correcting methods based on the clock calibration circuit.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to clock calibration circuit and clock alignment based on phaselocked loop
Method.
Background technique
Narrowband Internet of Things is the wide area network technical standard based on Cellular Networks, be applied to system on chip, formation it is narrow
Band Internet of Things chip can be realized the long function of low in energy consumption and stand-by time, to improve the service life of battery.Narrowband Internet of Things
During carrying out information exchange between chip, narrowband Internet of Things chip completes primary reception and transmitting information, enters suspend mode
State, so the information exchange time between narrowband Internet of Things chip is reduced for the function of realization low-power consumption and stand-by time length
It is particularly important.The information exchange time between narrowband Internet of Things chip is determined by chip clock, while narrowband Internet of Things core
Chip clock between piece accomplishes Frequency Synchronization, it is ensured that information transmission quality.
Application publication number is that the Chinese invention patent application of CN100508397C discloses a kind of clock based on phaselocked loop
Generating device, including crystal oscillator, the first phaselocked loop, digital dock frequency divider and clock frequency processing unit, crystal vibration
The clock signal for swinging device output is input to clock frequency processing unit through the first phaselocked loop, and clock frequency processing unit is according to needed for
Clock frequency adjusts the frequency range of the clock signal of the first phaselocked loop output, then by digital dock frequency divider to first lock
The output signal of phase ring and clock frequency processing unit is divided, and the clock of required frequency is obtained.Above-mentioned application described device
Although there is biggish clock frequency transmission range, the precision and transmission quality of clock frequency be not high.
Therefore, it is necessary to provide a kind of clock calibration circuit to avoid the above-mentioned problems in the prior art.
Summary of the invention
The purpose of the present invention is to provide a kind of clock calibration circuit and clock correcting method based on phaselocked loop, avoids
The problem of precision of clock frequency is low in the prior art and poor transmission, while the interaction time between clock is reduced to reduce
Power consumption.
To achieve the above object, clock calibration circuit of the present invention include clock generating unit, clock modulation unit,
Clock feedback unit, clock processing unit and clock division unit, the clock generating unit is for generating reference clock frequency；
The clock modulation unit is used to be modulated processing to frequency dividing ratio before modulating according to initial clock frequency, is adjusted
Frequency dividing ratio after system, and frequency dividing ratio before the modulation is updated to frequency dividing ratio after the modulation；
The clock feedback unit is used to carry out at multimode initial oscillation clock frequency according to frequency dividing ratio after the modulation
Reason, obtains the feedback clock frequency, and the initial clock frequency is updated to the feedback clock frequency；
The clock processing unit be used to carry out the reference clock frequency and the feedback clock frequency conversion processing,
Filtration treatment and oscillation treatment are to obtain running clock frequency, and when the initial concussion clock frequency is updated to the concussion
Clock frequency；
The clock division unit is used to carry out scaling down processing to the running clock frequency, obtains frequency-dividing clock frequency.
The beneficial effect of the clock calibration circuit of the invention is: firstly, the clock calibration circuit increases institute
Clock modulation unit is stated, the clock modulation unit is modulated frequency dividing ratio before the modulation according to the feedback clock frequency
Processing, frequency dividing ratio after being modulated, to increase reference clock frequency and flexibility；Secondly, passing through the clock processing unit pair
The reference clock frequency and the feedback clock frequency carry out conversion processing, filtration treatment and oscillation treatment, to improve clock
The accuracy and transmission quality of frequency, while lowering the interaction time between clock to reduce power consumption.
Further, frequency dividing ratio is 8-128 after the modulation, and frequency dividing ratio is integer after the modulation.
Further, the clock processing unit includes conversion module, filtering module and oscillation module, the conversion module
For calculating the phase difference of the reference clock frequency and the feedback clock frequency, the phase difference is carried out at the conversion
Reason forms voltage signal, and the filtering module is used to carry out the filtration treatment to the voltage signal to form control voltage,
The oscillation module is used to carry out the oscillation treatment to the control voltage to form the running clock frequency.It is beneficial to effect
Fruit is: by the way that the conversion module, the filtering module and the oscillation module is arranged, can be improved the stabilization of clock frequency
Property high pass filter carried out to the phase noise of generation simultaneously make an uproar.
Further, the conversion module is phase discriminator, and the filtering module is filter, and the oscillation module is oscillation
Device, the phase discriminator, the filter and the oscillator are sequentially connected in series.
Further, the clock feedback unit is multi-modulus frequency divider, the first input end of the multi-modulus frequency divider and institute
The output end for stating oscillator is connected, and the output end of the multi-modulus frequency divider is connected with the first input end of the phase discriminator.
Further, the clock modulation unit is modulator, the input terminal of the modulator and the multi-modulus frequency divider
Output end be connected, the output end of the modulator is connected with the second input terminal of the multi-modulus frequency divider.
Further, the clock generating unit is ring oscillator, the output end of the ring oscillator and the mirror
Second input terminal of phase device is connected.
Further, the frequency unit is high-speed frequency divider, the input terminal of the high-speed frequency divider and the oscillator
Output end be connected.
The present invention also provides the clock correcting method for using the clock calibration circuit, the clock correcting method packet
It includes:
S1: reference clock frequency is generated by the clock generating unit；
S2: the clock modulation unit is modulated processing to frequency dividing ratio before modulating according to the initial clock frequency, obtains
Frequency dividing ratio after to modulation, and frequency dividing ratio before the modulation is updated to frequency dividing ratio after the modulation；
S3: the clock feedback unit carries out at multimode initial oscillation clock frequency according to frequency dividing ratio after the modulation
Reason, obtains the feedback clock frequency, and the initial clock frequency is updated to the feedback clock frequency；
S4: the reference clock frequency and the feedback clock frequency are carried out at conversion by the clock processing unit
Reason, filtration treatment and oscillation treatment, obtain the running clock frequency, and described in the initial concussion clock frequency is updated to
Shake clock frequency；
S5: scaling down processing is carried out to the running clock frequency by the clock division unit, obtains frequency-dividing clock frequency
Rate.
The beneficial effect of clock correcting method of the present invention is: according to the feedback clock frequency to the modulation before
Frequency dividing ratio carries out the modulation treatment, and frequency dividing ratio can increase reference clock frequency and flexibility after the obtained modulation, together
When by carrying out the conversion processing, the filtration treatment and described to the reference clock frequency and the feedback clock frequency
Oscillation treatment can be improved the accuracy of the clock frequency and the transmission quality of clock, while lower the interaction between clock
Time is to reduce the power consumption of clock.
Detailed description of the invention
Fig. 1 is the structural block diagram of clock calibration circuit of the invention；
Fig. 2 is the flow chart of clock correcting method of the invention.
Fig. 3 is the structural block diagram of clock calibration circuit in particular embodiments of the invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing of the invention, to this hair
Technical solution in bright embodiment is clearly and completely described, it is clear that described embodiment is that a part of the invention is real
Example is applied, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creation
Property labour under the premise of every other embodiment obtained, shall fall within the protection scope of the present invention.Unless otherwise defined, make herein
Technical term or scientific term should be persons with general skills in the field understood it is usual
Meaning.The similar word such as " comprising " used herein, which means to occur element or object before the word, to be covered and appears in this
The element of word presented hereinafter perhaps object and its equivalent and be not excluded for other elements or object.
In view of the problems of the existing technology, the embodiment provides a kind of, and the clock alignment based on phaselocked loop is electric
Road.
Fig. 1 is the structural block diagram of the clock calibration circuit of some embodiments of the invention.With reference to Fig. 1, clock calibration circuit tool
There are clock generating unit 11, clock modulation unit 12, clock feedback unit 14, clock processing unit 13 and clock division unit
15, the clock generating unit 11 is used for for generating reference clock frequency, the clock modulation unit 12 according to initial clock
Frequency is modulated processing to frequency dividing ratio before modulating, frequency dividing ratio after being modulated, and frequency dividing ratio before the modulation is updated to institute
State modulation after frequency dividing ratio, the clock feedback unit 14 be used for according to frequency dividing ratio after the modulation to initial oscillation clock frequency into
The processing of row multimode, obtains the feedback clock frequency, and the initial clock frequency is updated to the feedback clock frequency, institute
Clock processing unit 13 is stated for carrying out conversion processing, filtration treatment to the reference clock frequency and the feedback clock frequency
With oscillation treatment to obtain running clock frequency, and the initial concussion clock frequency is updated to the concussion clock frequency,
The clock division unit 15 is used to carry out scaling down processing to the running clock frequency, obtains frequency-dividing clock frequency.
The present invention also provides the clock correcting methods based on the clock calibration circuit, with reference to Fig. 2, the clock alignment
Method includes:
S1: reference clock frequency is generated by the clock generating unit；
S2: the clock modulation unit is modulated processing to frequency dividing ratio before modulating according to the initial clock frequency, obtains
Frequency dividing ratio after to modulation, and frequency dividing ratio before the modulation is updated to frequency dividing ratio after the modulation；
S3: the clock feedback unit carries out at multimode initial oscillation clock frequency according to frequency dividing ratio after the modulation
Reason, obtains the feedback clock frequency, and the initial clock frequency is updated to the feedback clock frequency；
S4: the reference clock frequency and the feedback clock frequency are carried out at conversion by the clock processing unit
Reason, filtration treatment and oscillation treatment, obtain the running clock frequency, and described in the initial concussion clock frequency is updated to
Shake clock frequency；
S5: scaling down processing is carried out to the running clock frequency by the clock division unit, obtains frequency-dividing clock frequency
Rate.
In some embodiments of the present invention, the step S1 is repeated to the step S5, to calibrate to clock.
In some embodiments of the present invention, with reference to Fig. 1, the clock processing unit 13 has conversion module 131, filter module
Block 132 and oscillation module 133, the conversion module 131 is for calculating the reference clock frequency and the feedback clock frequency
Phase difference, the conversion processing is carried out to the phase difference and forms voltage signal, the filtering module 132 is used for the electricity
Pressure signal carries out the filtration treatment to form control voltage, and the oscillation module 132 is used to carry out institute to the control voltage
Oscillation treatment is stated to form the running clock frequency；The specific conversion module 131 is phase discriminator, the filtering module
132 be filter, the oscillation module 133 be oscillator, oscillator described further be voltage controlled oscillator, the phase discriminator,
The filter and the voltage controlled oscillator are sequentially connected in series, the institute of the reference clock frequency and the feedback clock frequency
It states phase difference and the voltage signal output is converted by phase discriminator, form the institute of the voltage controlled oscillator after filter filtering
Control voltage is stated, the running clock frequency of voltage controlled oscillator output is implemented to control.
In some embodiments of the present invention, the clock feedback unit 14 is multi-modulus frequency divider and the clock processing unit
13 is in parallel, and one end of the specially described multi-modulus frequency divider is connected with the phase discriminator, and the other end is connected with the voltage controlled oscillator,
The multi-modulus frequency divider carries out multimode processing to the running clock frequency according to frequency dividing ratio after the modulation, obtains the feedback
Clock frequency.
In some specific embodiments of the present invention, the phase discriminator, the filter, the voltage controlled oscillator and described more
Mould frequency divider forms phase-locked loop structures.
In some embodiments of the present invention, the clock modulation unit 12 is according to the feedback clock frequency to before modulation points
Frequency ratio is modulated processing, frequency dividing ratio after being modulated, and frequency dividing ratio has integer portion before modulation described in some specific implementations
Point and fractional part, after the modulation frequency dividing ratio be integer, be specially not fixed integer.The specific clock modulation unit 12
For modulator, the both ends of the modulator are connected respectively at the both ends of the multi-modulus frequency divider, i.e., and the of the described multi-modulus frequency divider
One input terminal is connected with the output end of the oscillator, the first input of the output end of the multi-modulus frequency divider and the phase discriminator
End is connected.
In some specific embodiments of the present invention, the clock generating unit 11 is ring oscillator, the ring oscillation
The output end of device is connected with the second input terminal of the phase discriminator, and the ring oscillator generates the reference clock frequency, and
It is transferred to the phase discriminator through the reference clock frequency, the phase noise of the reference clock frequency is higher.
In some specific embodiments of the present invention, the clock division unit 15 is high-speed frequency divider, the high speed frequency dividing
The input terminal of device is connected with the output end of the oscillator, and the running clock frequency is divided by the high-speed frequency divider
Processing, obtains frequency-dividing clock frequency, is transferred to digital circuit.
In some specific implementations of the invention, the second input of the output end of the ring oscillator and the phase discriminator
End.The connection relationship of the phase-locked loop structures is that the input terminal of the filter is connected with the output end of the phase discriminator, described
The output end of filter is connected with the input terminal of the voltage controlled oscillator, the output end of the multi-modulus frequency divider and the phase discriminator
First input end be connected, the first input end of the multi-modulus frequency divider is connected with the output end of the voltage controlled oscillator, described
The output end of voltage controlled oscillator is also connected with the input terminal of the high-speed frequency divider.The modulator and the multi-modulus frequency divider are simultaneously
Connection, the output end of the specially described multi-modulus frequency divider is connected with the input terminal of the modulator, the output end of the modulator and
Second input terminal output end of the multi-modulus frequency divider is connected.
In some specific embodiments of the present invention, the ring oscillator generates the M times reference clock frequency, and passes through institute
The M times reference clock frequency is transferred to institute by the second input terminal of the phase discriminator by the output end for stating ring oscillator
State phase discriminator.Frequency dividing ratio calculates to form the by the modulator according to the M-1 times feedback clock frequency before modulating simultaneously
Frequency dividing ratio after M-1 modulation, frequency dividing ratio is divided by the output end of the modulator by the multimode after the M-1 times modulation
Second input terminal of device is transferred to the high mould frequency dividing ratio；It is divided after the M-1 times running clock frequency and the M-1 times modulation
Than forming the M-1 times feedback clock frequency by the multi-modulus frequency divider, the M-1 times feedback clock frequency is by described
The output end of multi-modulus frequency divider is transferred to the second input terminal of the phase discriminator 2 and the input terminal of the modulator respectively.
The phase discriminator receives the M times reference clock frequency and the M-1 times feedback clock frequency, and detects
The M reference clock frequency and the M-1 times feedback clock frequency plot difference signal, are converted to the M times voltage signal
And it is transferred to the filter.
The filter receives the M times voltage signal, and the M times voltage signal is formed M secondary control
The output end of voltage, the filter gives the M times control voltage transmission to the voltage controlled oscillator.
The M times control voltage controls the M times running clock frequency of the voltage controlled oscillator output, and the one M times described
Running clock frequency is transferred to the input terminal of the high-speed frequency divider by the output end of the oscillator and the multimode divides
The first input end of device.
In some specific embodiments of the present invention, when the reference clock frequency is identical as the feedback clock frequency,
The running clock clock frequency is the product of frequency dividing ratio after the feedback clock and the modulation.
In some specific embodiments of the present invention, the bandwidth of the phase-locked loop structures is 300KHz~1MHz.
In some specific embodiments of the present invention, the modulator improves the input clock frequency of the phase-locked loop structures
To 8 to 128 times of reference clock frequency, in the case where the bandwidth of the phase-locked loop structures is constant to the noise of the modulator
It is filtered.
In some specific embodiments of the present invention, the high-speed frequency divider divides the voltage controlled oscillator, by institute
The phase noise for stating modulator integrally pushes.Specifically, the running clock frequency of the high-speed frequency divider input improves 2
Times, the phase noise of the modulator reduces 6dB.The running clock frequency for improving the voltage controlled oscillator simultaneously, in the lock
The running clock frequency of phaselocked loop output is divided again except phase ring structure.Frequency dividing ratio has integer and fractional part before modulating,
Frequency dividing ratio is the modulator output as a result, to be not fixed integer after modulation, and the average value of frequency dividing ratio is described after the modulation
Frequency dividing ratio before modulating.
Fig. 3 is the structural block diagram of clock calibration circuit described in particular embodiments of the invention.The clock alignment electricity
Road includes ring oscillator 10, phase discriminator 20, filter 30, oscillator 40, high-speed frequency divider 50, multi-modulus frequency divider 60 and modulation
Device 70, the output end of the ring oscillator 10 are connect with the second input terminal of the phase discriminator 20, the phase discriminator 20 it is defeated
Outlet is connect with the input terminal of the filter 30, and the input terminal of the output end of the filter 30 and the oscillator 40 connects
It connects, the input with the input terminal and the multi-modulus frequency divider 60 of the high-speed frequency divider 50 respectively of the output end of the oscillator 40
End connection, the output end of the multi-modulus frequency divider 60 respectively with the first input end of the phase discriminator 20 and the modulator 70
Input terminal connection, the output end of the modulator 70 are connect with the input terminal of the multi-modulus frequency divider 60.
Although embodiments of the present invention are hereinbefore described in detail, show for those skilled in the art
And be clear to, these embodiments can be carry out various modifications and be changed.However, it is understood that this modifications and variations are all
Belong within scope and spirit of the present invention described in the claims.Moreover, the present invention described herein can have others
Embodiment, and can be practiced or carried out in several ways.
Claims (9)
1. a kind of clock calibration circuit based on phaselocked loop, which is characterized in that including clock generating unit, clock modulation unit,
Clock feedback unit, clock processing unit and clock division unit；
The clock generating unit is for generating reference clock frequency；
The clock modulation unit is used to be modulated processing to frequency dividing ratio before modulating according to initial clock frequency, after obtaining modulation
Frequency dividing ratio, and frequency dividing ratio before the modulation is updated to frequency dividing ratio after the modulation；
The clock feedback unit is used to carry out multimode processing to initial oscillation clock frequency according to frequency dividing ratio after the modulation, obtains
The feedback clock frequency is updated to the feedback clock frequency, and by the initial clock frequency；
The clock processing unit is used to carry out conversion processing, filtering to the reference clock frequency and the feedback clock frequency
The initial concussion clock frequency is updated to the concussion clock frequency to obtain running clock frequency by processing and oscillation treatment
Rate；
The clock division unit is used to carry out scaling down processing to the running clock frequency, obtains frequency-dividing clock frequency.
2. clock calibration circuit according to claim 1, which is characterized in that frequency dividing ratio is 8-128, and institute after the modulation
Frequency dividing ratio is integer after stating modulation.
3. clock calibration circuit according to claim 1, which is characterized in that the clock processing unit includes conversion mould
Block, filtering module and oscillation module, the conversion module is for calculating the reference clock frequency and the feedback clock frequency
Phase difference, the conversion processing is carried out to the phase difference and forms voltage signal, the filtering module is used for the voltage
Signal carries out the filtration treatment to form control voltage, and the oscillation module is used to carry out the oscillation to the control voltage
Processing is to form the running clock frequency.
4. clock calibration circuit according to claim 3, which is characterized in that the conversion module is phase discriminator, the mistake
Filter module is filter, and the oscillation module is oscillator, and the phase discriminator, the filter and the oscillator are sequentially connected in series
Connection.
5. clock calibration circuit according to claim 4, which is characterized in that the clock feedback unit is multimode frequency dividing
Device, the first input end of the multi-modulus frequency divider are connected with the output end of the oscillator, the output end of the multi-modulus frequency divider
It is connected with the first input end of the phase discriminator.
6. clock calibration circuit according to claim 5, which is characterized in that the clock modulation unit is modulator, institute
The input terminal for stating modulator is connected with the output end of the multi-modulus frequency divider, and the output end of the modulator and the multimode divide
Second input terminal of device is connected.
7. clock calibration circuit according to claim 4, which is characterized in that the clock generating unit is ring oscillation
Device, the output end of the ring oscillator are connected with the second input terminal of the phase discriminator.
8. clock calibration circuit according to claim 4, which is characterized in that the frequency unit is high-speed frequency divider, institute
The input terminal for stating high-speed frequency divider is connected with the output end of the oscillator.
9. it is a kind of using the clock correcting method realized such as clock calibration circuit of any of claims 1-8, it is special
Sign is, comprising:
S1: reference clock frequency is generated by the clock generating unit；
S2: the clock modulation unit is modulated processing to frequency dividing ratio before modulating according to the initial clock frequency, is adjusted
Frequency dividing ratio after system, and frequency dividing ratio before the modulation is updated to frequency dividing ratio after the modulation；
S3: the clock feedback unit carries out multimode processing to initial oscillation clock frequency according to frequency dividing ratio after the modulation, obtains
The feedback clock frequency is updated to the feedback clock frequency, and by the initial clock frequency；
S4: by the clock processing unit to the reference clock frequency and the feedback clock frequency carry out conversion processing,
Filtration treatment and oscillation treatment obtain the running clock frequency, and the initial concussion clock frequency are updated to the shake
Swing clock frequency；
S5: scaling down processing is carried out to the running clock frequency by the clock division unit, obtains frequency-dividing clock frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910411571.7A CN110113048A (en) | 2019-05-17 | 2019-05-17 | Clock calibration circuit and clock correcting method based on phaselocked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910411571.7A CN110113048A (en) | 2019-05-17 | 2019-05-17 | Clock calibration circuit and clock correcting method based on phaselocked loop |
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| CN110113048A true CN110113048A (en) | 2019-08-09 |
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ID=67490827
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910411571.7A Pending CN110113048A (en) | 2019-05-17 | 2019-05-17 | Clock calibration circuit and clock correcting method based on phaselocked loop |
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| CN1784831A (en) * | 2003-05-02 | 2006-06-07 | 硅谷实验室公司 | Method and apparatus for a low jitter dual-loop fractional N-type synthesizer |
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Application publication date: 20190809 |
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