CN110120746B - Multiphase parallel DCDC circuit and chip structure thereof - Google Patents
Multiphase parallel DCDC circuit and chip structure thereof Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/084—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
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- H10D89/10—Integrated device layouts
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
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Abstract
Description
技术领域Technical field
本申请涉及电路领域，尤其涉及一种多相并联DCDC电路及其芯片结构。The present application relates to the field of circuits, and in particular to a multi-phase parallel DCDC circuit and its chip structure.
背景技术Background technique
随着消费类电子产品的快速发展，对电子产品中电源管理集成电路(PowerManagement Integrated Circuit，PMIC)之中的集成电压调制器(Integraded VoltageRegulator，IVR)的需求和性能要求也越来越高。对IVR的输出带载能力也提出了更高的要求，主流趋势是通过多相并联DCDC电路方式实现带载能力的提升，同时，要求IVR对输出负载的瞬态跳变响应越快越好，常用的方法是提高IVR的开关频率或者增加环路带宽。With the rapid development of consumer electronic products, the demand and performance requirements for integrated voltage modulators (Integraded Voltage Regulator, IVR) in power management integrated circuits (PowerManagement Integrated Circuit, PMIC) in electronic products are also getting higher and higher. Higher requirements are also put forward for the output load capacity of the IVR. The mainstream trend is to improve the load capacity through multi-phase parallel DCDC circuits. At the same time, the IVR is required to respond as quickly as possible to the transient jump of the output load. Commonly used methods are to increase the switching frequency of the IVR or increase the loop bandwidth.
对于要求IVR的输出带载能力到达几十安培至几百安培的场景时，就需要并联的DCDC电路数目达到16相、32相或者更多相。如图1所示给出了一个4相并联降压式变换BUCK型的DCDC电路的原理框图，将一个误差放大器EA(ErrorAmplifier)的输出电压VEAOUT接到四个比较器COMP(Comparator)的负向端，各COMP的正向端分别接入预设的三角波信号VSAW，从而分别产生具有预定占空比的方波电压信号，通过由缓冲器BUF(Buffer)、两个三极管、输出电感L1、L2、L3及L4和输出电容C0组成的功率级电路，得到输出信号V0。以16相的并联BUCK为例，16相并联的BUCK理论上和4相并联BUCK一样，都是共用EA的输出。For scenarios that require the output load capacity of the IVR to reach tens to hundreds of amps, the number of parallel DCDC circuits needs to reach 16 phases, 32 phases or more. As shown in Figure 1, the principle block diagram of a 4-phase parallel buck conversion BUCK type DCDC circuit is given. The output voltage VEAOUT of an error amplifier EA (ErrorAmplifier) is connected to the negative terminals of four comparators COMP (Comparator). end, the forward end of each COMP is connected to the preset triangular wave signal VSAW, thereby generating a square wave voltage signal with a predetermined duty cycle, which is passed through the buffer BUF (Buffer), two transistors, and output inductors L1 and L2 , L3 and L4 and the output capacitor C0 form a power stage circuit to obtain the output signal V0. Take the 16-phase parallel BUCK as an example. The 16-phase parallel BUCK is theoretically the same as the 4-phase parallel BUCK, sharing the output of the EA.
在实际设计(layout)电路平面图(floorplan)时，一种方案是把EA的layout位置放在裸片(die)的正中心位置，而COMP为了减小到功率级电路的延迟，都是尽量摆放的靠近功率级电路，如图2所示，给出了用一个EA拓展到16相的layout floorplan，其中2相功率级电路为一组，一相功率级电路与一个COMP连接，并且COMP靠近对应的功率级电路。另一种方案如图3所示，把EA的layout位置放在die的正中心位置，16个COMP分别放置在EA的四周，而COMP通过长的走线接入到对应的一相功率级电路。When actually designing the circuit floor plan (layout), one solution is to place the layout position of EA at the very center of the die. In order to reduce the delay to the power stage circuit, COMP places it as far as possible. placed close to the power stage circuit, as shown in Figure 2, which shows a layout floorplan expanded to 16 phases using an EA, in which 2-phase power stage circuits are a group, one-phase power stage circuit is connected to a COMP, and COMP is close to Corresponding power stage circuit. Another solution is shown in Figure 3. Place the layout of the EA in the center of the die, and place 16 COMPs around the EA. The COMPs are connected to the corresponding one-phase power stage circuit through long traces. .
图2的方案中，按照一个4mm*4mm的die大小，意味着VEAOUT的走线需要走至少8mm长，对于EA的输出，layout走线越长，其上的寄生电容和电阻也就是越大，这样带来的寄生极点也就越低频，对于高环路带宽的设计是有很大的影响的，最终导致环路的瞬态响应变差。特别是并联的相位数量越大时，die的面积越大，EA的走线长度和寄生都会增加。图3的方案中，按照一个4mm*4mm的die大小，意味着每一个COMP的输出走线需要走至少2mm长，对于COMP的输出，layout走线越长，其上的寄生电容和电阻也就是越大，这样带来的寄生极点也就越低频，这样对于环路的延迟有很大的影响的，导致瞬态响应时过冲或过跌都增大，最终导致环路的瞬态响应变差。In the solution in Figure 2, according to a die size of 4mm*4mm, it means that the trace of VEAOUT needs to be at least 8mm long. For the output of EA, the longer the layout trace, the greater the parasitic capacitance and resistance on it. The parasitic poles brought about in this way are lower-frequency, which has a great impact on the design of high loop bandwidth, and ultimately leads to a deterioration of the transient response of the loop. Especially when the number of parallel phases is larger, the die area is larger, and the EA trace length and parasitics will increase. In the scheme of Figure 3, according to a die size of 4mm*4mm, it means that the output trace of each COMP needs to be at least 2mm long. For the output of COMP, the longer the layout trace, the parasitic capacitance and resistance on it are The larger the value is, the lower the frequency of the parasitic poles will be, which will have a great impact on the loop delay, causing the overshoot or overshoot to increase during the transient response, and ultimately causing the transient response of the loop to change. Difference.
发明内容Contents of the invention
本申请提供了一种多相并联DCDC电路及其芯片结构，用于降低环路运放EA单元和COMP的输出寄生，从而提高环路带宽，加快瞬态响应。This application provides a multi-phase parallel DCDC circuit and its chip structure, which are used to reduce the output parasitics of the loop operational amplifier EA unit and COMP, thereby increasing the loop bandwidth and accelerating the transient response.
本申请第一方面提供一种多相并联DCDC电路，包括：The first aspect of this application provides a multi-phase parallel DCDC circuit, including:
环路运放EA单元、N个输出级电路单元及M个驱动单元，其中，一个驱动单元对应至少一个输出级电路单元，输出级电路单元包括COMP及功率级电路，N为大于等于2的整数，M为小于等于N的整数；Loop operational amplifier EA unit, N output stage circuit units and M drive units. One drive unit corresponds to at least one output stage circuit unit. The output stage circuit unit includes COMP and power stage circuits. N is an integer greater than or equal to 2. , M is an integer less than or equal to N;
所述环路运放EA单元的输出端与驱动单元的输入端连接；The output end of the loop operational amplifier EA unit is connected to the input end of the drive unit;
所述驱动单元的输出端与对应的输出级电路单元中COMP的输入端连接，所述COMP的输出端与处于同一个输出级电路单元中的功率级电路的输入端连接；The output end of the drive unit is connected to the input end of COMP in the corresponding output stage circuit unit, and the output end of COMP is connected to the input end of the power stage circuit in the same output stage circuit unit;
所述环路运放EA的输入端与所有功率级电路的输出端连接。The input terminal of the loop operational amplifier EA is connected to the output terminals of all power stage circuits.
在多相并联DCDC电路中，具有环路运放EA单元、N个输出级电路单元及M个驱动单元，其中，一个驱动单元对应至少一个输出级电路单元，输出级电路单元包括COMP及功率级电路，N为大于等于2的整数，M为小于等于N的整数，表示一个驱动单元可以驱动一个或者多个COMP，多相的具体数量由N的数值决定，由于环路运放EA单元的输出端与驱动单元的输入端连接，驱动单元的输出端与对应的输出级电路单元中COMP的输入端连接，那么环路运放EA单元的输出电压是经过驱动单元之后，再通过驱动单元的输出电压驱动COMP的，环路运放EA的输入端与所有功率级电路的输出端连接，形成环路结构的电路。与现有技术相比，由于环路运放EA单元的输出端不是直接与所有的COMP的输入端连接，而是通过驱动单元，那么在多相并联DCDC电路的芯片中环路运放EA单元的输出走线的长度必然减少，环路运放EA单元的输出走线的寄生电容和寄生电阻减小，而由于驱动单元的存在，COMP无需考虑靠近环路运放EA单元，可以将COMP靠近功率级电路，减少COMP的输出走线的寄生电容和寄生电阻，由于寄生电容和寄生电阻越大，带来的寄生极点也就越低频，对于高环路带宽的设计是有很大的影响的，会导致环路的瞬态响应变差，那么本申请减少了环路运放EA单元和COMP的输出寄生电容和寄生电阻，可以提高环路带宽，加快瞬态响应。In the multi-phase parallel DCDC circuit, there are loop operational amplifier EA units, N output stage circuit units and M drive units. Among them, one drive unit corresponds to at least one output stage circuit unit, and the output stage circuit unit includes COMP and power stage. Circuit, N is an integer greater than or equal to 2, M is an integer less than or equal to N, indicating that one driving unit can drive one or more COMPs. The specific number of polyphases is determined by the value of N. Since the output of the loop operational amplifier EA unit The terminal is connected to the input terminal of the driving unit, and the output terminal of the driving unit is connected to the input terminal of COMP in the corresponding output stage circuit unit. Then the output voltage of the loop operational amplifier EA unit passes through the driving unit and then passes through the output of the driving unit. The voltage drives COMP, and the input terminal of the loop operational amplifier EA is connected to the output terminals of all power stage circuits to form a loop structure circuit. Compared with the existing technology, since the output terminal of the loop operational amplifier EA unit is not directly connected to the input terminals of all COMPs, but through the driving unit, the loop operational amplifier EA unit in the chip of the multi-phase parallel DCDC circuit The length of the output trace will inevitably be reduced, and the parasitic capacitance and parasitic resistance of the output trace of the loop op amp EA unit will be reduced. Due to the existence of the driver unit, COMP does not need to be considered close to the loop op amp EA unit, and COMP can be placed close to the power level circuit to reduce the parasitic capacitance and parasitic resistance of the COMP output trace. Because the larger the parasitic capacitance and parasitic resistance, the lower the frequency of the parasitic poles will be, which has a great impact on the design of high loop bandwidth. It will cause the transient response of the loop to deteriorate, so this application reduces the output parasitic capacitance and parasitic resistance of the loop operational amplifier EA unit and COMP, which can increase the loop bandwidth and speed up the transient response.
结合本申请第一方面，本申请第一方面第一实施方式中，Combined with the first aspect of this application, in the first implementation mode of the first aspect of this application,
所述驱动单元的负向端与所述驱动单元的输出端连接，所述驱动单元的正向端与所述环路运放EA单元的输出端连接。The negative terminal of the driving unit is connected to the output terminal of the driving unit, and the positive terminal of the driving unit is connected to the output terminal of the loop operational amplifier EA unit.
驱动单元可以为EA，将的负向端和输出端连接，正向端与环路运放EA单元的输出端连接，那么EA的负向端和输出端之间形成一个负反馈，可以对正向端所接收到的运放EA单元的输出的输出电压起到驱动作用，即保证驱动单元输出端输出至COMP的输出电压与运放EA单元的输出电压一致。The driving unit can be EA. Connect the negative terminal to the output terminal, and connect the positive terminal to the output terminal of the loop operational amplifier EA unit. Then a negative feedback is formed between the negative terminal and the output terminal of the EA, which can correct the positive The output voltage of the operational amplifier EA unit received by the forward terminal plays a driving role, that is, ensuring that the output voltage output to COMP from the output terminal of the driving unit is consistent with the output voltage of the operational amplifier EA unit.
结合本申请第一方面第一实施方式，本申请第一方面第二实施方式中，Combined with the first implementation mode of the first aspect of the application, in the second implementation mode of the first aspect of the application,
所述功率级电路包括两个BUF、下功率管、上功率管、输出电感及输出电容；The power stage circuit includes two BUFs, a lower power tube, an upper power tube, an output inductor and an output capacitor;
所述COMP的负向端与所述驱动单元的输出端连接，所述COMP的正向端与三角波信号端连接，使得所述COMP输出端输出具有预定占空比的方波电压信号；The negative terminal of the COMP is connected to the output terminal of the driving unit, and the positive terminal of the COMP is connected to the triangular wave signal terminal, so that the COMP output terminal outputs a square wave voltage signal with a predetermined duty cycle;
所述两个BUF的输入端分别与所述COMP的输出端连接，所述两个BUF的输出端分别与所述下功率管的栅极和所述上功率管的栅极连接，所述上功率管的源极与供电端连接，所述下功率管的源极与接地端连接，所述下功率管的漏极及所述上功率管的漏极与所述输出电感的一端连接，所述输出电感的另一端与所述输出电容的非接地端连接，所述输出电容的另一端接地。The input terminals of the two BUFs are respectively connected to the output terminals of the COMP, and the output terminals of the two BUFs are respectively connected to the gates of the lower power tube and the gate of the upper power tube. The source of the power tube is connected to the power supply terminal, the source of the lower power tube is connected to the ground terminal, and the drain of the lower power tube and the drain of the upper power tube are connected to one end of the output inductor, so The other end of the output inductor is connected to the non-grounded end of the output capacitor, and the other end of the output capacitor is connected to ground.
输出级电路单元可以以BUCK电路为例，根据已知的BUCK电路的电路结构，输出级电路单元中功率级电路包括两个BUF、下功率管、上功率管、输出电感及输出电容，COMP的负向端与驱动单元的输出端连接，COMP的正向端与三角波信号端连接，三角波信号端提供的三角波形式的电压波形，目的是为了使得COMP能够根据三角波信号与驱动单元输出的输出信号，在COMP输出端输出具有预定占空比的方波电压信号，占空比的大小由预先设置的三角波信号和驱动单元输出的输出信号共同所决定，两个BUF的输入端分别与COMP的输出端连接，BUF所起到的作用是驱动，两个BUF的输出端分别与下功率管的栅极和上功率管的栅极连接，上功率管的源极与供电端连接，下功率管的源极与接地端连接，下功率管的漏极及上功率管的漏极与输出电感的一端连接，输出电感的另一端与输出电容的非接地端连接，输出电容的另一端接地，并通过输出电感和输出电容将多路功率级电路输出的信号合成一路信号，从而向负载供电。The output stage circuit unit can take the BUCK circuit as an example. According to the known circuit structure of the BUCK circuit, the power stage circuit in the output stage circuit unit includes two BUFs, a lower power tube, an upper power tube, an output inductor and an output capacitor. The COMP The negative end is connected to the output end of the drive unit, and the positive end of COMP is connected to the triangle wave signal end. The triangle wave signal end provides a voltage waveform in the form of a triangle wave, in order to enable COMP to output the output signal of the drive unit based on the triangle wave signal. A square wave voltage signal with a predetermined duty cycle is output at the COMP output terminal. The size of the duty cycle is determined by the preset triangle wave signal and the output signal output by the drive unit. The input terminals of the two BUFs are connected to the output terminals of COMP respectively. connection, the role of BUF is to drive. The output terminals of the two BUFs are connected to the gates of the lower power tube and the gate of the upper power tube respectively. The source of the upper power tube is connected to the power supply terminal. The source of the lower power tube The drain of the lower power tube and the drain of the upper power tube are connected to one end of the output inductor. The other end of the output inductor is connected to the non-grounded end of the output capacitor. The other end of the output capacitor is grounded and passed through the output The inductor and output capacitor combine the signals output from multiple power stage circuits into one signal to provide power to the load.
结合本申请第一方面第二实施方式，本申请第一方面第三实施方式中，Combined with the second implementation mode of the first aspect of the application, in the third implementation mode of the first aspect of the application,
所述环路运放EA单元包括：反馈补偿网络及环路运放EA；The loop operational amplifier EA unit includes: a feedback compensation network and a loop operational amplifier EA;
所述反馈补偿网络的第一端口与所述环路运放EA的负向端连接；The first port of the feedback compensation network is connected to the negative terminal of the loop operational amplifier EA;
所述反馈补偿网络的第二端口与所述功率级电路的所述输出电容的非接地端连接；The second port of the feedback compensation network is connected to the non-ground end of the output capacitor of the power stage circuit;
所述反馈补偿网络的第三端口与所述环路运放EA的输出端连接；The third port of the feedback compensation network is connected to the output end of the loop operational amplifier EA;
所述环路运放EA的正向端与参考电压端连接。The forward terminal of the loop operational amplifier EA is connected to the reference voltage terminal.
环路运放EA单元由反馈补偿网络及环路运放EA组成，其中反馈补偿网络的第一端口与环路运放EA的负向端连接，反馈补偿网络的第二端口与输出电容的非接地端连接，环路电路的第三端口与环路运放EA的输出端连接，环路运放EA的正向端与参考电压端连接，环路电路通过第二端口接收到所有功率级电路的输出电压合成后的一路信号，通过第一端口接收到环路运放EA的输出电压，第三端口向环路运放EA输入反馈电压，环路运放EA根据负向端的反馈电压和正向端的参考电压，输出差值转换电压。The loop operational amplifier EA unit is composed of a feedback compensation network and a loop operational amplifier EA. The first port of the feedback compensation network is connected to the negative terminal of the loop operational amplifier EA, and the second port of the feedback compensation network is connected to the non-positive terminal of the output capacitor. The ground terminal is connected, the third port of the loop circuit is connected to the output terminal of the loop operational amplifier EA, the forward terminal of the loop operational amplifier EA is connected to the reference voltage terminal, and the loop circuit receives all power stage circuits through the second port The output voltage of the synthesized signal is received through the first port of the output voltage of the loop operational amplifier EA, and the third port inputs the feedback voltage to the loop operational amplifier EA. The loop operational amplifier EA is based on the feedback voltage of the negative terminal and the positive The reference voltage at the terminal, outputs the difference conversion voltage.
结合本申请第一方面第三实施方式，本申请第一方面第四实施方式中，所述反馈补偿网络包括：Combined with the third implementation mode of the first aspect of the application, in the fourth implementation mode of the first aspect of the application, the feedback compensation network includes:
第一电阻与第一电容串联后，与第二电阻并联，所述第一电阻和所述第二电阻的连接点为所述第二端口，所述第二电阻和所述第一电容的连接点为所述第一端口；After the first resistor is connected in series with the first capacitor, it is connected in parallel with the second resistor. The connection point between the first resistor and the second resistor is the second port. The connection point between the second resistor and the first capacitor is The point is the first port;
第三电阻与第二电容串联后，与第三电容并联，所述第三电阻和所述第三电容的连接点与所述第一端口连接，所述第二电容和所述第三电容的连接点为所述第三端口；After the third resistor is connected in series with the second capacitor, it is connected in parallel with the third capacitor. The connection point between the third resistor and the third capacitor is connected to the first port. The connection point between the second capacitor and the third capacitor is The connection point is the third port;
第四电阻的一端与所述第一端口连接，另一端与接地端连接。One end of the fourth resistor is connected to the first port, and the other end is connected to the ground terminal.
反馈补偿网络中包括第一电阻、第二电阻、第三电阻、第四电阻、第一电容、第二电容和第三电容，第一电阻与第一电容串联后，与第二电阻并联，第一电阻和所述第二电阻的连接点为第二端口，第一电阻和第一电容的连接点为第一端口，第三电阻与第二电容串联后，与第三电容并联，第三电阻和第三电容的连接点与第一端口连接，第二电容和第三电阻的连接点为第三端口，第四电阻的一端与第一端口连接，另一端与接地端连接，通过反馈补偿网络的反馈补偿作用对环路运放EA的输出电压进行调整。The feedback compensation network includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and a third capacitor. After the first resistor is connected in series with the first capacitor, it is connected in parallel with the second resistor. The connection point between a resistor and the second resistor is the second port, the connection point between the first resistor and the first capacitor is the first port, and the third resistor is connected in series with the second capacitor and then connected in parallel with the third capacitor. The connection point with the third capacitor is connected to the first port, the connection point between the second capacitor and the third resistor is the third port, one end of the fourth resistor is connected to the first port, and the other end is connected to the ground terminal, through the feedback compensation network The feedback compensation function adjusts the output voltage of the loop operational amplifier EA.
本申请第二方面提供一种多相并联DCDC电路的芯片结构，包括：The second aspect of this application provides a chip structure of a multi-phase parallel DCDC circuit, including:
设置于芯片die上的环路运放EA单元、N个输出级电路单元及M个驱动单元，其中，一个驱动单元对应至少一个输出级电路单元，输出级电路单元包括COMP及功率级电路，N为大于等于2的整数，M为小于等于N的整数；The loop operational amplifier EA unit, N output stage circuit units and M drive units are arranged on the chip die. Among them, one drive unit corresponds to at least one output stage circuit unit, and the output stage circuit unit includes COMP and power stage circuits, N is an integer greater than or equal to 2, M is an integer less than or equal to N;
所述环路运放EA单元的输出端通过芯片die上的走线与驱动单元的输入端连接；The output end of the loop operational amplifier EA unit is connected to the input end of the drive unit through the wiring on the chip die;
所述驱动单元的输出端通过芯片die上的走线与对应的输出级电路单元中COMP的输入端连接；The output end of the driving unit is connected to the input end of COMP in the corresponding output stage circuit unit through the wiring on the chip die;
所述COMP的输出端通过芯片die上的走线与处于同一个输出级电路单元中的功率级电路的输入端连接。The output terminal of the COMP is connected to the input terminal of the power stage circuit in the same output stage circuit unit through the wiring on the chip die.
在多相并联DCDC电路的芯片结构中，在芯片die上设置有环路运放EA单元、N个输出级电路单元及M个驱动单元，其中，一个驱动单元对应至少一个输出级电路单元，输出级电路单元包括COMP及功率级电路，N为大于等于2的整数，M为小于等于N的整数，表示一个驱动单元可以驱动一个或者多个COMP，多相的具体数量由N的数值决定，环路运放EA单元的输出端通过芯片die上的走线与驱动单元的输入端连接，驱动单元的输出端通过芯片die上的走线与对应的输出级电路单元中COMP的输入端连接，COMP的输出端通过芯片die上的走线与处于同一个输出级电路单元中的功率级电路的输入端连接。环路运放EA单元的输出电压是经过驱动单元之后，再通过驱动单元的输出电压驱动COMP的，与现有技术相比，由于环路运放EA单元的输出端不是直接与所有的COMP的输入端连接，而是通过驱动单元，那么环路运放EA单元的输出走线的长度必然减少，环路运放EA单元的输出走线的寄生电容和寄生电阻减小，而由于驱动单元的存在，COMP无需考虑靠近环路运放EA单元，可以将COMP靠近功率级电路，减少了COMP的输出走线的寄生电容和寄生电阻，由于寄生电容和寄生电阻越大，带来的寄生极点也就越低频，对于高环路带宽的设计是有很大的影响的，会导致环路的瞬态响应变差，那么本申请减少了环路运放EA单元和COMP的输出寄生电容和寄生电阻，可以提高环路带宽，加快瞬态响应。In the chip structure of the multi-phase parallel DCDC circuit, a loop operational amplifier EA unit, N output stage circuit units and M drive units are provided on the chip die. Among them, one drive unit corresponds to at least one output stage circuit unit, and the output The stage circuit unit includes COMP and power stage circuits. N is an integer greater than or equal to 2, and M is an integer less than or equal to N, indicating that one drive unit can drive one or more COMPs. The specific number of polyphases is determined by the value of N. The output end of the operational amplifier EA unit is connected to the input end of the drive unit through the wiring on the chip die. The output end of the driving unit is connected to the input end of COMP in the corresponding output stage circuit unit through the wiring on the chip die. COMP The output end is connected to the input end of the power stage circuit in the same output stage circuit unit through the wiring on the chip die. The output voltage of the loop operational amplifier EA unit drives COMP through the output voltage of the driving unit after passing through the driving unit. Compared with the existing technology, because the output terminal of the loop operational amplifier EA unit is not directly connected to all COMP The input end is connected instead through the drive unit, so the length of the output trace of the loop op amp EA unit will inevitably be reduced, and the parasitic capacitance and parasitic resistance of the output trace of the loop op amp EA unit will be reduced, and due to the There is no need for COMP to be close to the loop op amp EA unit. COMP can be placed close to the power stage circuit, which reduces the parasitic capacitance and parasitic resistance of the COMP's output trace. As the parasitic capacitance and parasitic resistance are larger, the parasitic poles will also be caused. The lower the frequency, the greater the impact on the design of high loop bandwidth, which will cause the transient response of the loop to deteriorate. Therefore, this application reduces the output parasitic capacitance and parasitic resistance of the loop op amp EA unit and COMP. , which can increase the loop bandwidth and speed up the transient response.
结合本申请第二方面，本申请第二方面第一实施方式中，Combined with the second aspect of this application, in the first implementation mode of the second aspect of this application,
所述环路运放EA单元设置于所述芯片die的中间位置，所述M个驱动单元围绕所述环路运放EA单元进行设置，所述功率级电路设置于所述芯片die的边缘位置，与所述功率级电路对应的所述COMP的设置位置靠近所述功率级电路。The loop operational amplifier EA unit is arranged in the middle of the chip die, the M drive units are arranged around the loop operational amplifier EA unit, and the power stage circuit is arranged at the edge of the chip die. , the COMP corresponding to the power stage circuit is located close to the power stage circuit.
在多相并联DCDC电路具体的芯片结构中，为了方便走线的需要，环路运放EA单元一般情况下都是设置于芯片die的中间位置，M个驱动单元围绕环路运放EA单元进行设置，功率级电路设置于芯片die的边缘位置，与功率级电路对应的COMP的设置位置靠近功率级电路。In the specific chip structure of the multi-phase parallel DCDC circuit, in order to facilitate wiring, the loop operational amplifier EA unit is generally set in the middle of the chip die, and M drive units surround the loop operational amplifier EA unit. Setting, the power stage circuit is set at the edge of the chip die, and the COMP corresponding to the power stage circuit is set close to the power stage circuit.
结合本申请第二方面第一实施方式，本申请第二方面第二实施方式中，Combined with the first implementation mode of the second aspect of the application, in the second implementation mode of the second aspect of the application,
所述驱动单元对应的输出级电路单元中的功率级电路集成为一个功率级单元，并设置于所述芯片die的边缘位置。The power stage circuit in the output stage circuit unit corresponding to the driving unit is integrated into a power stage unit and is arranged at the edge of the chip die.
在芯片结构中，为了方便布局和制作，将一个驱动单元对应的输出级电路单元中的所有功率级电路集成为一个功率级单元，一个驱动单元可能对应一个或者多个输出级电路单元，使得输出级电路单元数量多的情况下，走线更加方便。In the chip structure, in order to facilitate layout and production, all power stage circuits in the output stage circuit unit corresponding to a driving unit are integrated into one power stage unit. One driving unit may correspond to one or more output stage circuit units, so that the output When the number of stage circuit units is large, wiring is more convenient.
结合本申请第二方面，本申请第二方面第三实施方式中，Combined with the second aspect of this application, in the third implementation mode of the second aspect of this application,
所述驱动单元为EA，所述驱动单元的负向端与所述驱动单元的输出端连接，所述驱动单元的正向端与所述环路运放EA单元的输出端连接。The driving unit is an EA, the negative end of the driving unit is connected to the output end of the driving unit, and the positive end of the driving unit is connected to the output end of the loop operational amplifier EA unit.
驱动单元在具体实现时可以为EA，将的负向端和输出端连接，正向端与环路运放EA单元的输出端连接，那么EA的负向端和输出端之间形成一个负反馈，可以对正向端所接收到的运放EA单元的输出的输出电压起到驱动作用，即保证驱动单元输出端输出至COMP的输出电压与环路运放EA单元的输出电压一致。In specific implementation, the driving unit can be EA, connect the negative end to the output end, and connect the positive end to the output end of the loop operational amplifier EA unit, then a negative feedback is formed between the negative end and the output end of the EA , can drive the output voltage of the op amp EA unit received by the forward end, that is, ensure that the output voltage output from the output end of the drive unit to COMP is consistent with the output voltage of the loop op amp EA unit.
结合本申请第二方面、第二方面第一实施方式、第二方面第二实施方式或第二方面第三实施方式，本申请第二方面第四实施方式中，Combining the second aspect of the application, the first implementation mode of the second aspect, the second implementation mode of the second aspect or the third implementation mode of the second aspect, in the fourth implementation mode of the second aspect of the application,
所述芯片die为圆片形硅片或者正方形硅片。The chip die is a round silicon wafer or a square silicon wafer.
在多相并联DCDC电路具体的芯片结构中，芯片die一般采用的是圆片形硅片或者正方形硅片。In the specific chip structure of multi-phase parallel DCDC circuits, the chip die generally uses wafer-shaped silicon wafers or square silicon wafers.
附图说明Description of the drawings
为了更清楚地说明本申请实施例技术方案，下面将对实施例和现有技术描述中所需要使用的附图作简单地介绍。In order to explain the technical solutions of the embodiments of the present application more clearly, the drawings needed to be used in the description of the embodiments and the prior art will be briefly introduced below.
图1为一种4相并联BUCK电路的电路结构示意图；Figure 1 is a schematic diagram of the circuit structure of a 4-phase parallel BUCK circuit;
图2为一种16相并联DCDC电路的芯片结构的结构示意图；Figure 2 is a schematic structural diagram of the chip structure of a 16-phase parallel DCDC circuit;
图3为另一种16相并联DCDC电路的芯片结构的结构示意图；Figure 3 is a schematic structural diagram of the chip structure of another 16-phase parallel DCDC circuit;
图4为本申请提供的一种多相并联DCDC电路的芯片结构的结构示意图；Figure 4 is a schematic structural diagram of the chip structure of a multi-phase parallel DCDC circuit provided by this application;
图5为本申请提供的另一种多相并联DCDC电路的芯片结构的结构示意图；Figure 5 is a schematic structural diagram of the chip structure of another multi-phase parallel DCDC circuit provided by this application;
图6为本申请提供的又一种多相并联DCDC电路的芯片结构的结构示意图；Figure 6 is a schematic structural diagram of the chip structure of another multi-phase parallel DCDC circuit provided by this application;
图7为本申请提供的一种多相并联DCDC电路的电路结构示意图；Figure 7 is a schematic circuit structure diagram of a multi-phase parallel DCDC circuit provided by this application;
图8为本申请提供的16相并联DCDC电路的电路结构示意图。Figure 8 is a schematic circuit structure diagram of the 16-phase parallel DCDC circuit provided by this application.
具体实施方式Detailed ways
本申请提供了一种多相并联DCDC电路及其芯片结构，用于降低环路运放EA单元和COMP的输出寄生，从而提高环路带宽，加快瞬态响应。This application provides a multi-phase parallel DCDC circuit and its chip structure, which are used to reduce the output parasitics of the loop operational amplifier EA unit and COMP, thereby increasing the loop bandwidth and accelerating the transient response.
下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述。The technical solution in this application will be clearly and completely described below in conjunction with the accompanying drawings in this application.
请参阅图4，本申请实施例提供一种多相并联DCDC电路的芯片结构，包括：Please refer to Figure 4. This embodiment of the present application provides a chip structure of a multi-phase parallel DCDC circuit, including:
设置于芯片die401上的环路运放EA单元402、N个输出级电路单元403及M个驱动单元404，其中，一个驱动单元404对应至少一个输出级电路单元403，输出级电路单元403包括COMP4031及功率级电路4032，N为大于等于2的整数，M为小于等于N的整数；The loop operational amplifier EA unit 402, N output stage circuit units 403 and M drive units 404 are provided on the chip die401. Among them, one drive unit 404 corresponds to at least one output stage circuit unit 403, and the output stage circuit unit 403 includes COMP4031 and power stage circuit 4032, N is an integer greater than or equal to 2, M is an integer less than or equal to N;
环路运放EA单元402的输出端通过芯片die401上的走线与驱动单元404的输入端连接；The output end of the loop operational amplifier EA unit 402 is connected to the input end of the drive unit 404 through the wiring on the chip die 401;
驱动单元404的输出端通过芯片die401上的走线与对应的输出级电路单元中COMP4031的输入端连接；The output end of the driving unit 404 is connected to the input end of COMP4031 in the corresponding output stage circuit unit through the wiring on the chip die401;
COMP4031的输出端通过芯片die401上的走线与处于同一个输出级电路单元403中的功率级电路4032的输入端连接。The output terminal of COMP4031 is connected to the input terminal of the power stage circuit 4032 in the same output stage circuit unit 403 through the wiring on the chip die401.
本申请实施例中，在图4所示的芯片结构中，环路运放EA单元402与所有的M个驱动单元404连接，而N为大于等于2的整数，M为小于等于N的整数，所以一个驱动单元404必然至少对应一个输出级电路单元403，环路运放EA单元402的输出端通过芯片die401上的走线与驱动单元404的输入端连接，驱动单元404的输出端通过芯片die401上的走线与对应的输出级电路单元403中COMP4031的输入端连接，COMP4031的输出端通过芯片die上402的走线与处于同一个输出级电路单元403中的功率级电路4032的输入端连接。环路运放EA单元402的输出电压是经过驱动单元404之后，再通过驱动单元404的输出电压驱动COMP4031的，与图2所示的芯片结构相比，由于环路运放EA单元402的输出端不是直接与所有的COMP4031的输入端连接，而是通过驱动单元404，那么环路运放EA单元402的输出走线的长度必然减少，那么环路运放EA单元402的输出走线的寄生电容和寄生电阻减小，与图3所示的芯片结构相比，由于驱动单元404的存在，COMP4031无需考虑靠近环路运放EA单元402，可以将COMP4031靠近功率级电路4032，减少了COMP4031的输出走线的寄生电容和寄生电阻，由于寄生电容和寄生电阻越大，带来的寄生极点也就越低频，对于高环路带宽的设计是有很大的影响的，会导致环路的瞬态响应变差，那么本申请减少了环路运放EA单元402和COMP4031的输出寄生电容和寄生电阻，可以提高环路带宽，加快瞬态响应。In the embodiment of the present application, in the chip structure shown in Figure 4, the loop operational amplifier EA unit 402 is connected to all M drive units 404, and N is an integer greater than or equal to 2, M is an integer less than or equal to N, Therefore, a drive unit 404 must correspond to at least one output stage circuit unit 403. The output end of the loop operational amplifier EA unit 402 is connected to the input end of the drive unit 404 through the wiring on the chip die401, and the output end of the drive unit 404 passes through the chip die401. The wiring on the chip is connected to the input end of COMP4031 in the corresponding output stage circuit unit 403. The output end of COMP4031 is connected to the input end of the power stage circuit 4032 in the same output stage circuit unit 403 through the wiring 402 on the chip die. . The output voltage of the loop operational amplifier EA unit 402 drives the COMP4031 through the output voltage of the driving unit 404 after passing through the driving unit 404. Compared with the chip structure shown in Figure 2, due to the output of the loop operational amplifier EA unit 402 terminal is not directly connected to all input terminals of COMP4031, but through the driver unit 404, then the length of the output trace of the loop operational amplifier EA unit 402 will inevitably be reduced, then the parasitic of the output trace of the loop operational amplifier EA unit 402 The capacitance and parasitic resistance are reduced. Compared with the chip structure shown in Figure 3, due to the existence of the driver unit 404, COMP4031 does not need to consider being close to the loop operational amplifier EA unit 402. COMP4031 can be placed close to the power stage circuit 4032, reducing the cost of COMP4031. The parasitic capacitance and parasitic resistance of the output trace, because the larger the parasitic capacitance and parasitic resistance, the lower the frequency of the parasitic poles, which has a great impact on the design of high loop bandwidth, which will lead to the instantaneous loss of the loop. If the state response becomes worse, then this application reduces the output parasitic capacitance and parasitic resistance of the loop operational amplifier EA unit 402 and COMP4031, which can improve the loop bandwidth and speed up the transient response.
可选的，本申请的一些实施例中，Optionally, in some embodiments of this application,
环路运放EA单元402设置于芯片die401的中间位置，M个驱动单元404围绕环路运放EA单元402进行设置，功率级电路4032设置于芯片die401的边缘位置，与功率级电路4032对应的COMP4031的设置位置靠近功率级电路4032。The loop operational amplifier EA unit 402 is arranged in the middle of the chip die 401. M drive units 404 are arranged around the loop operational amplifier EA unit 402. The power stage circuit 4032 is arranged at the edge of the chip die 401, corresponding to the power stage circuit 4032. COMP4031 is located close to the power stage circuit 4032.
本申请实施例中，在多相并联DCDC电路具体的芯片结构中，为了方便走线的需要，环路运放EA单元402一般情况下都是设置于芯片die401的中间位置，M个驱动单元404围绕环路运放EA单元402进行设置，功率级电路4032设置于芯片die401的边缘位置，与功率级电路4032对应的COMP4031的设置位置靠近功率级电路，利用驱动单元404的驱动功能，驱动单元404只需要靠近环路运放EA单元402与其连接即可，那么环路运放EA单元402的输出走线将很短，走线寄生可以减少，而且COMP4031可以靠近功率级电路4032设置，那么COMP4031的输出走线也会很短，进一步的减小了走线寄生，从而更好的提高环路带宽，加快瞬态响应。In the embodiment of the present application, in the specific chip structure of the multi-phase parallel DCDC circuit, in order to facilitate wiring, the loop operational amplifier EA unit 402 is generally arranged in the middle position of the chip die 401, and M drive units 404 Set around the loop operational amplifier EA unit 402, the power stage circuit 4032 is set at the edge of the chip die401. The COMP4031 corresponding to the power stage circuit 4032 is set close to the power stage circuit. Using the driving function of the driving unit 404, the driving unit 404 You only need to connect it close to the loop operational amplifier EA unit 402, then the output trace of the loop operational amplifier EA unit 402 will be very short, trace parasitics can be reduced, and COMP4031 can be set close to the power stage circuit 4032, then COMP4031 The output traces will also be very short, further reducing trace parasitics, thereby better improving loop bandwidth and speeding up transient response.
可选的，如图5所示，本申请的一些实施例中，Optionally, as shown in Figure 5, in some embodiments of this application,
驱动单元404对应的输出级电路单元中的功率级电路4032集成为一个功率级单元501，并设置于芯片die401的边缘位置。The power stage circuit 4032 in the output stage circuit unit corresponding to the driving unit 404 is integrated into a power stage unit 501 and is disposed at the edge of the chip die 401.
本申请实施例中，如图5所示，其中输出级电路单元的数量N为16，而驱动单元404的数量M为4个，以一个驱动单元404对应4个输出级电路单元为例进行说明，那么一个驱动单元404与4个COMP连接，与这4个COMP对应的功率级电路集成的一个功率级单元501，为了方便走线，将功率级单元501设置在芯片die401的外侧边缘位置。另外，也可以如图6所示，将2个功率级电路集成为一个功率级单元601。In the embodiment of the present application, as shown in FIG. 5 , the number N of output stage circuit units is 16, and the number M of drive units 404 is 4. One drive unit 404 corresponds to 4 output stage circuit units as an example for explanation. , then a drive unit 404 is connected to 4 COMPs, and a power stage unit 501 is integrated with the power stage circuits corresponding to these 4 COMPs. In order to facilitate wiring, the power stage unit 501 is set at the outer edge of the chip die 401. In addition, as shown in FIG. 6 , two power stage circuits can also be integrated into one power stage unit 601 .
可选的，本申请的一些实施例中，Optionally, in some embodiments of this application,
驱动单元404为EA，驱动单元404的负向端与驱动单元404的输出端连接，驱动单元404的正向端与环路运放EA单元402的输出端连接。The driving unit 404 is EA, the negative end of the driving unit 404 is connected to the output end of the driving unit 404, and the positive end of the driving unit 404 is connected to the output end of the loop operational amplifier EA unit 402.
本申请实施例中，在具体实现时驱动单元404可以为EA，将的负向端和输出端连接，正向端与环路运放EA单元402的输出端连接，那么EA的负向端和输出端之间形成一个负反馈，可以对正向端所接收到的环路运放EA单元402的输出的输出电压起到驱动作用，即保证驱动单元输出端输出至COMP4031的输出电压与环路运放EA单元402的输出电压一致。In the embodiment of the present application, during specific implementation, the driving unit 404 can be an EA. The negative terminal of EA is connected to the output terminal, and the positive terminal is connected to the output terminal of the loop operational amplifier EA unit 402. Then the negative terminal of EA and A negative feedback is formed between the output terminals, which can drive the output voltage of the loop operational amplifier EA unit 402 received by the positive terminal, that is, to ensure that the output voltage output from the output terminal of the driving unit to COMP4031 is consistent with the loop The output voltages of the operational amplifier EA unit 402 are consistent.
可选的，本申请的一些实施例中，Optionally, in some embodiments of this application,
芯片die401为圆片形硅片或者正方形硅片。Chip die401 is a wafer-shaped silicon wafer or a square silicon wafer.
本申请实施例中，多相并联DCDC电路具体的芯片结构的制作时，一般是采用圆片形硅片或者正方形硅片，假如功率级电路的数量少，则可以采用4*4mm大小的正方形硅片，如果功率级电路的数量增加，则需要适当的增大芯片die的大小。In the embodiment of the present application, when manufacturing the specific chip structure of the multi-phase parallel DCDC circuit, wafer-shaped silicon wafers or square silicon wafers are generally used. If the number of power stage circuits is small, square silicon wafers with a size of 4*4mm can be used. If the number of power stage circuits increases, the size of the chip die needs to be appropriately increased.
以上实施例中介绍本申请的多相并联DCDC电路的芯片结构，下面通过实施例对芯片结构中的多相并联DCDC电路进行详细说明。The above embodiments introduce the chip structure of the multi-phase parallel DCDC circuit of the present application. The multi-phase parallel DCDC circuit in the chip structure will be described in detail below through the embodiments.
请参阅图7，本申请实施例提供一种多相并联DCDC电路，包括：Please refer to Figure 7. This embodiment of the present application provides a multi-phase parallel DCDC circuit, including:
环路运放EA单元701、N个输出级电路单元702及M个驱动单元703，其中，一个驱动单元703对应至少一个输出级电路单元702，输出级电路单元702包括COMP7021及功率级电路7022，N为大于等于2的整数，M为小于等于N的整数；Loop operational amplifier EA unit 701, N output stage circuit units 702 and M drive units 703, wherein one drive unit 703 corresponds to at least one output stage circuit unit 702, and the output stage circuit unit 702 includes COMP7021 and power stage circuit 7022, N is an integer greater than or equal to 2, M is an integer less than or equal to N;
环路运放EA单元701的输出端与驱动单元703的输入端连接；The output end of the loop operational amplifier EA unit 701 is connected to the input end of the drive unit 703;
驱动单元703的输出端与对应的输出级电路单元702中COMP7021的输入端连接，COMP7021的输出端与处于同一个输出级电路单元中的功率级电路的7022输入端连接；The output end of the driving unit 703 is connected to the input end of COMP7021 in the corresponding output stage circuit unit 702, and the output end of COMP7021 is connected to the 7022 input end of the power stage circuit in the same output stage circuit unit;
环路运放EA单元701的输入端与所有功率级电路7022的输出端连接。The input terminal of the loop operational amplifier EA unit 701 is connected to the output terminals of all power stage circuits 7022.
在多相并联DCDC电路中，具有环路运放EA单元701、N个输出级电路单元702及M个驱动单元703，其中，一个驱动单元703对应至少一个输出级电路单元702，例如，驱动单元1对应输出级电路单元1，驱动单元2对应输出级电路单元2和3，输出级电路单元702包括COMP7021及功率级电路7022，由于环路运放EA单元701的输出端与驱动单元703的输入端连接，驱动单元703的输出端与对应的输出级电路单元702中COMP7021的输入端连接，那么环路运放EA单元701的输出电压VEAOUT是经过驱动单元703之后，再通过驱动单元的输出电压VEAOUT_M驱动COMP7021，环路运放EA单元701的输入端与所有功率级电路7022的输出端连接，形成环路结构的电路。与图1所示的多相并联BUCK电路相比，由于环路运放EA单元701的输出端不是直接与所有的COMP7021的输入端连接，而是通过驱动单元703，那么在多相并联DCDC电路的芯片中环路运放EA单元701的输出走线的长度必然减少，环路运放EA单元701的输出走线的寄生电容和寄生电阻减小，而由于驱动单元703的存在，COMP7021无需考虑靠近环路运放EA单元701，可以将COMP7021靠近功率级电路，减少COMP7021的输出走线的寄生电容和寄生电阻，由于寄生电容和寄生电阻越大，带来的寄生极点也就越低频，对于高环路带宽的设计是有很大的影响的，会导致环路的瞬态响应变差，那么本申请减少了环路运放EA单元701和COMP7021的输出寄生电容和寄生电阻，可以提高环路带宽，加快瞬态响应。In the multi-phase parallel DCDC circuit, there are loop operational amplifier EA unit 701, N output stage circuit units 702 and M drive units 703, wherein one drive unit 703 corresponds to at least one output stage circuit unit 702, for example, the drive unit 1 corresponds to the output stage circuit unit 1, and the driving unit 2 corresponds to the output stage circuit units 2 and 3. The output stage circuit unit 702 includes COMP7021 and power stage circuit 7022. Since the output end of the loop operational amplifier EA unit 701 and the input of the driving unit 703 terminal is connected, the output terminal of the driving unit 703 is connected to the input terminal of COMP7021 in the corresponding output stage circuit unit 702, then the output voltage VEAOUT of the loop operational amplifier EA unit 701 passes through the driving unit 703, and then passes through the output voltage of the driving unit VEAOUT_M drives COMP7021, and the input terminal of the loop operational amplifier EA unit 701 is connected to the output terminals of all power stage circuits 7022 to form a loop structure circuit. Compared with the multi-phase parallel BUCK circuit shown in Figure 1, since the output terminal of the loop operational amplifier EA unit 701 is not directly connected to the input terminals of all COMP7021, but through the driving unit 703, then in the multi-phase parallel DCDC circuit The length of the output trace of the loop op amp EA unit 701 in the chip will inevitably be reduced, and the parasitic capacitance and parasitic resistance of the output trace of the loop op amp EA unit 701 will be reduced. However, due to the existence of the driver unit 703, COMP7021 does not need to be considered close to The loop operational amplifier EA unit 701 can place the COMP7021 close to the power stage circuit to reduce the parasitic capacitance and parasitic resistance of the output trace of the COMP7021. Since the larger the parasitic capacitance and parasitic resistance, the lower the frequency of the parasitic pole will be. For high frequency The design of the loop bandwidth has a great influence and will cause the transient response of the loop to deteriorate. Therefore, this application reduces the output parasitic capacitance and parasitic resistance of the loop operational amplifier EA unit 701 and COMP7021, which can improve the loop bandwidth to speed up transient response.
可选的，如图8所示，本申请的一些实施例中，Optionally, as shown in Figure 8, in some embodiments of this application,
驱动单元负向端与驱动单元的输出端连接，驱动单元的正向端与环路运放EA单元的输出端连接。The negative end of the drive unit is connected to the output end of the drive unit, and the positive end of the drive unit is connected to the output end of the loop operational amplifier EA unit.
本申请实施例中，驱动单元用EA来实现，将EA_1至EA_4的负向端和输出端连接，正向端与环路运放EA单元的输出端连接，那么EA的负向端和输出端之间形成一个负反馈，可以对正向端所接收到的运放EA单元的输出的输出电压起到驱动作用，即保证驱动单元输出端输出至COMP的输出电压VEAOUT_1与运放EA单元的输出电压VEAOUT一致，需要说明的是，驱动单元除了可以使用EA实现之外，还可以使用其他的电路器件或电路结构来实现，具体不做限定。In the embodiment of this application, the driving unit is implemented by EA. The negative terminals of EA_1 to EA_4 are connected to the output terminal, and the positive terminal is connected to the output terminal of the loop operational amplifier EA unit. Then the negative terminal of EA and the output terminal are A negative feedback is formed between them, which can drive the output voltage of the op amp EA unit received by the positive end, that is, ensure that the output voltage VEAOUT_1 of the drive unit is output to COMP and the output of the op amp EA unit The voltage VEAOUT is consistent. It should be noted that in addition to using EA to implement the drive unit, it can also be implemented using other circuit devices or circuit structures. There is no specific limit.
需要说明的是，图8中驱动单元EA_1、EA_2、EA_3和EA_4均对应4个输出级电路单元，表示图8为16相并联DCDC电路，在实际应用中，一个驱动单元还可以对应其他数量的输出级电路单元，而且数量不等，具体不做限定。It should be noted that the drive units EA_1, EA_2, EA_3 and EA_4 in Figure 8 all correspond to four output stage circuit units, indicating that Figure 8 is a 16-phase parallel DCDC circuit. In practical applications, one drive unit can also correspond to other numbers. The output stage circuit units vary in number and are not specifically limited.
可选的，如图8所示，本申请的一些实施例中，Optionally, as shown in Figure 8, in some embodiments of this application,
功率级电路包括两个BUF、上功率管M1、下功率管M2、输出电感及输出电容；The power stage circuit includes two BUFs, upper power tube M1, lower power tube M2, output inductor and output capacitor;
COMP的负向端与驱动单元的输出端连接，COMP的正向端与三角波信号端连接，使得COMP输出端输出具有预定占空比的方波电压信号；The negative terminal of COMP is connected to the output terminal of the drive unit, and the positive terminal of COMP is connected to the triangular wave signal terminal, so that the COMP output terminal outputs a square wave voltage signal with a predetermined duty cycle;
两个BUF的输入端分别与COMP的输出端连接，两个BUF的输出端分别与上功率管M1的栅极和下功率管M2的栅极连接，上功率管M1的源极与供电端PVDD连接，下功率管M2的源极与接地端连接，上功率管M1的漏极及下功率管M2的漏极与输出电感的一端连接，输出电感的另一端与输出电容的非接地端连接，输出电容的另一端接地。The input terminals of the two BUFs are respectively connected to the output terminals of COMP. The output terminals of the two BUFs are respectively connected to the gates of the upper power tube M1 and the gate of the lower power tube M2. The source of the upper power tube M1 is connected to the power supply terminal PVDD. connection, the source of the lower power tube M2 is connected to the ground terminal, the drain of the upper power tube M1 and the drain of the lower power tube M2 are connected to one end of the output inductor, and the other end of the output inductor is connected to the non-ground end of the output capacitor. The other end of the output capacitor is connected to ground.
本申请实施例中，在图8所示的电路中，输出级电路单元以BUCK电路为例，根据已知的BUCK电路的电路结构，第一个输出级电路单元中COMP1的负向端与驱动单元的输出端连接，COMP的正向端与三角波信号端连接，三角波信号端提供的三角波形式的电压波形，目的是为了使得COMP1能够根据三角波信号与驱动单元输出的输出信号VEAOUT_1，在COMP1输出端输出具有预定占空比的方波电压信号，预定占空比由预先设置的三角波信号和VEAOUT_1所共同决定，两个BUF的输入端分别与COMP的输出端连接，BUF所起到的作用是驱动，当上功率管M1导通时，下功率管M2不导通；当下功率管M2导通时，上功率管M1不导通，同理，其他输出级电路单元中的元器件的连接与上述的第一个输出级电路单元相同，输出电感L1、L2、L3和L4所连接的输出电容C0一端接地，那么通过输出电感L1、L2、L3和L4和输出电容C0可以将多路功率级电路输出的信号合成一路信号，并且反馈到环路运放EA负向端。In the embodiment of the present application, in the circuit shown in Figure 8, the output stage circuit unit takes the BUCK circuit as an example. According to the known circuit structure of the BUCK circuit, the negative terminal of COMP1 in the first output stage circuit unit is connected to the driver The output end of the unit is connected, and the positive end of COMP is connected to the triangle wave signal end. The triangle wave signal end provides a voltage waveform in the form of a triangle wave. The purpose is to enable COMP1 to output the output signal VEAOUT_1 of the drive unit according to the triangle wave signal. At the output end of COMP1 Output a square wave voltage signal with a predetermined duty cycle. The predetermined duty cycle is determined by the preset triangle wave signal and VEAOUT_1. The input terminals of the two BUFs are connected to the output terminals of COMP respectively. The role of BUF is to drive , when the upper power tube M1 is turned on, the lower power tube M2 is not turned on; when the lower power tube M2 is turned on, the upper power tube M1 is not turned on. In the same way, the connections of the components in other output stage circuit units are as mentioned above. The first output stage circuit unit of The output signal is synthesized into a signal and fed back to the negative terminal of the loop operational amplifier EA.
需要说明的是，在多相并联DCDC电路中输出级电路单元除了BUCK型电路之外，还可以为其他类型的电路，具体不做限定。It should be noted that in the multi-phase parallel DCDC circuit, in addition to the BUCK type circuit, the output stage circuit unit can also be other types of circuits, and there is no specific limitation.
可选的，如图8所示，本申请的一些实施例中，Optionally, as shown in Figure 8, in some embodiments of this application,
环路运放EA单元包括：反馈补偿网络及环路运放EA；The loop operational amplifier EA unit includes: feedback compensation network and loop operational amplifier EA;
反馈补偿网络的第一端口与环路运放EA的负向端连接；The first port of the feedback compensation network is connected to the negative terminal of the loop operational amplifier EA;
反馈补偿网络的第二端口与功率级电路的输出电容的非接地端连接；The second port of the feedback compensation network is connected to the non-ground end of the output capacitor of the power stage circuit;
反馈补偿网络的第三端口与环路运放EA的输出端连接；The third port of the feedback compensation network is connected to the output end of the loop operational amplifier EA;
环路运放EA的正向端与参考电压端Vref连接；The positive terminal of the loop operational amplifier EA is connected to the reference voltage terminal Vref;
反馈补偿网络具体为：The feedback compensation network is specifically:
第二电阻R2与第一电容C1串联后，与第一电阻R1并联，第一电阻R1和第二电阻R2的连接点为第二端口，第二电阻R1和第一电容C1的连接点为第一端口；After the second resistor R2 is connected in series with the first capacitor C1, it is connected in parallel with the first resistor R1. The connection point of the first resistor R1 and the second resistor R2 is the second port, and the connection point of the second resistor R1 and the first capacitor C1 is the second port. one port;
第三电阻R3与第二电容C2串联后，与第三电容C3并联，第三电阻R3和第三电容C3的连接点与第一端口连接，第二电容C2和第三电容C3的连接点为第三端口；After the third resistor R3 is connected in series with the second capacitor C2, it is connected in parallel with the third capacitor C3. The connection point of the third resistor R3 and the third capacitor C3 is connected to the first port. The connection point of the second capacitor C2 and the third capacitor C3 is third port;
第四电阻R4的一端与第一端口连接，另一端与接地端连接。One end of the fourth resistor R4 is connected to the first port, and the other end is connected to the ground terminal.
环路运放EA单元由反馈补偿网络及环路运放EA组成，其中反馈补偿网络的第一端口与环路运放EA的负向端连接，反馈补偿网络的第二端口与功率级电路的输出电容C0的非接地端连接，反馈补偿网络的第三端口与环路运放EA的输出端连接，环路运放EA的正向端与参考电压端Vref连接，反馈补偿网络通过第二端口接收到所有功率级电路的输出电压，通过第一端口接收到环路运放EA的输出电压，第三端口向环路运放EA输入反馈电压VFB，环路运放EA根据负向端的反馈电压VFB和正向端的参考电压Vref，输出差值转换电压VEAOUT，而且反馈补偿网络中包括第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第一电容C1、第二电容C2和第三电容C3，第一电阻R1与第一电容C1串联后，与第二电阻R2并联，第一电阻R1和第二电阻R2的连接点为第二端口，第一电阻R1和第一电容C1的连接点为第一端口，第三电阻R3与第二电容C2串联后，与第三电容C3并联，第三电阻R3和第三电容C3的连接点与第一端口连接，第二电容C2和第三电阻R3的连接点为第三端口，第四电阻R4的一端与第一端口连接，另一端与接地端连接，通通过反馈补偿网络的反馈补偿作用可以对环路运放EA的输出电压VEAOUT进行调整。The loop operational amplifier EA unit is composed of a feedback compensation network and a loop operational amplifier EA. The first port of the feedback compensation network is connected to the negative end of the loop operational amplifier EA, and the second port of the feedback compensation network is connected to the negative end of the power stage circuit. The non-ground end of the output capacitor C0 is connected, the third port of the feedback compensation network is connected to the output end of the loop operational amplifier EA, the forward end of the loop operational amplifier EA is connected to the reference voltage terminal Vref, and the feedback compensation network passes through the second port The output voltage of all power stage circuits is received, and the output voltage of the loop operational amplifier EA is received through the first port. The third port inputs the feedback voltage VFB to the loop operational amplifier EA. The loop operational amplifier EA is based on the feedback voltage of the negative terminal. VFB and the reference voltage Vref at the forward end, output the difference conversion voltage VEAOUT, and the feedback compensation network includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, and a second capacitor C2 and the third capacitor C3. After the first resistor R1 is connected in series with the first capacitor C1, it is connected in parallel with the second resistor R2. The connection point of the first resistor R1 and the second resistor R2 is the second port. The first resistor R1 and the first capacitor The connection point of C1 is the first port. After the third resistor R3 and the second capacitor C2 are connected in series, it is connected in parallel with the third capacitor C3. The connection point of the third resistor R3 and the third capacitor C3 is connected to the first port. The second capacitor C2 The connection point with the third resistor R3 is the third port. One end of the fourth resistor R4 is connected to the first port, and the other end is connected to the ground terminal. The output of the loop operational amplifier EA can be adjusted through the feedback compensation effect of the feedback compensation network. voltage VEAOUT is adjusted.
需要说明的是，反馈补偿网络还可以通过其他的电路结构和电路元器件来实现，具体不做限定。It should be noted that the feedback compensation network can also be implemented through other circuit structures and circuit components, and there is no specific limitation.
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。As mentioned above, the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still make the foregoing technical solutions. The technical solutions described in each embodiment may be modified, or some of the technical features may be equivalently replaced; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions in each embodiment of the present application.
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| US12176306B2 (en) * | 2020-08-07 | 2024-12-24 | Electronics And Telecommunications Research Institute | Electrical circuit of semiconductor channel resistor and apparatus and method for generating the same |
| CN118157469B (en) * | 2023-12-21 | 2025-01-07 | 芯合电子(上海)有限公司 | A switching noise suppression circuit and a switching noise suppression method |
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Also Published As
| Publication number | Publication date |
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| CN110120746A (en) | 2019-08-13 |
| CN106685226B (en) | 2019-05-21 |
| WO2018149098A1 (en) | 2018-08-23 |
| CN106685226A (en) | 2017-05-17 |
| EP3553933A4 (en) | 2020-02-26 |
| US20190348408A1 (en) | 2019-11-14 |
| US10672757B2 (en) | 2020-06-02 |
| EP3553933A1 (en) | 2019-10-16 |
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