CN110120856B - Test vector generation and detection system and method for multi-type test sequences - Google Patents
Test vector generation and detection system and method for multi-type test sequences Download PDFInfo
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
- H04L1/244—Testing correct operation by comparing a transmitted test signal with a locally generated replica test sequence generators
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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Abstract
The invention discloses a test vector generation and detection system and a method of a multi-type test sequence, comprising a test vector generation unit and a test vector detection unit; the test vector generation unit comprises a test vector control unit and a test sequence generation unit; the test vector control unit is used for completing the selection and switching of a test mode and the initial value configuration of the filter; and the test vector detection unit is used for receiving the PRBS31 test sequences, the Pattern1 test sequences and the Pattern2 test sequences, descrambling the data obtained by the receiving end, comparing whether the received test vectors are correct pseudorandom sequences or not, recording error times and feeding back the error times. The PCS sublayer test vector management method is stably applicable to a common high-speed Ethernet communication controller; the invention can work under five test sequence modes of square wave, PRBS9, PRBS31, Pattern1 and Pattern2, has wide application range and can meet the requirements of different Ethernet link test platforms.
Description
Technical Field
The invention relates to a test vector generation and detection system and method for multi-type test sequences.
Background
The Test Pattern (Test Pattern) is a binary sequence used for detecting the bit error rate in the data transmission process in the ethernet PCS (physical coding sublayer), and includes a square wave and a pseudo random sequence (PRBS for short), and different Test sequences can be used for testing different characteristics of the ethernet data link. In the high-speed Ethernet communication controller, multiple transmission problems may occur in a data link, a single test sequence cannot comprehensively detect the problems existing in the data link, and a test device cannot be transplanted to other common high-speed Ethernet controllers for use, and meanwhile, automatic matching of seeds and data is difficult to realize at the transmitting end and the receiving end of the conventional test device. In summary, a test management method supporting online dynamic switching of multi-type test sequences and automatic matching of test sequence seeds and data with strong portability is needed.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a test vector generation and detection system and a test vector generation and detection method for multi-type test sequences, based on the test characteristics of a 10G Ethernet data link, the invention integrates five test sequences such as square waves, PRBS9, PRBS31, Pattern1, Pattern2 and the like, realizes the online dynamic switching of test vector types, simultaneously realizes the automatic matching of seeds and data at the transmitting end and the receiving end, provides a solution for the 10G Ethernet link test, and can be independently used as a test management device of other high-speed communication controllers to become an auxiliary measurement means of the high-speed communication link.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
a test vector generation and detection system of multi-type test sequences comprises a test vector generation unit and a test vector detection unit;
the test vector generation unit comprises a test vector control unit and a test sequence generation unit; the test vector control unit is used for completing the selection and switching of a test mode and the initial value configuration of the filter; the test sequence generation unit comprises a square wave sequence generation filter, a PRBS9 sequence generation filter, a PRBS31 sequence generation filter, a Pattern1 sequence generation filter and a Pattern2 sequence generation filter;
and the test vector detection unit is used for receiving the PRBS31 test sequences, the Pattern1 test sequences and the Pattern2 test sequences, descrambling the data obtained by the receiving end, comparing whether the received test vectors are correct pseudorandom sequences or not, recording error times and feeding back the error times.
The invention further improves the following steps:
the square wave sequence generating filter, the PRBS9 sequence generating filter, the PRBS31 sequence generating filter, the Pattern1 sequence generating filter and the Pattern2 sequence generating filter all complete the generation of test sequences under the control of the test vector control unit.
A test vector generation and detection method for multi-type test sequences comprises the following steps:
step 1: selecting a test mode through an external port according to the test requirements of a user, generating a corresponding test sequence generation filter control signal, and completing the selection of the test mode;
step 2: carrying out initial value configuration on a corresponding test sequence generation filter through an external port to complete initialization of the filter;
and step 3: when other test modes need to be switched in the using process, a stop signal is immediately generated to control the current working filter to stop running, and meanwhile, a test mode control signal needing to be used is generated to control the test sequence generating unit to switch the test sequence generating filter, so that the switching of the test modes is completed.
The further improvement is that:
when the square wave sequence is generated, the initial value is not required to be set, and the input data are n1 and n 0 in succession.
Generating a PRBS9 sequence and a PRBS31 sequence, wherein the PRBS9 sequence and the PRBS31 sequence respectively use independent filters, and the initial values of the filters are not all zero;
the same filter is used for generating the Pattern1 sequence and the Pattern2 sequence, filter input data determination occurs, and initial values are dynamically configured through registers.
Compared with the prior art, the invention has the following beneficial effects:
the PCS sublayer test vector management method is stably applicable to a common high-speed Ethernet communication controller; the invention can work under five test sequence modes of square wave, PRBS9, PRBS31, Pattern1 and Pattern2, has wide application range and can meet the requirements of different Ethernet link test platforms; according to the invention, a user only needs to configure the test mode according to the test requirement, and the rest of work is transparent to the user, so that the operation is simple and convenient.
Drawings
FIG. 1 is a block diagram of a test vector generation unit according to the present invention;
FIG. 2 is a block diagram of a test vector detection unit according to the present invention.
Wherein: 1-a test vector control unit; 2-a test sequence generation unit; 3-square wave sequence generation filter; a 4-PRBS9 sequence generation filter; 5-PRBS31 sequence generation filter; a 6-Pattern1 sequence generation filter; a 7-Pattern2 sequence generation filter; 8-PRBS9 sends an enable signal; 9-PRBS31 sends an enable signal; 10-send test vector enable signal; 11-test vector select signal; 12-data type select signal; 13-a test vector detection unit; 14-Pattern1& Pattern2 sequence filtering unit; 15-PRBS31 sequence filtering unit; 16-error detection and enable test vector control unit; 17-Pattern1 or Pattern2 filtered data signals; 18-Pattern1& Pattern2 filtering enable signal; 19-PRBS31 filtered data signal; 20-PRBS31 filter enable signal; 21-test vector receive enable signal; the 22-PRBS31 receives the enable signal.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments, and are not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Various structural schematics according to the disclosed embodiments of the invention are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers and their relative sizes and positional relationships shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, according to actual needs.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the accompanying drawings:
referring to fig. 1 and 2, the multi-type test sequence test vector generation and detection system method of the present invention includes a test vector generation unit and a test vector detection unit; the test vector generating unit comprises a test vector control unit 1 and a test sequence generating unit 2; the test vector control unit 1 is used for completing the selection and switching of a test mode and the initial value configuration of a filter; the test sequence generation unit 2 comprises a square wave sequence generation filter 3, a PRBS9 sequence generation filter 4, a PRBS31 sequence generation filter 5, a Pattern1 sequence generation filter 6 and a Pattern2 sequence generation filter 7; and the test vector detection unit 13 is configured to receive three test sequences, namely PRBS31, Pattern1, and Pattern2, descramble data obtained by the receiving end, compare whether the received test vector is a correct pseudorandom sequence, record error times, and perform feedback.
The test vector generating unit can generate five test sequences of square waves, PRBS9, PRBS31, Pattern1, Pattern2 and the like at a transmitting end, and comprises a test vector control unit 1 and a test sequence generating unit 2.
The test vector control unit needs to complete the test mode selection and switching and the initial filter value configuration. Firstly, the unit can select a test mode through an external port according to the test requirements of a user, generate a corresponding test sequence generation filter control signal and complete the selection of the test mode; secondly, the unit can carry out initial value configuration on the corresponding test sequence generation filter through an external port to complete the initialization of the filter; finally, when other test modes need to be switched in the using process, the unit immediately generates a stop signal to control the current working filter to stop running, and simultaneously generates a test mode control signal to be used to control the test sequence generating unit to switch the test sequence generating filter, thereby completing the switching of the test modes.
When the filter is controlled to work, the default initial value of the internal filter of the unit can be used, and the initial value can be freely configured according to needs. When square waves are generated, initial values do not need to be set, and input data are n continuous 1 s and n continuous 0 s; generating PRBS9 and PRBS31 which respectively use independent filters, and only need to generate non-all-zero initial values of the filters; the generation Pattern1 and the Pattern2 use the same filter, filter input data determination occurs, and the initial values are dynamically configurable via registers. The specific requirements of the five test sequences are shown in table 1.
TABLE 1 test sequence input data and initial value configuration requirements
The test sequence generation unit comprises a square wave sequence generation filter 3, a PRBS9 sequence generation filter 4, a PRBS31 sequence generation filter 5, a Pattern1 sequence generation filter 6 and a Pattern2 sequence generation filter 7, wherein the generation filters of the five test sequences are independent from each other and do not influence each other, but the generation of the test sequences is completed under the control of the test vector control unit.
The test vector detection unit 13 can detect three test sequences, i.e., PRBS31, Pattern1, Pattern2, at the receiving end, descramble the data obtained at the receiving end after the test vector detection unit is started, compare whether the received test vector is a correct pseudorandom sequence, and record the number of errors for feedback, wherein the descrambling mode used by the PRBS31 is different from that used by the Pattern1 and the Pattern 2.
When the Pattern1 and the Pattern2 are used for detection, because a seed is reused every 128 data blocks at the sending end, an error occurs every 128 data blocks at the receiving end, the error state is automatically cleared and is not accumulated, the error times generated by other forms are accumulated, and the error times of the data blocks are accumulated by the error register in the test mode.
When using the PRBS31 mode for detection, each bit data error is recorded by a corresponding register, and the error register accumulates the number of bit errors in the data block.
Except that the square wave and the PRBS9 can not be applied to the receiving end, the other three test sequences can be detected by a test vector detection unit of the receiving end, the filters used in the corresponding modes are the same, the initial values are the same, and the initial values of the seed register and the input data can be synchronously updated after the test mode is selected.
The test vector generation unit structure is shown in fig. 1. The test vector control unit 1 configures the register according to the requirement to enable the test sequence generation unit 2 to output a corresponding test sequence. When the transmission test vector enable signal 10 is 1 'b 1 and the test vector selection signal 11 is 1' b1, the square wave sequence generation filter 3 outputs a square wave sequence; when the transmission test vector enable signal 10 is 1 ' b1, the test vector select signal 11 is 1 ' b0, and the data type select signal 12 is 1 ' b0, the Pattern1 sequence generating filter 6 outputs a Pattern1 sequence; when the transmission test vector enable signal 10 is 1 ' b1, the test vector select signal 11 is 1 ' b0, and the data type select signal 12 is 1 ' b1, the Pattern2 sequence generating filter 7 outputs a Pattern2 sequence; when the transmission test vector enable signal 10 is 1 ' b0, the PRBS9 transmission enable signal 8 is 1 ' b1, and the PRBS31 transmission enable signal 9 is 1 ' b0, the PRBS9 sequence generating filter 4 outputs a PRBS9 sequence; when the transmission test vector enable signal 10 is 1 ' b0, the PRBS9 transmission enable signal 8 is 1 ' b0, and the PRBS31 transmission enable signal 9 is 1 ' b1, the PRBS31 sequence generating filter 5 outputs a PRBS31 sequence.
The test vector detection unit structure is shown in fig. 2. After the test vector control unit 1 determines the test sequence generated by the sending end, the receiving end starts the test vector detection unit 13 at the same time to realize the butt joint of the sending end and the receiving end. When the test vector reception enable signal 21 is 1 ' b1 and the data type selection signal 12 is 1 ' b1, the Pattern1& Pattern2 sequence filtering unit 14 is activated (the detection is a detection process of a Pattern2 sequence), the data signal 17 after the Pattern1 or the Pattern2 filtered output by the Pattern1& Pattern2 sequence filtering unit 14 is compared with 64 ' h0 in the error detection and enable test vector control unit 16, if the data signal is not consistent with the data signal 17, the error counter in the error detection and enable test vector control unit 16 is once accumulated, the data block number counter of the module 128 in the error detection and enable test vector control unit 16 is simultaneously activated, and each time the data block number counter in the error detection and enable test vector control unit 16 is 0, a first error clear signal is generated to ensure that the error is not accumulated. When the test vector reception enable signal 21 is 1 'b 1 and the data type selection signal 12 is 1' b0, the Pattern1& Pattern2 sequence filter unit 14 is activated (the detection is a detection process of a Pattern1 sequence), the data signal 17 after the Pattern1 or the Pattern2 filtered by the Pattern1& Pattern2 sequence filter unit 14 is compared with 64 'h 5500_0001_0000_0001 or 64' h8000_0000_8000_00AA in the error detection and enable test vector control unit 16, if the data signal is inconsistent, the error counter in the error detection and enable test vector control unit 16 is accumulated once, and the subsequent operation is the same as the detection of the Pattern2, which is not repeated. The PRBS31 sequence filter unit 15 is enabled when the test vector receive enable signal 21 is 1 ' b0 and the PRBS31 receive enable signal 22 is 1 ' b1, while the error detection and enable test vector control unit 16 records the number of 1 ' b1 in the PRBS31 filtered data signal 19 and accumulates this number into an error counter within the error detection and enable test vector control unit 16.
According to the scheme, a Verilog HDL language is used for describing the logic design of the test vector generation unit and the test vector detection unit, and logic synthesis and layout wiring are completed; the scheme is used in the high-speed time-triggered Ethernet PCS sublayer controller based on optical interconnection, and the function test is carried out, and the test result shows that the method has good implementation, and can realize the online dynamic switching of multi-type test vectors and the automatic matching of test sequence seeds and data.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (5)
1. A test vector generation and detection system of multi-type test sequences is characterized by comprising a test vector generation unit and a test vector detection unit;
the test vector generation unit comprises a test vector control unit (1) and a test sequence generation unit (2); the test vector control unit (1) is used for completing the selection and switching of a test mode and the initial value configuration of a filter; the test sequence generation unit (2) comprises a square wave sequence generation filter (3), a PRBS9 sequence generation filter (4), a PRBS31 sequence generation filter (5), a Pattern1 sequence generation filter (6) and a Pattern2 sequence generation filter (7);
when square waves are generated, initial values do not need to be set, and input data are n continuous 1 s and n continuous 0 s; generating PRBS9 and PRBS31 which respectively use independent filters, and only need to generate non-all-zero initial values of the filters; the same filter is used for generating Pattern1 and Pattern2, filter input data determination occurs, and initial values can be dynamically configured through a register;
the test sequence generation unit is used for generating a square wave sequence generation filter (3), a PRBS9 sequence generation filter (4), a PRBS31 sequence generation filter (5), a Pattern1 sequence generation filter (6) and a Pattern2 sequence generation filter (7) under the control of the test vector control unit;
and the test vector detection unit (13) is used for receiving the three test sequences of PRBS31, Pattern1 and Pattern2, descrambling the data obtained by the receiving end, comparing whether the received test vector is a correct pseudorandom sequence, recording the error times and feeding back the error times.
2. A method for test vector generation and detection using multi-type test sequences in the system of claim 1, comprising the steps of:
step 1: selecting a test mode through an external port according to the test requirements of a user, generating a corresponding test sequence generation filter control signal, and completing the selection of the test mode;
step 2: carrying out initial value configuration on a corresponding test sequence generation filter through an external port to complete initialization of the filter;
and step 3: when other test modes need to be switched in the using process, a stop signal is immediately generated to control the current working filter to stop running, and meanwhile, a test mode control signal needing to be used is generated to control the test sequence generating unit to switch the test sequence generating filter, so that the switching of the test modes is completed.
3. The method of claim 2, wherein the input data are consecutive n1 s and n 0 s without setting an initial value when generating the square wave sequence.
4. The method of claim 2, wherein the generating of the PRBS9 sequence and the generating of the PRBS31 sequence each use a separate filter, and wherein the non-all-zero initial filter values occur.
5. The method of claim 2, wherein the generating Pattern1 sequence and the Pattern2 sequence use the same filter, the filter input data determination occurs, and the initial values are dynamically configured by registers.
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