CN110233140A - Semiconductor devices and forming method thereof and working method - Google Patents
Semiconductor devices and forming method thereof and working method Download PDFInfo
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- CN110233140A CN110233140A CN201810179409.2A CN201810179409A CN110233140A CN 110233140 A CN110233140 A CN 110233140A CN 201810179409 A CN201810179409 A CN 201810179409A CN 110233140 A CN110233140 A CN 110233140A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 156
- 238000000034 method Methods 0.000 title claims abstract description 76
- 238000012360 testing method Methods 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 106
- 239000000523 sample Substances 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims description 176
- 239000011241 protective layer Substances 0.000 claims description 50
- 239000011248 coating agent Substances 0.000 claims description 45
- 238000000576 coating method Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 238000013461 design Methods 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000002633 protecting effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000006378 damage Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
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- 230000005669 field effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
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- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000013528 metallic particle Substances 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0651—Function
- H01L2224/06515—Bonding areas having different functions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A kind of semiconductor devices and forming method thereof and working method, wherein semiconductor devices includes: semiconductor substrate, and the semiconductor substrate includes device region and non-device area, has the device main body being electrically connected to each other and interconnection structure in semiconductor substrate device region；Positioned at connection liner, test pads and the conducting wire of semiconductor substrate surface, connection liner is connected with interconnection structure, connection liner and test pads are electrically connected by conducting wire, and connection liner is located at semiconductor substrate device region, and test pads are located at semiconductor substrate non-device area；The conducting wire is used to after probe test fuse, and disconnects connection liner and test pads.The performance of the semiconductor devices is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof and work side
Method.
Background technique
MOS (Metal-oxide-semicondutor) transistor is one of most important element in modern integrated circuits.MOS is brilliant
The basic structure of body pipe includes: semiconductor substrate；Positioned at the gate structure of semiconductor substrate surface, the gate structure includes:
Gate electrode layer positioned at the gate dielectric layer of semiconductor substrate surface and positioned at gate dielectric layer surface；Positioned at gate structure two sides half
Source and drain doping area in conductor substrate.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin and the gate structure of side wall described in covering part are located at grid knot
Source and drain doping area in the fin of structure two sides.
However, the performance for the semiconductor devices that fin formula field effect transistor is constituted in the prior art is still to be improved.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor devices and forming method thereof and working methods, to improve
The performance of semiconductor devices.
In order to solve the above technical problems, the present invention provides a kind of semiconductor devices, comprising: semiconductor substrate, it is described partly to lead
Body substrate includes device region and non-device area, and the semiconductor substrate device region is interior with the device main body being electrically connected to each other and mutual
Link structure；Positioned at connection liner, test pads and the conducting wire of semiconductor substrate surface, connection liner is connected with interconnection structure,
Connection liner and test pads are electrically connected by conducting wire, and connection liner is located at semiconductor substrate device region, and test pads are located at
Semiconductor substrate non-device area, the conducting wire are used to after probe test fuse, and disconnect connection liner and test pads.
Optionally, the connection liner includes the first back lining bed course, and the first back lining bed course is located at semiconductor lining
In the device region top surface of bottom, and the first back lining bed course is connected with interconnection structure；The test pads include the second bottom
Laying, the second back lining bed course are located in semiconductor substrate non-device area top surface；The conducting wire is located at semiconductor
In top surface, the second back lining bed course is electrically connected with the first back lining bed course by the conducting wire.
Optionally, the connection liner further includes the first topper cushion layer positioned at the first bottom liner layer surface.
Optionally, the test pads further include the second topper cushion layer positioned at the second bottom liner layer surface.
Optionally, further includes: the coating in semiconductor substrate and on the first back lining of part bed course, in coating
With the first opening, the first opening exposes the atop part surface of the first back lining bottom；First in the first opening
Topper cushion layer, the first protective layer at the top of the first top layer substrate layer, the first protective layer is interior to have third opening.
Optionally, the coating is also located in semiconductor substrate and part the second back lining bed course, is had in coating
Second opening, the second opening expose the atop part surface of the second back lining bottom；The second top layer in the second opening
Laying, the second protective layer at the top of the second top layer substrate layer, the second protective layer is interior to have the 4th opening.
The present invention also provides a kind of working methods of semiconductor devices, comprising: provides the half of an any of the above-described kind of structure
Conductor device；Probe test is carried out to the test pads surface using probe, the electrical parameter for acquisition device main body；It visits
After needle test, fuse the conducting wire, so that the connection substrate and test pads open circuit.
Optionally, the method for fused wire includes: using conducting wire described in laser blown.
Optionally, the coating also covers the conducting wire；The method of fused wire includes: in semiconductor substrate device region
On coating in form wire openings, the wire openings expose the part of the surface of conducting wire；After probe test, fused wire
The conducting wire of open bottom.
The present invention also provides a kind of forming methods of semiconductor devices, comprising: provides semiconductor substrate, the semiconductor lining
Bottom includes device region and non-device area, has the device main body being electrically connected to each other and interconnection structure in semiconductor substrate device region；
It is respectively formed connection liner, test pads and conducting wire in semiconductor substrate surface, connection liner is connected with interconnection structure, connects
Liner and test pads are electrically connected by conducting wire, and the connection substrate is located at semiconductor substrate device region, the test pads
Positioned at semiconductor substrate non-device area；The conducting wire is used to after probe test fuse, and makes connection liner and test pads
It disconnects.
Optionally, the connection liner includes the first back lining bed course, and the first back lining bed course is located at semiconductor lining
In the device region top surface of bottom, and it is connected with interconnection structure；The test pads include the second back lining bed course, described second
Back lining bed course is located in semiconductor substrate non-device area top surface, the second back lining bed course and the first back lining bed course
It is electrically connected by conducting wire, the conducting wire also is located in semiconductor substrate top surface.
Optionally, the connection liner further includes the first topper cushion layer positioned at the first bottom liner layer surface；It is described
Test pads further include the second topper cushion layer positioned at the second bottom liner layer surface.
Optionally, the forming method of the connection liner includes: to form coating on a semiconductor substrate；It is served as a contrast in semiconductor
The first opening is formed in coating on bottom, first opening exposes the atop part surface of the first back lining bed course；Shape
After the first opening, the first initial topper cushion layer is formed in first opening；After forming the first initial topper cushion layer,
The first protective layer is formed in the first initial topper cushion layer surface；After forming the first protective layer, etching removal part first is protected
Layer and the initial topper cushion layer in part first, form third opening in the first protective layer, and the first topper cushion layer is located at
Third open bottom.
Optionally, the forming method of the described first initial topper cushion layer includes: to be formed in coating and the first opening
Initial topper cushion material layer；The initial topper cushion material layer is planarized, until the top surface of coating is exposed,
The first initial topper cushion layer is formed in first opening.
Optionally, the forming method of the test pads includes: that the second opening, institute are formed in semiconductor substrate coating
State the atop part surface that the second opening exposes the second back lining bed course；The second initial top layer is formed in second opening
Laying；The second protective layer is formed in the second initial topper cushion layer surface；Etching removal the second protective layer of part and part the
Two initial topper cushion layers, form the 4th opening in the second protective layer, and the second topper cushion layer is located at the 4th open bottom
Portion.
Optionally, the forming method of the described second initial topper cushion layer includes: that initial top is also formed in the second opening
Layer cushioning material layer；The initial topper cushion material layer is planarized, until exposing the top surface of coating, is opened second
The second initial topper cushion layer is formed in mouthful.
Optionally, the connection liner and test pads are formed in identical formation process.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the semiconductor devices that technical solution of the present invention provides, test pads are located in non-device area, are not take up semiconductor
The spatial area of device, and for probe test when, will not damage connection liner, connection pad surfaces it is in good condition, be conducive to
Improve the yield in subsequent encapsulation plant ball technique.Probe test simultaneously carries out in test pads, reduces on connection liner
The probability for forming particle reduces the probability that semiconductor devices wafer is damaged during planting ball, to improve semiconductor devices
Performance and yield.
Further, connection liner and test pads separate, and the area for connecting liner, which need to only meet in subsequent encapsulating process, plants
Area design required for ball technique does not need to test reserved test area for probe, is conducive to reduce connection liner
Area complies with the trend of device size microminiaturization development.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of semiconductor devices；
Fig. 2 to Figure 10 is the structural schematic diagram of the forming process of the semiconductor devices of one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
A kind of semiconductor devices, referring to FIG. 1, including: semiconductor substrate 100；Device in semiconductor substrate 100
Main body (not shown) and liner, it is described liner include back lining bed course 101 and topper cushion layer 102, back lining bed course 101 with
Device main body electrical connection, 101 top surface of back lining bed course are flushed with 100 top surface of semiconductor substrate；Positioned at bottom liner
Coating 103 on layer 101, coating is interior to have topper cushion layer 102, and topper cushion layer 102 is located at 101 table of back lining bed course
Face；Protective layer 104 positioned at 102 surface of topper cushion layer, protective layer 104 is interior to have opening, and opening exposes topper cushion layer
102 top surfaces.
In semiconductor technology, the electric property of semiconductor devices is detected using probe test, probe test is destructiveness
Test, probe can prick into laying, and probe may take the partial particulate in laying out of during lifting, and fall to
Laying surface plants ball technique since subsequent laying will do it, and plant ball technique is more demanding to surfacing, if surface has
Particle, ball attachment machine plant ball during pressure may be such that the chipping risk of the wafer of semiconductor devices, so as to cause
The performance decline of semiconductor devices and yield reduce.
In order to reduce destruction of the probe test to laying, the yield for planting ball technique is improved, leading to way is to reserve a part
Laying dedicated for probe test, be not applied to probe test laying it is subsequent carry out plant ball technique, can mention in this way
The yield of Gao Zhiqiu technique, but can make the area of laying is opposite to increase, violate becoming for the microminiaturization of semiconductor devices
Gesture, while the probe test zone of action remains as laying, still has metallic particles to be taken out of by probe, falls to laying surface
Risk.
The present invention in semiconductor substrate non-device area by forming test pads, and connection liner is with test pads by leading
Line is electrically connected, and test pads are tested for probe, after probe is tested, is disconnected connection between the two, will not half-and-half be led
The performance of body device impacts, while test pads are discrete out, reduces influence of the probe test to connection liner, has
Conducive to the performance for improving semiconductor devices.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 10 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Fig. 2 and Fig. 3 are please referred to, Fig. 2 is the sectional view along cutting line M-M1 in Fig. 3, and Fig. 3 is that the plan structure of Fig. 2 is shown
It is intended to provide semiconductor substrate 200, the semiconductor substrate 200 includes device region I and non-device area II, semiconductor substrate 200
There is the device main body 201 being electrically connected to each other and interconnection structure in device region I.
The semiconductor substrate 200 also has back lining bed course 210, and the back lining bed course 210 includes the first back lining
Bed course 211, the second back lining bed course 212 and conducting wire 220, the first back lining bed course 211 and the second back lining bed course 212 are by leading
Line 220 connects, and the first back lining bed course 211 is located in 200 device region I of semiconductor substrate, the first back lining bed course
211 are connected with interconnection architecture realizes being electrically connected for device main body 201 and the first back lining bed course 211, second bottom liner
Floor 212 is located in 200 non-device area II of semiconductor substrate.
The top surface of back lining bed course 210 is flushed with 200 top surface of semiconductor substrate.
Using this kind design back lining bed course 210 can more semiconductor substrate 200 rationally distributed design first
The position of back lining bed course and the second back lining bed course.
Extended meeting forms the first topper cushion layer to form connection liner, in the second bottom on the first back lining bed course afterwards
The second topper cushion layer is formed on laying to form test pads.Test pads are subsequently used for probe test, test pads
In non-device area, when being not take up the spatial area of semiconductor devices, and testing for probe, connection liner will not be damaged,
Connection pad surfaces are in good condition, are conducive to improve the yield in subsequent encapsulation plant ball technique.Probe test simultaneously is served as a contrast in test
It is carried out on pad, reduces the probability for forming particle on connection liner, reduce and damage semiconductor devices wafer during planting ball
Probability, to improve the performance and yield of semiconductor devices.
Connection liner and test pads separate, and the area for connecting liner need to only meet plant ball technique institute in subsequent encapsulating process
The area design needed does not need to test reserved test area for probe, is conducive to the area for reducing connection liner, complies with
The trend of device size microminiaturization development.
The material of the semiconductor substrate 200 includes silicon, germanium, SiGe or GaAs.In the present embodiment, the semiconductor
The material of substrate 200 is silicon.
The material of the back lining bed course 210 includes aluminium, tungsten, silver, copper, platinum or their alloy.The back lining bed course
210 connect it is necessary to have low conductivity with interconnection structure, take cost factor into consideration, in the present embodiment, the back lining bed course
210 material is copper, i.e., the material of the first back lining bed course, the second back lining bed course and conducting wire is copper.
The conducting wire 220 is along being parallel to 200 extending direction of semiconductor substrate and perpendicular to the width of 220 extending direction of conducting wire
More than or equal to 2um.
220 width of conducting wire is less than 2um, and the resistivity of conducting wire is higher, divides larger on conducting wire, influences the survey of semiconductor devices
Test result.
The forming method of the back lining bed course 210 includes: that the first inter-level dielectric is sequentially depositing on top layer interconnection structure
Layer and the second interlayer dielectric layer；After forming the second interlayer dielectric layer, the first graphical photoetching is formed on the second interlayer dielectric layer
Glue-line, the first graphical photoresist layer expose the first back lining bed course, the second back lining bed course and conducting wire shape and
Position；Using the first graphical photoresist layer as exposure mask, second interlayer dielectric layer is etched, forms groove；Form first groove
Afterwards, the first graphical photoresist layer is removed；After removing the first graphical photoresist layer, the shape in the second interlayer dielectric layer and groove
At second graphical photoresist layer, the second graph photoresist layer exposes the position being conducted for top layer interconnection structure；With
Second graphical photoresist layer is exposure mask, etches first interlayer dielectric layer, forms through-hole, removes second graphical photoresist
Layer, the deposited metal in through-hole and groove form back lining bed course.
Referring to FIG. 4, forming coating 202 on 200 surface of semiconductor substrate.
The coating 202 is located at the 200 non-device area surface II 200 device region I of semiconductor substrate and semiconductor substrate, covers
The first back lining of lid bed course 211, the second back lining bed course 212 and conducting wire 220.
The coating 202 is for protecting semiconductor substrate 200 and conducting wire 220.
The material of the coating 202 includes: silica, silicon nitride or silicon oxynitride.
In the present embodiment, the material of the coating 202 is silica.
The technique for forming the coating includes chemical vapor deposition process, physical gas-phase deposition or atomic layer deposition
Technique.
Referring to FIG. 5, forming first in the coating 202 of 200 device region I of semiconductor substrate after forming coating 202
Opening 203, first opening 203 expose the atop part surface of the first back lining bed course 211.
Correspondingly, the second opening 213 is formed in the coating 202 on the 200 non-device area surface II of semiconductor substrate, it is described
Second opening 213 exposes the top surface of the second back lining bed course 212.
In the present embodiment, the first opening 203 and the second opening 213 are formed in identical processing procedure, form the first opening 203
While formed second opening 213.
In other embodiments, the first opening 203 and the second opening 213 are not formed simultaneously.
The method for forming first opening 203 and the second opening 213 includes: the formation third figure on coating 202
The photoresist layer of change, the graphical photoresist layer of third expose the position of the first back lining bed course and the second laying；With
The graphical photoresist layer of third is exposure mask, etches the coating 202, until exposing the first back lining bed course and second
The surface of laying forms the first opening 203 on the first back lining bed course, forms second on the second back lining bed course 212
Opening 213；Later, the graphical photoresist layer of the third is removed.
The shape of the first opening and the second opening designs for T-type, the opening of T-type design, in existing board processing procedure energy
Under the premise of power, which can be to not being wrapped up effectively in back lining bed course by the region that topper cushion layer covers, bottom
The material of laying is copper, which can prevent copper from spreading and aoxidizing, while provide effective area to form liner.
Referring to FIG. 6, forming the first initial topper cushion layer in first opening 203 after forming the first opening 203
204。
The first initial topper cushion layer 204 is located at the surface of the first back lining bed course 211.
Correspondingly, forming the second topper cushion layer 214, the second initial topper cushion in second opening 213
Layer 214 is located at the surface of the second back lining bed course 212.
In the present embodiment, the first initial topper cushion layer 204 and the second initial topper cushion layer 214 are in same processing procedure
Middle formation.
The method for forming the described first initial topper cushion layer 204 and the second initial topper cushion layer 214 includes: to form
After one opening 203 and the first opening 213, formed in first opening 203, in the second opening 213 with 202 surface of coating
Initial topper cushion material layer (not shown)；After forming the initial top layer substrate material layer, the initial top layer lining is planarized
The mat material bed of material forms the described first initial top layer lining until exposing the top surface of coating 202 in the first opening 203
Bed course 204 forms the described second initial topper cushion layer 214 in the second opening 213.
The material of the initial topper cushion material layer includes: aluminium.
The material of first bottom backing layer and the second bottom backing layer is copper, and copper is easy to aoxidize and migrate, and aluminium can be
Outer surface forms alumina passivation layer, and changing passivation layer can prevent aluminium from continuing to aoxidize, to reach protection connection liner and survey
Try liner effect, while the electric conductivity of aluminium it is also higher and and the connecting material in subsequent encapsulating process combination it is preferable.
In other embodiments, the first initial topper cushion layer 204 and the second initial topper cushion layer be not in same system
It is formed in journey.
In the present embodiment, the liner only includes back lining bed course and topper cushion layer.Specifically, connection liner includes the
One back lining bed course and the first topper cushion layer, test pads include the second back lining bed course and the second topper cushion layer.
In other embodiments, the laying includes back lining bed course, topper cushion layer and intervening gasket layer, the centre
Laying can be one layer, or multilayer.According to the laying for needing to select suitable construction of device.
Referring to FIG. 7, after forming the first initial topper cushion layer 204 and the second initial topper cushion layer 214, at the beginning of first
204 surface of beginning topper cushion layer forms the first protective layer 205.
First protective layer 205 is for protecting the first initial topper cushion layer 204, for the protecting effect meeting reached
While the first initial topper cushion layer 204 of covering part, the part covering around the first initial topper cushion layer 204 is also covered
Layer 202.
The material of first protective layer 205 includes: silica, silicon nitride or silicon oxynitride.
Correspondingly, forming the second protective layer 215 on the second initial 214 surface of topper cushion layer.
The material of second protective layer 215 includes: silica, silicon nitride or silicon oxynitride.
Second protective layer 215 is for protecting the second initial topper cushion layer 214, for the protecting effect meeting reached
While the second initial topper cushion layer 214 of covering part, the part covering around the second initial topper cushion layer 214 is also covered
Layer 202.
In the present embodiment, first protective layer 205 and the second protective layer 215 are formed in same processing procedure.
The technique for forming first protective layer 205 and the second protective layer 215 includes chemical vapor deposition process, physics gas
Phase depositing operation or atom layer deposition process.
The material of first protective layer 205 and the second protective layer 215 is silica.
In other embodiments, it is not formed simultaneously the first protective layer 205 and the second protective layer 215.
Referring to FIG. 8, the part the after forming the first protective layer 205, on etching removal 200 device region I of semiconductor substrate
One protective layer 205, the initial topper cushion layer 204 in part first and part of covering layer 202 form the first headliner layer 209, the
Three openings 206 and wire openings 207, the third opening 206 is in the first protective layer 205, the first topper cushion layer 209
Positioned at 206 bottoms of third opening, the wire openings 207 are positioned in layer 202, and expose 220 atop part table of conducting wire
Face.
Correspondingly, at the beginning of etching removes the first protective layer of part 205 and part first on 200 device region I of semiconductor substrate
Beginning topper cushion layer 204 forms the first headliner layer 209 and third opening 206, etching removal 200 device of semiconductor substrate
The initial topper cushion floor 214 of the second protective layer of the area part II 215 and part second forms the second topper cushion layer 219 and the 4th
Opening 216, the second topper cushion layer 219 is located at the 4th open bottom 216.
The wire openings 207 are formed during forming the third opening 206.
In the present embodiment, the material of first protective layer 206 and the second protective layer 216 is silica, the coating
202 material is silica.Can be during etching remove the first protective layer of part 206, etching removal part of covering layer,
Until exposing the top surface of conducting wire 220, wire openings 207 are formed in coating 202.
Specifically, the method for forming the first headliner layer 209, the second headliner layer 219 and wire openings 207
It include: that the 4th graphical photoresist layer (not shown) of formation, the 4th graphical photoresist layer are sudden and violent on semiconductor substrate 200
Expose shape and the position of the 206, the 4th opening 216 and wire openings 207 of third opening；With the 4th graphical photoresist layer
For mask etching the first protective layer 205, the second protective layer 215 and coating 202, until exposing the first initial topper cushion layer
204, the atop part surface of the second initial topper cushion layer 214 and conducting wire 220, the shape on the first initial topper cushion layer 204
At third initial openings (not shown), the 4th initial openings (not shown) are formed on the second initial topper cushion layer 214, are being covered
Wire openings 207 are formed in cap rock 202, the wire openings 207 expose the part of the surface of conducting wire 220；It is initial to form third
After opening and the 4th initial openings, the 4th graphical photoresist layer is removed, forms the 5th graphical photoresist on coating 202
Layer (not shown), the 5th graphical photoresist layer expose third initial openings (not shown) and the 4th initial openings (not
Diagram)；Using the 5th graphical photoresist layer as exposure mask, the etching removal initial topper cushion layer 204 and second in part first
Initial topper cushion layer 214, forms third opening 206 in the first protective layer 205, and third opening 209 exposes the first top
Laying 209, forms the 4th opening 216 in the second protective layer 215, and the 4th opening 216 exposes the second headliner layer
219。
The purpose for etching removal protective layer is so that connection liner and test pads top opening, facilitate follow-up test
And encapsulation.The purpose of the etching removal initial topper cushion layer 204 in part first and the second initial topper cushion layer 214 is in order to complete
The protective layer of full removal first initial topper cushion layer 204 and the second initial 214 top of topper cushion layer, while considering full wafer crystalline substance
Difference when circle etching carries out a certain amount of cross to the first initial topper cushion layer 204 and the second initial topper cushion layer 214 and carves
Erosion, to form the first headliner layer 209 and the second topper cushion layer 219.
The first topper cushion layer 209 and the first back lining bed course 211 collectively form connection liner.
The connection liner is connected between device main body by interconnection structure, and the plant ball work of packaging technology is subsequently used for
In skill.
The second topper cushion layer 219 and the second back lining bed course 212 collectively form test pads.
The test pads are subsequently used for probe test.
Test pads are located in non-device area, when being not take up the spatial area of semiconductor devices, and testing for probe, no
Connection liner can be damaged, connection pad surfaces are in good condition, are conducive to improve the yield in subsequent encapsulation plant ball technique.It visits simultaneously
Needle test carries out in test pads, reduces the probability that particle is formed on connection liner, reduces and damages during planting ball
The probability of semiconductor devices wafer, to improve the performance and yield of semiconductor devices.
Connection liner and test pads separate, and the area for connecting liner need to only meet plant ball technique institute in subsequent encapsulating process
The area design needed does not need to test reserved test area for probe, is conducive to the area for reducing connection liner, complies with
The trend of device size microminiaturization development.
The wire openings 207 expose the atop part surface of conducting wire 220 in back lining bed course 210.
Along being parallel to 200 extending direction of semiconductor substrate and wide perpendicular to wire openings 207 described in 220 extending direction of conducting wire
Degree is greater than the width of conducting wire 220.
Edge is parallel to 200 extending direction of semiconductor substrate and perpendicular to wire openings 207 described in 220 extending direction of conducting wire
Length is 2um.
The wire openings 207 provide opening using laser blown conducting wire 220 to be subsequent, can only need to remove conducting wire
220 both can, do not need additionally to remove coating 220.Simultaneously as foring wire openings 207, lesser laser energy can be used
Amount can fused wire 220, improve efficiency.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method, referring to FIG. 8, including:
Semiconductor substrate 200；The semiconductor substrate 200 includes device region and non-device area, is had in 200 device region of semiconductor substrate
The device main body and interconnection structure being electrically connected to each other；Connection liner, test pads and conducting wire positioned at 200 surface of semiconductor substrate
220, connection liner is connected with interconnection structure, and connection liner is electrically connected with test pads by conducting wire 220, connection liner position
In 200 device region of semiconductor substrate, test pads are located at 200 non-device area of semiconductor substrate；The conducting wire 200 is used in probe
It fuses after test, disconnects connection liner and test pads.
The connection liner includes the first back lining bed course 211, and the first back lining bed course is located at semiconductor substrate 200
In device region top surface, and it is connected with interconnection structure；The test pads include the second back lining bed course 212, and described the
Two back lining bed courses are located in 200 non-device area top surface of semiconductor substrate, the second back lining bed course 212 and the first bottom
Layer laying 211 is electrically connected by conducting wire 220, and the conducting wire 200 also is located in 200 top surface of semiconductor substrate.
The connection liner further includes the first topper cushion layer 209 positioned at 211 surface of the first back lining bed course.
The test pads further include the second topper cushion layer 219 positioned at 212 surface of the second back lining bed course.
The content of the semiconductor substrate 200 with reference to the foregoing embodiments, is no longer described in detail.
The structure of the connection liner and the content of reference by location previous embodiment, are no longer described in detail.
The structure of the test pads and the content of reference by location previous embodiment, are no longer described in detail.
Correspondingly, the present embodiment also provides a kind of method to work using semiconductor devices as shown in Figure 8, such as Fig. 8 to figure
Shown in 10.
Referring to FIG. 8, providing semiconductor devices.
The semiconductor devices is as described in the previous embodiment, and this will not be repeated here.
Fig. 9 and Figure 10 are please referred to, Fig. 9 is the schematic diagram of the section structure of the Figure 10 along M-M1 secant, and Figure 10 is that Fig. 9 is only to show
Semiconductor substrate 200, device main body 201, the semiconductor for connecting liner, test pads, conducting wire 220 and the 5th opening 208
The top view of device carries out probe test to the test pads surface using probe, and the electricity for acquisition device main body is joined
Number；After probe test, fuse the conducting wire, so that the connection substrate and test pads open circuit.
The method of fused wire includes: using conducting wire 220 described in laser blown.
The method of fused wire further include: form wire openings in the coating 202 on 200 device region of semiconductor substrate
207, the wire openings 207 expose the part of the surface of conducting wire 220；After probe test, fused wire 207 bottoms of opening are led
Line 220.
Specifically, carrying out probe test in test pads after forming wire openings 207；After completing probe test, removal
The conducting wire 220 of 207 bottom of wire openings forms the 5th opening 208.
The method for removing the conducting wire 220 of 207 bottom of wire openings includes: to be open using the method fused wire of laser bombardment
The conducting wire 220 of 207 bottoms.
5th 208 bottom-exposeds of opening go out the atop part surface of 200 device region I of semiconductor substrate.
After probe test, fused wire 220 disconnects connection liner and test pads.
5th opening 208 is to have cut off the state after conducting wire 220, and connection liner is not turned on test pads, is avoided
Influence of the test pads to device main body in subsequent encapsulation procedure.Semiconductor substrate 200 is split in extended meeting after simultaneously, forms core
Piece, chip include device main body, connection metal substrate and conducting wire；Chip side wall exposes 220 section of conducting wire, has cut off conducting wire
220, it avoids in subsequent encapsulation procedure, influence of the conducting wire 220 of chip side wall to internal circuit.The present invention realizes probe survey
The test pads tried outside device carry out, after end probe test, cut-off loop, and the mesh that device inside circuit is not interfered with
's.
Semiconductor substrate non-device area II is non-device area, and rear extended meeting is removed with cutting action.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate, the semiconductor substrate include device region and non-device area, are had in the semiconductor substrate device region
The device main body and interconnection structure being electrically connected to each other；
Positioned at connection liner, test pads and the conducting wire of semiconductor substrate surface, connection liner is connected with interconnection structure, connects
Liner and test pads are electrically connected by conducting wire, and connection liner is located at semiconductor substrate device region, and test pads, which are located at, partly to be led
Body substrate non-device area, the conducting wire are used to after probe test fuse, and disconnect connection liner and test pads.
2. semiconductor devices as described in claim 1, which is characterized in that the connection liner includes the first back lining bed course,
The first back lining bed course is located in semiconductor substrate device region top surface, and the first back lining bed course and interconnection structure phase
Connection；The test pads include the second back lining bed course, and the second back lining bed course is located at semiconductor substrate non-device area
In top surface；The conducting wire is located in semiconductor substrate top surface, the second back lining bed course and the first bottom liner
Layer is electrically connected by the conducting wire.
3. semiconductor devices as claimed in claim 2, which is characterized in that the connection liner further includes being located at the first back lining
First topper cushion layer of mat surface.
4. semiconductor devices as claimed in claim 3, which is characterized in that the test pads further include being located at the second back lining
Second topper cushion layer of mat surface.
5. semiconductor devices as claimed in claim 3, which is characterized in that further include: it is located in semiconductor substrate and part the
Coating on one back lining bed course, coating is interior to have the first opening, and the first opening exposes the portion of the first back lining bottom
Divide top surface；The first topper cushion layer in the first opening, the first protective layer at the top of the first top layer substrate layer,
There is third opening in first protective layer.
6. semiconductor devices as claimed in claim 5, which is characterized in that the coating is also located at semiconductor substrate and part
There is the second opening, the second opening exposes the atop part of the second back lining bottom on second back lining bed course, in coating
Surface；The second topper cushion layer in the second opening, the second protective layer at the top of the second top layer substrate layer, second protects
There is the 4th opening in sheath.
7. a kind of working method of semiconductor devices characterized by comprising
The semiconductor devices of one structure as described in claims 1 to 6 any one is provided；
Probe test is carried out to the test pads surface using probe, the electrical parameter for acquisition device main body；
After probe test, fuse the conducting wire, so that the connection substrate and test pads open circuit.
8. the working method of semiconductor devices as claimed in claim 7, which is characterized in that the method for fused wire includes: to adopt
The conducting wire described in laser blown.
9. the working method of semiconductor devices as claimed in claim 7, which is characterized in that the coating also cover described in lead
Line；The method of fused wire includes: that wire openings are formed in the coating on semiconductor substrate device region, the wire openings
Expose the part of the surface of conducting wire；After probe test, the conducting wire of fused wire open bottom.
10. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate includes device region and non-device area, is had in semiconductor substrate device region
The device main body and interconnection structure being electrically connected to each other；
It is respectively formed connection liner, test pads and conducting wire in semiconductor substrate surface, connection liner is connected with interconnection structure,
Connection liner and test pads are electrically connected by conducting wire, and the connection substrate is located at semiconductor substrate device region, the test
Liner is located at semiconductor substrate non-device area；
The conducting wire is used to after probe test fuse, and disconnects connection liner and test pads.
11. the forming method of semiconductor devices as claimed in claim 10, which is characterized in that the connection liner includes first
Back lining bed course, the first back lining bed course are located in semiconductor substrate top surface, and the first back lining bed course and interconnection
Structure is connected；The test pads include the second back lining bed course, the second back lining bed course and the first back lining bed course
It is connected by conducting wire, the second back lining bed course and conducting wire also are located in semiconductor substrate top surface.
12. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that the connection liner further includes position
In the first topper cushion layer of the first bottom liner layer surface；The test pads further include being located at the second bottom liner layer surface
The second topper cushion layer.
13. the forming method of semiconductor devices as claimed in claim 12, which is characterized in that the formation side of the connection liner
Method includes: to form coating on a semiconductor substrate；It forms first in coating on a semiconductor substrate to be open, described first
Opening exposes the atop part surface of the first back lining bed course；
After forming the first opening, the first initial topper cushion layer is formed in first opening；Form the first initial top layer lining
After bed course, the first protective layer is formed in the first initial topper cushion layer surface；After forming the first protective layer, etching removal part the
The initial topper cushion layer of one protective layer and part first forms third opening, first topper cushion in the first protective layer
Layer is located at third open bottom.
14. the forming method of semiconductor devices as claimed in claim 13, which is characterized in that the first initial topper cushion
The forming method of layer includes: to form initial topper cushion material layer in coating and the first opening；Planarize the initial top
Layer cushioning material layer forms the first initial topper cushion layer in the first opening until exposing the top surface of coating.
15. the forming method of semiconductor devices as claimed in claim 12, which is characterized in that the formation side of the test pads
Method includes: that the second opening is formed in semiconductor substrate coating, and second opening exposes the portion of the second back lining bed course
Divide top surface；The second initial topper cushion layer is formed in second opening；In the second initial topper cushion layer surface shape
At the second protective layer；Etching removal the second protective layer of part and the initial topper cushion layer in part second, the shape in the second protective layer
At the 4th opening, the second topper cushion layer is located at the 4th open bottom.
16. the forming method of semiconductor devices as claimed in claim 15, which is characterized in that the second initial topper cushion
The forming method of layer includes: also to form initial topper cushion material layer in the second opening；
The initial topper cushion material layer is planarized, until exposing the top surface of coating, is formed in the second opening
Second initial topper cushion layer.
17. the forming method of semiconductor devices as claimed in claim 16, which is characterized in that the connection liner and test lining
Pad is formed in identical formation process.
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| CN201810179409.2A CN110233140A (en) | 2018-03-05 | 2018-03-05 | Semiconductor devices and forming method thereof and working method |
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| JPH05299466A (en) * | 1991-09-10 | 1993-11-12 | Nec Corp | Structure of semiconductor chip and manufacture thereof |
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