CN110362512B - SCA and SDR-oriented rapid system reconstruction method - Google Patents

Abstract

The invention discloses a rapid system reconstruction method facing SCA and SDR, the system is composed of a main control module and a waveform module, the main control module and the waveform module are interconnected and communicated through a VPX bus of a backboard, a PCIE X45.0GT/s interface is adopted, an X86 hardware platform of the main control module is used as a root component RC of the PCIE interface, a ZYNQ chip of the waveform module is used as PCIE interface terminal equipment EP, wherein the main control module comprises an X86 hardware platform, an operating system, SCA Core Framework (CF), CORBA Middleware (CORBA), SCA Device, POSIX AEP and SCA Applications, the SCA Device comprises a driver of the waveform module, the waveform module comprises ZYNQ series, FPGA7 series, DDR and other chips, the interface between the ZYNQ and the FPGA7 comprises SelectMAP, LVDS, SRIO and the like, and the external memory of the ZYNQ is a large-capacity DDR. The invention comprehensively utilizes the technologies and resources of a high-speed bus, PCIE and SRIO interfaces, DMA, an interrupt mechanism, a large-capacity DDR and the like, and realizes the rapid reconfiguration of the FPGA waveform, the rapid configuration of waveform parameters, the real-time return of waveform states and the high-speed transmission of waveform data.

Description

A Fast System Reconfiguration Method Oriented to SCA and SDR

technical field

The invention relates to the technical field of software communication architecture and software radio, in particular to a fast system reconfiguration method oriented to SCA and SDR.

Background technique

SCA is a standard architecture defined for software radio SDR, which supports the development of SDR communication systems and makes waveform application software easier to port across radio platforms. SCA provides a unique way for waveform software and other elements of software radio to interact with hardware. Through standardization, waveforms are compatible, not just for one platform, but for any device that supports SCA. Waveform software can be used with many different radios, whether handheld or other communication devices.

SCA makes waveform software very portable and reusable by defining the core framework interface and application environment description (AEP). SCA creates SCA domain configuration file elements through a set of XML description files with complex semantics. It is used to identify the functions, attributes, interdependencies and locations of hardware devices and software components in an SCA compliant system. A general SCA system includes three types of chips: GPP, DSP, and FPGA. When system deployment and waveform loading are performed, the GPP, DSP, and FPGA chips in the system need to be reconfigured to complete system reconstruction.

With the continuous expansion of the scale of GPP, DSP, and FPGA chips, their configuration files are getting larger and larger, and the time it takes to complete the configuration has seriously affected the performance of SCA system reconstruction. According to the current research situation, using a single optimization method It can no longer meet the user's time requirements for system reconfiguration, and a comprehensive design must be carried out from the perspective of architecture, interface, and process to achieve rapid system reconfiguration.

Contents of the invention

In order to solve the above-mentioned deficiencies in the prior art, the present invention provides a fast system reconfiguration method facing SCA and SDR, and comprehensively utilizes technologies and resources such as high-speed bus, PCIE and SRIO interface, DMA, interrupt mechanism, and large-capacity DDR to realize Fast reconfiguration of FPGA waveforms, quick configuration of waveform parameters, real-time return of waveform status, and high-speed transmission of waveform data.

In order to achieve the above object, the technical scheme adopted in the present invention is:

A fast system reconfiguration method for SCA and SDR. The system is composed of a main control module and a waveform module. The main control module and the waveform module are interconnected through the VPX bus on the backplane. The X86 hardware platform is used as the root component RC of the PCIE interface, and the ZYNQ chip of the waveform module is used as the terminal equipment EP of the PCIE interface. The main control module includes the X86 hardware platform, operating system, SCA Core Framework (CF), CORBA Middleware (CORBA), SCA Device, POSIX AEP, SCA Applications, SCA Device includes the driver program of the waveform module. The waveform module includes ZYNQ series, FPGA7 series, DDR and other chips. The interface between ZYNQ and FPGA7 includes SelectMAP, LVDS, SRIO, etc. The external memory of ZYNQ is Large capacity DDR.

To further describe the present invention, the waveform module ZYNQ chip internal program includes ZYNQ7 ProcessingSystem (PS), 3 AXI Interconnects, 3 AXI BRAM Controllers, AXI Memory Mapped PCIExpress (M2PCIE), AXI Central Direct Memory Access (CDMA), AXI SelectMAP, DDR, BRAM, data read and write control logic, and interrupt control logic function modules, among which ZYNQ7 Processing System (PS) accesses the address space of M2PCIE, CDMA, SelectMAP, AXI BRAMController1, and data read and write control logic through the M_AXI_GPO interface and AXI Interconnect1 interconnection. AXI Memory Mapped PCI Express (M2PCIE) is interconnected with AXI Interconnect3 through AXI bus to access the address space of DDR, AXI BRAM Controller2, and AXIBRAM Controller3. Among them, AXI Central Direct Memory Access (CDMA) is interconnected with AXI Interconnect2 through AXI bus, and is connected with AXI Interconnect1 and AXI Interconnect3 cascade accesses the address space of M2PCIE, SelectMAP, AXI BRAM Controller1, AXI BRAM Controller3, and data read and write control logic, and realizes access to the DDR address space through the S_AXI_HPO interface of ZYNQ7Processing System (PS), where AXI BRAM Controller1 and AXI BRAM Controller2 is connected to two ports of BRAM respectively, and the main control module accesses the address space of the same BRAM through PCIE interface, PS and AXI bus.

To further describe the present invention, the BAR address of AXI Memory Mapped PCI Express (M2PCIE) maps the address spaces of DDR, AXI BRAM Controller2 and AXI BRAM Controller3 respectively, and directly accesses the above-mentioned three address spaces by the BAR address of PCIE by the main control module.

To further describe the present invention, the PCIE interface of AXI Memory Mapped PCI Express (M2PCIE) is interconnected with the PCIE interface of the main control module, the SelectMAP interface of AXI SelectMAP and FPGA7 is interconnected, the LVDS interface of AXI BRAMController3 and FPGA7 is interconnected, and the data read and write control logic and The SRIO interface of FPGA7 is interconnected, and the PS configures the registers of the data read and write control logic.

The further description of the present invention includes two kinds of interrupt mechanisms, namely main control module PCIE MSI interrupt mechanism and PS interrupt control logic, when ZYNQ sends a specific TLP packet to the main control module through the PCIE interface, it will trigger the MSI interrupt of the main control module PCIE , the corresponding interrupt service program will clear the interrupt. When the main control module writes data to the specific address of ZYNQ’s AXI BRAM Controller2 through the PCIE interface, the PS interrupt control logic will trigger the PS interrupt. When data is read from a specific address, the PS interrupt control logic will clear the PS interrupt.

The further description of the present invention includes two data flow directions, namely the downstream data flow from the main control module to ZYNQ or FPGA7 and the upstream data flow from ZYNQ or FPGA7 to the main control module.

Further description of the present invention, BRAM comprises two special 32-bit registers, is respectively the control status register (address is 0) of main control and the control status register (address is 4) of PS, is used for control, status information in the system Exchange, the register defines completion flag (1 bit), read/write flag (1 bit), control command (6 bits), data type (8 bits), and data length (16 bits) by bit.

A further description of the present invention includes 4 types of data, which are respectively FPGA7BIT files, parameter files, waveform parameters and state data, waveform input and output data;

The further description of the present invention includes 6 kinds of data processing flows, which are respectively configuring FPGA7 chip BIT files, configuring parameter files, configuring waveform parameters, reading waveform status, inputting waveform data, and outputting waveform data.

The present invention is described further, wherein FPGA7 chip BIT file flow process comprises the following steps:

(101): The PS has completed the system initialization and is in the state of waiting for the interrupt to be triggered. The SCA device driver of the main control module opens the FPGA7 BIT file, and writes the file data into the PCIE BAR0 address space, and writes the data through the BAR address mapping of the M2PCIE module Input the DDR of the waveform module;

(102): The main control module driver writes the written data length, data type (FPGA BIT file), control command (configuration FPGA), read/write flag (write), and completion flag (Y) to the address of PCIE BAR1 0 register (the control status register of the main control, which is actually the 32-bit space of address 0 of the BRAM), enters the MSI interrupt trigger state waiting for PCIE; the operation of the driver writing the control status register of the main control will prompt the interrupt control logic module Trigger the PS interrupt, and the PS interrupt service program will read the register (32 bits) of BRAM address 0 through AXI BRAM Controller1 to obtain the file data length, data type, control command, read/write flag and completion flag, and at the same time, the logic module will be controlled by the interrupt Clear the interrupt bit, the interrupt service program reads the file data in the DDR by configuring the CDMA module to start DMA, and saves it in the Linux file system;

(103): The program of PS writes the read data length, read/write flag (read), completion flag (Y) into the register of AXIBRAM Controller1 address 4 (the control state register of PS is actually the address 4 of BRAM 32-bit space), and write the MSI interrupt TLP packet to the PCIE interface through the M2PCIE module, the packet will trigger the main control PCIE MSI interrupt and run the PCIE interrupt service program, the PCIE interrupt service program clears the interrupt bit, and reads the PCIE BAR1 The register at address 4 (actually the 32-bit space of address 4 of BRAM) obtains the relevant information set by the PS program, and the PS program enters the interrupt trigger state again after writing the register;

(104): After the downloading of the BIT file, the main control module driver program writes the command of configuring the FPGA into the control state register of the main control, including configuration file name and sign; the interrupt control logic module triggers the PS interrupt at the same time, and the interrupt service program again Read the control status register of the main control, obtain the parameters for configuring FPGA7, then open the BIT file of FPGA7, start DMA to write file data to the AXI SelectMAP module, and check the sign of successful FPGA configuration;

(105): The program of the PS writes the configuration result into the control status register of the PS, including the flag status parameter of whether the configuration FPGA is successful, and writes the TLP packet of the MSI interrupt to the PCIE interface through the M2PCIE module to trigger the main control PCIE MSI interrupt, and the main control The PCIE interrupt service program clears the interrupt bit and reads the control status register of the PS to obtain the FPGA configuration status parameters, so far the configuration of the FPGA7 BIT file ends;

The waveform data input process includes the following steps:

(201): The PS has completed the system initialization and is in the state of waiting for the interrupt trigger. The SCA device driver of the main control module opens the waveform input file and writes the file data into the PCIE BAR0 address space. In fact, the data is directly written into the waveform module. in the DDR;

(202): The main control module driver writes the written data length, data type (waveform data file), control command (data input), read/write flag (write), and completion flag (Y) into the address of PCIE BAR1 0 register (the control status register of the main control), enter the MSI interrupt trigger state waiting for PCIE; the operation of the driver program writing the control status register of the main control will prompt the interrupt control logic module to trigger the PS interrupt, and the interrupt service program of the PS will pass AXI BRAMController1 reads the register (32 bits) of BRAM address 0 to obtain the file data length, data type, control command, read/write flag and completion flag, and at the same time, the interrupt control logic module clears the interrupt bit, and the interrupt service program sets the data read and write logic Control the register of the module, after setting the data direction, length, and whether to cycle the flag, start the DMA mode by configuring the CDMA module to read the file data in the DDR, and send it to the SRIO interface of the data read and write control logic module (input to the waveform);

(203): The program of PS writes the data length that has read, read/write sign (reading), completion sign (Y) into the register (the control state register of PS) that AXIBRAMController1 address is 4, and sends to PCIE by M2PCIE module The interface writes the TLP packet of MSI interrupt, which will trigger the main control PCIE MSI interrupt and run the PCIE interrupt service program, the PCIE interrupt service program clears the interrupt bit, and reads the register of address 4 of PCIE BAR1 to obtain the relevant information set by the PS program;

(204): The read-write control logic module judges the cyclic read-write flag. If it is cyclic writing, start the DMA mode to read the data in the DDR after writing the data and send it to the waveform through SRIO until the loop write is exited, and the input waveform data process Finish;

The waveform data output process includes the following steps:

(301): The PS has completed the system initialization and is in the state of waiting for the interrupt to be triggered. The SCA device driver of the main control module starts the process of reading the waveform output data, and will read the data length, data type (waveform data file), control command (data output), read/write flag (read), and completion flag (N) are written into the register of address 0 of PCIE BAR1 (the control status register of the main control), and enter the MSI interrupt trigger state waiting for PCIE;

(302): The operation of the driver program writing the control status register of the main control will prompt the interrupt control logic module to trigger the PS interrupt, and the interrupt service program of the PS will read the register (32 bits) of BRAM address 0 through AXI BRAM Controller1 to obtain the file data length , data type, control command, read/write flag and completion flag, and at the same time, the interrupt control logic module clears the interrupt bit, the interrupt service program sets the register of the data read and write logic control module, and after setting the data direction, length, and whether to loop the flag, start Data read and write logic control read data from SRIO interface to DDR;

(303): The program of PS writes the data length, read/write sign (reading), completion sign (Y) into AXIBRAM Controller1 address to be 4 registers (the control state register of PS) by the program of PS, and send to by M2PCIE module The PCIE interface writes the TLP packet of the MSI interrupt, which will trigger the main control PCIE MSI interrupt and run the PCIE interrupt service program, the PCIE interrupt service program clears the interrupt bit, and reads the register of address 4 of PCIE BAR1 to obtain the relevant information set by the PS program ;

(304): The driver starts the DMA mode to read the waveform output data in PCIE BAR0 (DDR), and judges the cyclic read and write flag. If it is a cyclic read, it starts the DMA mode to read the data in PCIE BAR0 after reading the data, until it exits the loop Read until the process of outputting waveform data ends.

Compared with the prior art, the present invention has the advantages of comprehensively utilizing high-speed bus, PCIE and SRIO interfaces, DMA, interrupt mechanism, large-capacity DDR and other technologies and resources to realize fast reconfiguration of FPGA waveforms, rapid configuration of waveform parameters, and real-time waveform status High-speed transmission of backhaul and waveform data.

Description of drawings

Fig. 1 is a system architecture diagram of the method of the present invention.

Fig. 2 is the connection diagram of ZYNQ internal function modules of the method of the present invention.

Figure 3 is a flow chart of configuring the FPGA7 BIT file.

Figure 4 is a flow chart of configuring waveform parameters and reading waveform status.

Figure 5 is a flow chart of waveform data input.

Figure 6 is a flow chart of waveform data output.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Example 1:

As shown in Figure 1, the verification system of the present invention is composed of two modules, the main control module and the waveform module, and realizes interconnection and intercommunication through the VPX bus of the backplane, adopts PCIE interface and is configured as X4 5.0GT/s.

The main control module includes the hardware platform of X86 architecture, running the operating system and SCA's core framework CF, CORBA middleware and SCA's waveform application, POSIX compatible application program environment description AEP provides a standard application program function interface for SCA's waveform application API, Device under the control of the SCA device manager provides driver and proxy functions for the FPGA7 chip in the waveform module, the driver implements the access interface to each hardware resource in the waveform module, and the agent implements the SCA management interface for the device, including device initialization (initializ ), load program (load), run program (execute), configuration parameter (configure), query status (query), terminate program (terminate), unload program (unload), release object (releaseObject), etc. The X86 hardware platform includes the root component RC of the PCIE interface, which realizes the communication and configuration with the PCIE interface of the waveform module.

Waveform modules mainly include ZYNQ series and FPGA 7 series FPGA chips, large-capacity DDR chips, etc. The interface between ZYNQ and FPGA7 mainly includes SelectMAP, LVDS, SRIO, etc. SelectMAP interface realizes ZYNQ’s waveform reconfiguration of FPGA7 chip, differential LVDS interface realizes ZYNQ’s waveform parameter configuration and waveform status query of FPGA7 chip, and SRIO interface is used as waveform data The input and output interface communicates with the PCIE interface of the main control module through the PCIE interface terminal equipment EP of ZYNQ. DDR is used as a dump device for data and large files, and is mapped to BAR0 of the PCIE interface of the main control module through the PCIE interface of ZYNQ.

The functional modules and connection relationship inside ZYNQ are shown in Figure 2, mainly including PS (ZYNQ7 Processing System), bus interconnection module (AXI Interconnect), block memory controller (AXI BRAM Controller), M2PCIE memory mapping module (AXI Memory Mapped PCI Express ), CDMA module (AXI Central DirectMemory Access), SelectMAP interface module (AXI SelectMAP), DDR, BRAM, data read and write control logic module, interrupt control logic module.

When designing, first configure the system parameters of the PS, including configuring DDR parameters, setting parameters such as GPO (M_AXI_GPO) interface, HPO (S_AXI_HPO) interface bit width, and interrupt triggering parameters; secondly, add each function module to the project, and then connect each function The interface of the module is configured with corresponding parameters. In this embodiment, the width of the AXI bus is 32 bits. The PS is connected to the AXI bus slave port of AXIInterconnect1 through the main port M_AXI_GPO of GPO, and connected to the AXI bus master port of AXI Interconnect2 through the slave port of HPO, and the output of the interrupt control logic is connected to the interrupt request of PS (corresponding to PL to PS interrupt number); The AXI bus master port of AXI Interconnect1 is respectively connected to the AXI bus slave ports of the 5 modules of CDMA, M2PCIE, AXI BRAMController1, AXI SelectMAP, and data read and write control logic, and supports PS access to 5 module address spaces. The PCIE interface of the M2PCIE module is interconnected with the PCIE interface of the main control module through the VPX bus, the AXI bus master port is connected with the AXI bus slave port of AXI Interconnect3, and the AXI bus master port of AXI Interconnect3 is respectively connected with DDR, AXI BRAM Controller2, and AXI BRAM Controller3 The AXI bus is connected from the port, configure the M2PCIE module parameters, the channel is X4, the bandwidth rate is 5.0GT/s, and the three BAR addresses are respectively mapped to the address spaces of DDR, AXI BRAM Controller2, and AXI BRAM Controller3, so that the main control module can be accessed through the PCIE interface. Directly access the address space of DDR, AXI BRAM Controller2, AXI BRAM Controller3. The AXI bus master port of the CDMA module is connected to the AXI bus slave port of AXI Interconnect2, and the AXI bus master port of AXI Interconnect2 is cascaded with AXI Interconnect1 and AXI Interconnect3, and is connected with the HPO slave port of PS to realize CDMA to DDR, M2PCIE, SelectMAP, AXI BRAM Controller1, AXI BRAM Controller3, data read and write control access to the address space of the logic module. The AXI SelectMAP module is directly connected to the FPGA7 through the SelectMAP interface, the AXIBRAM Controller3 module is connected to the FPGA7 through the LVDS interface, and the data read and write control logic module is connected to the FPGA7 through the SRIO interface. The two ports of BRAM are respectively connected to AXI BRAM Controller1 and AXI BRAM Controller2, so that the main control module accesses the address space of the same BRAM through the PCIE interface and the PS through the AXI bus, and the first 8 bytes in the BRAM are used as the control status register of the main control module and

Configuring the FPGA7BIT file through the SelectMAP module is divided into two stages. The first stage is to download the BIT file, and the second stage is to configure the FPGA; the entire configuration process requires the cooperation of the SCA device driver of the main control module and the program in the PS. The detailed steps are as follows: As shown in Figure 3:

Step 1: PS has completed the system initialization and is in the state of waiting for interrupt triggering. The SCA device driver of the main control module opens the FPGA7BIT file and writes the file data into the PCIE BAR0 address space. In fact, through the BAR address mapping of the M2PCIE module, the data It is directly written into the DDR of the waveform module;

Step 2: The main control module driver writes the written data length, data type (FPGA BIT file), control command (configure FPGA), read/write flag (write), and completion flag (Y) to the address of PCIE BAR1 0 register (the control status register of the main control, which is actually the 32-bit space of address 0 of the BRAM), enters the MSI interrupt trigger state waiting for PCIE; the operation of the driver writing the control status register of the main control will prompt the interrupt control logic module Trigger the PS interrupt, the PS interrupt service program will read the register (32 bits) of BRAM address 0 through AXI BRAM Controller1 to obtain the file data length, data type, control command, read/write flag and completion flag, etc., and the interrupt control logic The module clears the interrupt bit, and the interrupt service program reads the file data in the DDR by configuring the CDMA module to start DMA, and saves it in the Linux file system;

Step 3: The PS program writes the read data length, read/write flag (read), completion flag (Y), etc. into the register of AXIBRAM Controller1 whose address is 4 (the control status register of PS is actually the address of BRAM 4’s 32-bit space), and write the MSI interrupt TLP packet to the PCIE interface through the M2PCIE module, the packet will trigger the main control PCIE MSI interrupt and run the PCIE interrupt service program, the PCIE interrupt service program clears the interrupt bit, and reads the PCIE BAR1 The register of address 4 (actually the 32-bit space of address 4 of BRAM) obtains the relevant information set by the PS program, and the PS program enters the waiting interrupt trigger state again after writing the register;

Step 4: After the main control module driver finishes downloading the BIT file, write the command to configure the FPGA into the control status register of the main control, including the configuration file name, flag, etc.; at the same time, the interrupt control logic module triggers the PS interrupt, and the interrupt service program Read the control status register of the main control again, obtain the parameters for configuring FPGA7, then open the BIT file of FPGA7, start DMA to write file data to the AXI SelectMAP module, and check the sign of FPGA configuration success;

Step 5: The program of the PS writes the configuration result into the control status register of the PS, including parameters such as the flag status of whether the FPGA configuration is successful, and writes the MSI interrupt TLP packet to the PCIE interface through the M2PCIE module to trigger the main control PCIE MSI interrupt. The PCIE interrupt service program of the control clears the interrupt bit and reads the control status register of the PS to obtain parameters such as the FPGA configuration status, and the configuration of the FPGA7BIT file ends.

The BAR2 of the main control module PCIE maps the address space of the AXI BRAM Controller3 through the M2PCIE module, and configures the waveform parameters and reads the waveform form through the LVDS interface. The detailed process is shown in Figure 4:

The SCA device driver of the main control module first opens the waveform parameter file, and then writes the address into the BAR2 address space through the PCIE interface. The AXI BRAM Controller3 module then outputs the clock, address, parameter data, and write enable signal to the LVDS interface, and the driver completes the configuration. Waveform parameters;

The main control module SCA device driver reads the waveform shape, first reads the BAR2 address space through the PCIE interface according to the address, and the AXI BRAM Controller3 module then outputs the clock, address, and read enable signal to the LVDS interface, and returns when the next rising edge of the clock arrives The value corresponding to the parameter address is given to the PCIE interface, and the driver completes reading the waveform state.

The BAR0 of the main control module PCIE maps the DDR address space through the M2PCIE module, and the SCA device driver implements waveform data input by writing to the BAR0 address space of the PCIE interface. The detailed process is shown in Figure 5:

Step 1: PS has completed the system initialization and is waiting for an interrupt trigger. The SCA device driver of the main control module opens the waveform input file and writes the file data into the PCIE BAR0 address space. In fact, the data is directly written into the waveform module. in the DDR;

Step 2: The main control module driver writes the written data length, data type (waveform data file), control command (data input), read/write flag (write), and completion flag (Y) into the address of PCIE BAR1 0 register (the control status register of the main control), enter the MSI interrupt trigger state waiting for PCIE; the operation of the driver program writing the control status register of the main control will prompt the interrupt control logic module to trigger the PS interrupt, and the interrupt service program of the PS will pass AXI BRAMController1 reads the register (32 bits) of BRAM address 0 to obtain the file data length, data type, control command, read/write flag and completion flag, etc. At the same time, the interrupt control logic module clears the interrupt bit, and the interrupt service program sets the data read and write The register of the logic control module, after setting the data direction, length, whether to cycle and other signs, read the file data in the DDR by configuring the CDMA module to start the DMA mode, and send it to the SRIO interface of the data read and write control logic module (input to the waveform);

Step 3: The PS program writes the read data length, read/write flag (read), completion flag (Y), etc. into the AXIBRAM Controller1 address 4 register (PS control status register), and through the M2PCIE module Write the TLP package of MSI interrupt to the PCIE interface, the package will trigger the main control PCIE MSI interrupt and run the PCIE interrupt service program, the PCIE interrupt service program clears the interrupt bit, and reads the register of address 4 of PCIE BAR1 to obtain the relevant information set by the PS program information;

Step 4: The read-write control logic module judges the cyclic read-write flag. If it is cyclic writing, start the DMA mode to read the data in the DDR after writing the data and send it to the waveform through SRIO until the cyclic writing is exited, and the input waveform data process Finish.

The SCA device driver implements waveform data output by reading from the PCIE interface BAR0 address space. The detailed process is shown in Figure 6:

Step 1: The PS has completed the system initialization and is in the state of waiting for the interrupt trigger. The SCA device driver of the main control module starts the process of reading the waveform output data, and the data length, data type (waveform data file), control command (data output), read/write flag (read), and completion flag (N) are written into the register of address 0 of PCIE BAR1 (the control status register of the main control), and enter the MSI interrupt trigger state waiting for PCIE;

Step 2: The operation of the driver program to write the control status register of the main control will prompt the interrupt control logic module to trigger the PS interrupt, and the interrupt service program of the PS will read the register (32 bits) of BRAM address 0 through AXI BRAM Controller1 to obtain the file data length , data type, control command, read/write flag and completion flag, etc., and the interrupt control logic module clears the interrupt bit at the same time. , Start the data read and write logic control to read data from the SRIO interface and send it to DDR;

Step 3: The PS program writes the read data length, read/write flag (read), completion flag (Y), etc. into the AXIBRAM Controller1 address 4 register (PS control status register), and through the M2PCIE module Write the TLP package of MSI interrupt to the PCIE interface, the package will trigger the main control PCIE MSI interrupt and run the PCIE interrupt service program, the PCIE interrupt service program clears the interrupt bit, and reads the register of address 4 of PCIE BAR1 to obtain the relevant information set by the PS program information;

Step 4: The driver starts the DMA mode to read the waveform output data in PCIE BAR0 (DDR), and judges the cyclic read and write flag. If it is a cyclic read, start the DMA mode to read the data in PCIE BAR0 after reading the data, until it exits the loop Read until the process of outputting waveform data ends.

In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the level of the first feature is higher than that of the second feature, the first "Below" and "under" the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is less horizontally than the first feature.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "examples", "specific examples" or "some examples" mean specific features, structures, materials described in connection with the embodiments or examples. Or features are included in at least one embodiment or example of the invention, in this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limitations to the present invention. Variations, modifications, substitutions, and modifications to the above-described embodiments are possible within the scope of the present invention.

Claims (6)

1. A rapid system reconstruction method facing SCA and SDR is characterized in that the system is composed of a main control module and a waveform module, the main control module and the waveform module are interconnected and communicated through a VPX bus of a backboard, an interface adopts PCIE X4.0 GT/S, an X86 hardware platform of the main control module is used as a root component RC of a PCIE interface, a ZYNQ chip of the waveform module is used as PCIE interface terminal equipment EP, the main control module comprises SCA Device components, each SCA Device component is a logic abstraction of one waveform module and comprises a driving program of the waveform module, the internal program of the waveform module ZYNQ chip comprises ZYNQ7Processing System, 3 AXI interfaces, 3 AXI BRAM Controller, AXI Memory Mapped PCI Express, AXI Central Direct Memory Access, AXI select MAP, DDR, BRAM, data read-write control logic and interrupt control logic function modules, the ZYNQ7Processing System is interconnected with AXI Internect 1 through an M_AXI_GPO interface to access AXI Memory Mapped PCI Express, AXI Central Direct Memory Access, AXI SelectMAP, AXI BRAM Controller1 and address space of data read-write control logic, AXI Memory Mapped PCI Express is interconnected with AXI Internect 3 through an AXI bus to access DDR, AXI BRAM Controller2 and AXI BRAM Controller3, AXI Central Direct Memory Access is interconnected with AXI Internect 2 through an AXI bus and is connected with AXI Internect 1 and AXI Internect 3 in cascade to access AXI Memory Mapped PCI Express, AXI SelectMAP, AXI BRAM Controller1, AXI BRAM Controller3 and address space of data read-write control logic, access to DDR address space is realized through an S_AXI_HPO interface of ZYNQ7Processing System, AXI BRAM Controller and AXI BRAM Controller are respectively connected with two ports of BRAM, and the master control module is connected with address space of the same BRAM through a PCIE interface, ZYNQ7Processing System and the AXI bus; also included are 4 data types that are of a type, respectively an FPGA7BIT file, a parameter file, waveform parameters, state data and waveform input and output data; the 6 data processing flows are respectively a flow for configuring a BIT file, a configuration parameter file, a configuration waveform parameter, a waveform reading state, waveform data input and waveform data output of the FPGA7 chip;

the process for configuring the BIT file of the FPGA7 chip comprises the following steps of:

(101): ZYNQ7PROCESSING SYSTEM has completed the system initialization in the state of waiting for interrupt triggering, the SCA device driver of the main control module opens the FPGA7BIT file, writes the file data into PCIE BAR0 address space, and writes the data into the DDR of the waveform module through the BAR address mapping of the AXI Memory Mapped PCI Express module;

(102): the master control module driver writes the written data length, the data type of the FPGA BIT file, the control command of the configuration FPGA, the writing mark and the finishing mark of 'Y' into a master control state register of which the address is 0 of PCIE BAR1, wherein the register is actually positioned in a 32-BIT space of address 0 of BRAM and enters an MSI interrupt triggering state waiting for PCIE; the operation of the control state register of the driver program writing master control causes the interrupt control logic module to trigger ZYNQ7PROCESSING SYSTEM to interrupt, the interrupt service program of ZYNQ7PROCESSING SYSTEM obtains the file data length, the data type, the control command, the read/write mark and the completion mark by reading the 32-bit register of BRAM address 0 through AXI BRAM Controller1, meanwhile, the interrupt control logic module clears the interrupt bit, and the interrupt service program reads the file data in DDR through a DMA mode started by the configuration AXI Central Direct Memory Access module and stores the file data in a Linux file system;

(103): the program of ZYNQ7PROCESSING SYSTEM writes the read data length, the read flag and the completion flag representing 'Y' into a control state register of ZYNQ7PROCESSING SYSTEM with address 4 of AXI BRAM Controller, wherein the register is actually located in a 32-bit space of address 4 of BRAM, writes a TLP packet of MSI interrupt to a PCIE interface through AXI Memory Mapped PCI Express module, the packet triggers PCIE MSI interrupt and runs a PCIE interrupt service routine, the PCIE interrupt service routine clears interrupt bit, reads a control state register of ZYNQ7PROCESSING SYSTEM with address 4 of PCIE BAR1, is actually located in a 32-bit space of address 4 of BRAM, acquires relevant information set by the ZYNQ7PROCESSING SYSTEM, and enters a trigger state to be interrupted again after the program of ZYNQ7PROCESSING SYSTEM writes the register;

(104): after the host module driver finishes downloading the BIT file, writing a command for configuring the FPGA into a control state register of the host, wherein the control state register comprises a configuration file name and a mark; meanwhile, the interrupt control logic module triggers ZYNQ7PROCESSING SYSTEM to interrupt, an interrupt service routine reads a control state register of the main control to acquire parameters configuring the FPGA7, then a BIT file of the FPGA7 is opened, DMA is started to write file data into the AXI select MAP module, and a mark that the configuration of the FPGA is successful is checked;

(105): the program of ZYNQ7PROCESSING SYSTEM writes configuration results into a control state register of ZYNQ7PROCESSING SYSTEM, wherein the configuration results comprise flag state parameters of whether the configuration of the FPGA is successful or not, a TLP packet of MSI interrupt is written into a PCIE interface through a AXI Memory Mapped PCI Express module to trigger PCIE MSI interrupt to be controlled, a PCIE interrupt service routine of the main control clears interrupt BITs and reads the control state register of ZYNQ7PROCESSING SYSTEM to obtain the configuration state parameters of the FPGA, and the configuration of the FPGA7BIT file is finished;

the waveform data input flow comprises the following steps:

(201): ZYNQ7PROCESSING SYSTEM has completed the system initialization in the state of waiting for interrupt triggering, the SCA device driver of the main control module opens the waveform input file and writes the file data into PCIE BAR0 address space, in fact, the data is directly written into DDR of the waveform module;

(202): the master control module driver writes the written data length, the data type representing the waveform data file, the control command representing the data input, the writing mark and the finishing mark representing 'Y' into the master control state register of address 0 of PCIE BAR1, and enters the MSI interrupt triggering state waiting for PCIE; the operation of the control state register of the driver program writing master control causes the interrupt control logic module to trigger ZYNQ7PROCESSING SYSTEM to interrupt, the interrupt service program of ZYNQ7PROCESSING SYSTEM obtains the file data length, the data type, the control command, the read/write mark and the completion mark by reading the 32-bit register of BRAM address 0 through AXI BRAM Controller1, meanwhile, the interrupt control logic module clears the interrupt bit, the interrupt service program sets the register of the data read/write logic control module, after the data direction, the length and the cycle mark are set, the data read/write logic module is started to read the file data in the DDR through the configuration AXI Central Direct Memory Access module, and the data is sent to the SRIO interface of the data read/write control logic module to realize the data input to waveforms;

(203): the program of ZYNQ7PROCESSING SYSTEM writes the read data length, the read flag and the completion flag representing 'Y' into a AXI BRAM Controller control status register of ZYNQ7PROCESSING SYSTEM with address 4, writes a TLP packet of MSI interrupt to a PCIE interface through a AXI Memory Mapped PCI Express module, triggers PCIE MSI interrupt to be controlled and runs a PCIE interrupt service routine, clears interrupt bit by the PCIE interrupt service routine, reads a register with address 4 of PCIE BAR1 and acquires related information set by the ZYNQ7PROCESSING SYSTEM program;

(204): the read-write control logic module judges a cyclic read-write mark, if the cyclic write mark is cyclic write, the DMA mode is started to read data in the DDR after the data is written, the data is sent to the waveform through the SRIO until the cyclic write is exited, and the process of inputting the waveform data is ended;

the waveform data output flow comprises the following steps:

(301): ZYNQ7PROCESSING SYSTEM is in a state of waiting for interrupt triggering after completing system initialization, the SCA device driver of the main control module starts a waveform output data reading process, writes a to-be-read data length, a waveform data file data type, a data output control command, a reading mark and an 'N' completion mark into a control state register of the main control of address 0 of PCIE BAR1, and enters an MSI interrupt triggering state of waiting for PCIE;

(302): the operation of the control state register of the driver write master control causes the interrupt control logic module to trigger ZYNQ7PROCESSING SYSTEM to interrupt, the interrupt service program of ZYNQ7PROCESSING SYSTEM acquires the file data length, the data type, the control command, the read/write mark and the completion mark by reading the 32-bit register of BRAM address 0 through AXI BRAM Controller1, meanwhile, the interrupt control logic module clears the interrupt bit, the interrupt service program sets the register of the data read/write logic control module, and after the data direction, the length and the cycle mark are set, the data read/write logic control is started to read data from the SRIO interface to DDR;

(303): the program of ZYNQ7PROCESSING SYSTEM writes the read data length, the read flag and the completion flag representing 'Y' into a AXI BRAM Controller control status register of ZYNQ7PROCESSING SYSTEM with address 4, writes a TLP packet of MSI interrupt to a PCIE interface through a AXI Memory Mapped PCI Express module, triggers PCIE MSI interrupt to be controlled and runs a PCIE interrupt service routine, clears interrupt bit by the PCIE interrupt service routine, reads a register with address 4 of PCIE BAR1 and acquires related information set by the ZYNQ7PROCESSING SYSTEM program;

(304): the driver program starts the DMA mode to read PCIE BAR0, namely waveform output data in DDR, judges a cycle read-write mark, if the cycle read is completed, starts the DMA mode to read the data in PCIE BAR0 again after the data is read, and ends the process of outputting waveform data until the cycle read is exited.

2. The rapid system reconstruction method for SCA and SDR of claim 1 wherein the BAR addresses of AXI Memory Mapped PCI Express map the address spaces of DDR, AXI BRAM Controller, and AXI BRAM Controller3, respectively, and three address spaces of DDR, AXI BRAM Controller2, and AXI BRAM Controller3 are accessed directly by the master control module through the BAR addresses of PCIE.

3. The rapid system reconstruction method for SCA and SDR according to claim 1, wherein a PCIE interface of AXI Memory Mapped PCI Express is interconnected with a PCIE interface of a main control module, AXI SelectMAP is interconnected with an AXI SelectMAP interface of FPGA7, AXI BRAM Controller3 is interconnected with an LVDS interface of FPGA7, data read-write control logic is interconnected with an SRIO interface of FPGA7, and ZYNQ7PROCESSING SYSTEM configures registers of the data read-write control logic.

4. The rapid system reconfiguration method for SCA and SDR according to claim 1, comprising two interrupt mechanisms, namely a main control module PCIE MSI interrupt mechanism and a ZYNQ7PROCESSING SYSTEM interrupt control logic, wherein when the ZYNQ sends a specific TLP packet to the main control module through a PCIE interface, the MSI interrupt of the main control module PCIE will be triggered, the corresponding interrupt service routine will clear the interrupt, when the main control module writes data to a specific address of AXI BRAM Controller of the ZYNQ through the PCIE interface, the ZYNQ7PROCESSING SYSTEM interrupt control logic will trigger the ZYNQ7PROCESSING SYSTEM interrupt, and when the ZYNQ7PROCESSING SYSTEM reads data from a specific address of AXI BRAM Controller1 through an AXI bus, the ZYNQ7PROCESSING SYSTEM interrupt control logic will clear the ZYNQ7PROCESSING SYSTEM interrupt.

5. The rapid system reconstruction method for SCA and SDR according to claim 1, comprising two data streams, namely downstream from the master control module to the ZYNQ or FPGA7 and upstream from the ZYNQ or FPGA7 to the master control module.

6. The rapid system reconfiguration method for SCA and SDR according to claim 1, wherein BRAM includes two special 32-bit registers, a master control status register and a control status register of ZYNQ7PROCESSING SYSTEM, respectively, for control in the system, exchange of status information, the registers being defined by bits: a 1-bit completion flag, a 1-bit read/write flag, a 6-bit control command, an 8-bit data type, a 16-bit data length.

Images