CN110363301A - Quantum circuit processing method, device, storage medium and electronic device - Google Patents

Abstract

The invention discloses a quantum circuit processing method, device, storage medium and electronic device. Wherein, the method includes: when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by the single quantum logic gate, storing the control bit of the double quantum logic gate into a preset variable; The double quantum logic gate with the number of bits greater than or equal to 1 is decomposed to obtain the quantum logic gate with the number of control bits less than 1; the target quantum circuit is output, wherein the target quantum circuit includes the quantum logic gate with the number of control bits less than 1, and the target quantum The line supports the quantum chip instruction set. The invention solves the technical problem that the conversion of the two-bit logic gate of the quantum circuit cannot be realized in the related art.

Description

Quantum circuit processing method, device, storage medium and electronic device

This application claims the priority of the Chinese patent application with the application number 201810872386.3 and the title of the invention "quantum circuit processing method, device, storage medium and electronic device" submitted to the China Patent Office on August 02, 2018, the entire content of which is passed References are incorporated in this application.

technical field

The present invention relates to the communication field, in particular, to a quantum circuit processing method, device, storage medium and electronic device.

Background technique

The instruction set of a quantum chip is the collection of quantum operations supported by a quantum chip or qubit. It contains the collection of single-qubit logic gates supported by qubits, the collection of two-bit quantum logic gates, and the connection information of qubits on the quantum chip.

In actual quantum programming, the representation of quantum logic gates is often highly parameterized, which means that similar quantum logic gates may not belong to the instruction set supported by the qubit. In the related art, it is possible to decompose any single-bit logic gate into a set composed of H, S, and T gates. But it does not break down the scheme of two-bit gates or other more complex (greater than 2 qubit) quantum logic gate schemes. The conversion of two-bit logic gates to quantum circuits cannot be realized.

For the above problems, no effective solution has been proposed yet.

Contents of the invention

Embodiments of the present invention provide a quantum circuit processing method, device, storage medium and electronic device, to at least solve the technical problem in the related art that the two-bit logic gate of the quantum circuit cannot be converted.

According to an aspect of an embodiment of the present invention, a processing method for a quantum circuit is provided, including: when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by a single quantum logic gate, converting the double quantum logic gate The control bit of the gate is stored in a preset variable; the double quantum logic gate with a control bit number greater than or equal to 1 in the preset variable is decomposed to obtain a quantum logic gate with a control bit number less than 1; the target quantum circuit is output, wherein , the target quantum circuit includes the quantum logic gate whose control bit number is less than 1, and the target quantum circuit supports a quantum chip instruction set.

Optionally, before storing the control bit of the double quantum logic gate into the preset variable, the method further includes: converting the quantum logic gate in the quantum circuit to be converted, wherein the converted quantum logic Gates include dual quantum logic gates and single quantum logic gates.

Optionally, converting the quantum logic gate in the quantum circuit to be converted includes: decomposing the form of the quantum logic gate into all The combination form of the double quantum logic gate and the single quantum logic gate.

Optionally, decomposing the double quantum logic gates with the number of control bits greater than or equal to 1 in the preset variable to obtain the quantum logic gate with the number of control bits less than 1, including: traversing the number of control bits in the preset variable greater than 1 or a double quantum logic gate equal to 1; using a preset decomposition algorithm to decompose the double quantum logic gate with a control bit number greater than 1 in the preset variable, to obtain a quantum logic gate with a control bit number less than 1.

Optionally, the quantum logic gate includes: an operation matrix, a control bit, and a transpose conjugate mark.

Optionally, the quantum chip instruction set includes: the connection graph of the quantum chip, the single-bit operation supported by each vertex in the connection graph of the quantum chip; the dual operation supported by each edge in the connection graph of the quantum chip bit manipulation.

According to another embodiment of the present invention, there is also provided a quantum circuit processing device, including: a memory module, which is used to store The control bits of the double-quantum logic gate are stored in preset variables; the decomposition module is used to decompose the double-quantum logic gates whose number of control bits is greater than or equal to 1 in the preset variable to obtain the number of control bits less than 1 A quantum logic gate; an output module, configured to output a target quantum circuit, wherein the target quantum circuit includes the quantum logic gate whose control bit number is less than 1, and the target quantum circuit supports a quantum chip instruction set.

Optionally, the device further includes: a conversion module, configured to convert the quantum logic gate in the quantum circuit to be converted before storing the control bit of the double quantum logic gate into the preset variable, wherein, The converted quantum logic gates include double quantum logic gates and single quantum logic gates.

Optionally, the conversion module includes: a first decomposition unit, configured to decompose the form of the quantum logic gate into the form of the quantum logic gate when the form of the quantum logic gate is larger than the form of the double quantum logic gate Combination forms of double quantum logic gates and said single quantum logic gates.

Optionally, the decomposition module includes: a traversal unit for traversing the double quantum logic gates whose control bit number is greater than 1 or equal to 1 in the preset variable; a second decomposition unit for decomposing the The double quantum logic gate with the number of control bits greater than 1 in the preset variable is obtained to obtain the quantum logic gate with the number of control bits less than 1.

According to another embodiment of the present invention, a storage medium is further provided, and a computer program is stored in the storage medium, wherein the computer program is configured to execute the above method when running.

According to another embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the above method.

In the embodiment of the present invention, when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by the single quantum logic gate, the control bit of the double quantum logic gate is stored in the preset variable; the preset variable Decompose the double quantum logic gate with the number of control bits greater than or equal to 1 to obtain the quantum logic gate with the number of control bits less than 1; output the target quantum circuit, wherein the target quantum circuit includes the quantum logic gate with the number of control bits less than 1, and The target quantum circuit supports the quantum chip instruction set. Achieved the goal of converting all quantum logic gates in the quantum circuit that do not support the quantum chip instruction set into quantum logic gates supported by the quantum chip instruction set, thus achieving the technical effect of adapting the quantum circuit to any quantum chip instruction set , and then solve the technical problem that the conversion of the two-bit logic gate of the quantum circuit cannot be realized in the related technology.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention and constitute a part of the application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations to the present invention. In the attached picture:

Fig. 1 is a block diagram of the hardware structure of a mobile terminal of a quantum circuit processing method according to an embodiment of the present invention;

2 is a schematic flowchart of a quantum circuit processing method provided according to an embodiment of the present invention;

Fig. 3 is the algorithm flowchart of the present embodiment;

Fig. 4 is a schematic structural diagram of a quantum circuit processing device provided according to an embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first" and "second" in the description and claims of the present invention and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.

According to an embodiment of the present invention, an embodiment of a quantum circuit processing method is provided. It should be noted that the steps shown in the flow charts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and , although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

The method embodiments provided by the embodiments of the present invention can be executed in mobile terminals, computer terminals or similar computing devices. Taking a mobile terminal as an example, FIG. 1 is a block diagram of a hardware structure of a mobile terminal according to a quantum circuit processing method according to an embodiment of the present invention. As shown in FIG. 1, the mobile terminal 10 may include one or more (only one is shown in FIG. 1) processors 102 (the processors 102 may include but not limited to processing devices such as microprocessor MCU or programmable logic device FPGA, etc. ) and a memory 104 for storing data. Optionally, the above-mentioned mobile terminal may also include a transmission device 106 and an input and output device 108 for communication functions. Those skilled in the art can understand that the structure shown in FIG. 1 is only for illustration, and it does not limit the structure of the above mobile terminal. For example, the mobile terminal 10 may also include more or fewer components than those shown in FIG. 1 , or have a different configuration than that shown in FIG. 1 .

The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the quantum circuit processing method in the embodiment of the present invention, and the processor 102 runs the computer program stored in the memory 104, thereby Executing various functional applications and data processing is to realize the above-mentioned method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory that is remotely located relative to the processor 102, and these remote memories may be connected to the mobile terminal 10 through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. The specific example of the above-mentioned network may include a wireless network provided by the communication provider of the mobile terminal 10 . In one example, the transmission device 106 includes a network interface controller (NIC for short), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet in a wireless manner.

Fig. 2 is a schematic flowchart of a quantum circuit processing method provided according to an embodiment of the present invention. As shown in Fig. 2, the method includes the following steps:

Step S202, when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by the single quantum logic gate, storing the control bit of the double quantum logic gate into a preset variable;

Step S204, decomposing the double quantum logic gates whose number of control bits is greater than or equal to 1 in the preset variable, to obtain quantum logic gates whose number of control bits is less than 1;

Step S206, outputting a target quantum circuit, wherein the target quantum circuit includes a quantum logic gate with a control bit number less than 1, and the target quantum circuit supports a quantum chip instruction set.

Through the above steps, when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by the single quantum logic gate, the control bit of the double quantum logic gate is stored in the preset variable; the control bit in the preset variable The double quantum logic gate whose number is greater than or equal to 1 is decomposed to obtain the quantum logic gate whose control bit number is less than 1; output the target quantum circuit, wherein, the target quantum circuit includes the quantum logic gate whose control bit number is less than 1, and the target quantum circuit Support quantum chip instruction set. Achieved the goal of converting all quantum logic gates in the quantum circuit that do not support the quantum chip instruction set into quantum logic gates supported by the quantum chip instruction set, thus achieving the technical effect of adapting the quantum circuit to any quantum chip instruction set , and then solve the technical problem that the conversion of the two-bit logic gate of the quantum circuit cannot be realized in the related technology.

It should be noted that the execution subject mentioned above may be a computer program, but is not limited thereto.

In this embodiment, the quantum circuits to be converted include quantum logic gates that do not support the quantum chip instruction set, that is, include two-bit logic gates or logic gates greater than two bits. The expression form of this embodiment is a piece of computer program, including the input quantum circuit to be converted and the quantum chip instruction set, and the output is the converted quantum circuit (that is, the target quantum circuit), including one or more sequentially arranged Quantum logic gates.

Optionally, the representation form of the input quantum circuit to be converted and the target quantum circuit may be a linked list, an array, a string of JavaScript Object Notation (JSON for short) and the like. In addition, quantum circuits are composed of quantum logic gates, where each quantum logic gate contains three pieces of information: an operation matrix, control bits, and a transpose-conjugate label.

Optionally, this embodiment also includes converting the quantum logic gates in the quantum circuit to be converted before storing the control bits of the double quantum logic gates in the preset variable, wherein the converted quantum logic gates include double quantum logic gates and single quantum logic gates. In the case that the form of the quantum logic gate is larger than the form of the double quantum logic gate, the form of the quantum logic gate is decomposed into the form of the combination of the double quantum logic gate and the single quantum logic gate. For example, the operation matrix is assumed to be given in the form of at most 4×4. If the matrix is larger than 4×4, for each such matrix, the decomposition algorithm is executed in advance to decompose it into a matrix of at most 4×4. The decomposition algorithm can be set according to the known technology that "arbitrary matrix can be divided into 2×2 matrix and 4×4 matrix combination”. Since any matrix can be divided into 2×2 matrix and 4×4 matrix combination, the 4× 4 matrices can be completely constructed by 2×2 and 4×4 matrices (actually, the Controlled Not Gate (CNOT) gate and the single-bit quantum gate are general-purpose gates, and any gate can be converted into these two combination of categories).

The preset variable in this embodiment may be a custom ControlQubitVec vector used to indicate the control qubit vector, or may be other vectors.

Optionally, decompose the double quantum logic gate with the number of control bits greater than or equal to 1 in the preset variable in the following manner to obtain the quantum logic gate with the number of control bits less than 1: traverse the number of control bits in the preset variable greater than 1 or equal to A double quantum logic gate of 1; using a preset decomposition algorithm to decompose a double quantum logic gate with a control bit number greater than 1 in a preset variable, to obtain a quantum logic gate with a control bit number less than 1. The double quantum logic gate with the number of control bits greater than 1 refers to a logic gate whose operation matrix is not C-U, and the quantum logic gate with the number of control bits less than 1 is a C-U quantum logic gate and/or a single qubit gate. Traverse all logic gates whose operation matrix is 4×4, and convert all logic gates whose operation matrix is not C-U into a combination of C-U quantum logic gates and single-qubit gates. Specifically, all operation matrices are not C-U (control unitary transformation, control U gate, for example, CNOT is to control NOT gate, CZ is to control Z gate), and convert it into a combination of C-U quantum logic gate and single qubit gate, Among them, the conversion algorithm is a well-known technology, and it will not be described too much here. After this step, all 4×4 quantum logic gates are C-U type operations. Traverse all the logic gates of ControlQubitVec.size()>1, execute the "multi-bit control gate decomposition algorithm", and replace the logic gates with the quantum circuits represented by the logic gates of ControlQubitVec.size()<=1 (actually converted into in the form of universal quantum logic gates). Then, traverse all logic gates with ControlQubitVec.size()==1. Wherein: the multi-bit control gate decomposition algorithm is an existing technology, which can reduce the complexity of the quantum logic gate. In the decomposition preset variable described in this embodiment, the decomposition algorithm of the double quantum logic gate with the number of control bits greater than 1 and the multi-bit control gate decomposition algorithm idea can be based on Michael.A.Nielsen's "Quantum Computing and Quantum Information" No. 4 The content of this chapter is implemented in combination with computer codes, so it will not be described too much here.

Optionally, the quantum chip instruction set includes: a connection graph of the quantum chip, a single-bit operation supported by each vertex in the connection graph of the quantum chip, and a double-bit operation supported by each edge in the connection graph of the quantum chip.

Quantum logic gates in quantum circuits can include not only single-bit gates, but also two-bit gates and multi-bit gates. Each quantum logic gate can also have multiple control bits, as well as transpose conjugate labels. The generated quantum circuit is adapted according to the input quantum chip instruction set, and each quantum logic gate is an element contained in the instruction set, so it can be run on the chip.

Below in conjunction with a preferred embodiment the present invention is described in detail:

The main purpose of this embodiment is to convert all quantum logic gates in the quantum circuit that do not support the instruction set of the quantum chip into quantum logic gates supported by the instruction set of the quantum chip.

Fig. 3 is the algorithm flowchart of this embodiment, specifically comprises the following steps:

S301: The algorithm starts, and its manifestation is a piece of computer program (quantum program).

S302: The input of the quantum program is [1. The quantum circuit to be converted 2. The instruction set of the quantum chip], and the output it has is [the converted quantum circuit (one or more quantum logic gates arranged in sequence)] .

The input form of the quantum circuit can be a linked list, an array, a JSON string and so on. The output of this program is a quantum circuit in the same form. Quantum circuits are composed of quantum logic gates, and each quantum logic gate contains three pieces of information: operation matrix, control bit, and transpose conjugate label.

S303: The operation matrix is assumed to be given in the form of at most 4×4. If the matrix is larger than 4×4, for each such matrix, perform a decomposition algorithm in advance to decompose it into a matrix of at most 4×4. The decomposition algorithm can be set according to the known technology that "arbitrary matrix can be divided into 2×2 matrix and 4×4 matrix combination”. Since any matrix can be divided into 2×2 matrix and 4×4 matrix combination, the 4× 4 matrices can be constructed through 2×2 and 4×4 matrices (actually, CNOT gates and single-bit quantum gates are universal gates, and any gate can be converted into a combination of these two types of gates).

S304-S305: traverse all logic gates whose operation matrix is 4×4, and convert all logic gates whose operation matrix is not C-U (control unitary transformation, control U gate, such as CNOT is to control NOT gate, CZ is to control Z gate) into C-U's combination of quantum logic gates and single-qubit gates. After this step, all 4×4 quantum logic gates are C-U type operations.

S306-S308: For all 4×4 logic gates, move the control bits in the C-U operation to ControlQubitVec (if it does not exist, set up a ControlQubitVec), and use the U (controlled matrix) matrix in the C-U operation as New operation matrix. After this step ends, the operation matrix of all quantum logic gates is 2×2.

S309-S310: traverse all the logic gates of ControlQubitVec.size()>1, execute the "multi-bit control gate decomposition algorithm", and replace the logic gates with the quantum circuits represented by the logic gates of ControlQubitVec.size()<=1 (the actual It is converted into the form of a universal quantum logic gate).

S311: Traverse all logic gates with ControlQubitVec.size()==1, refer to patent 201811082315.X, application date: September 17, 2018, name: processing method and device for two-qubit logic gates, combining logic gates and quantum instructions Set as input, execute the algorithm shown in Figure 4 of reference patent 201811082315.X, and replace the single-bit gate with a quantum circuit for each output. Here, the operation matrix of the logic gate is a 2×2 matrix, and contains one control bit, so the whole is a two-bit operation. The scheme of this patent can be directly converted into a two-bit gate in the instruction set, and the two-bit gate here is expressed as a 4×4 matrix. After this step, ControlQubitVec.size()==0 must be true, the operation matrix contains 4×4 and 2×2 forms, and all 4×4 operation matrices must satisfy the two bits of the quantum instruction set operate.

S312: Inputting the quantum circuit into the optimization algorithm can obtain a relatively optimized representation. The resulting quantum circuit can be optimized to reduce the number of logic gates in the final quantum circuit.

S313-S314: Output the quantum circuit, and the algorithm ends.

It can be known from the above that in this embodiment, any quantum circuit can be adapted to any quantum chip instruction set.

It should be noted that the execution subject of the above steps may be the terminal shown in FIG. 1 above, but is not limited thereto.

An embodiment of the present invention also provides a quantum circuit processing device. FIG. 4 is a schematic structural diagram of a quantum circuit processing device provided according to an embodiment of the present invention. As shown in FIG. 4 , the device includes:

The storage module 42 is used to store the control bit of the double quantum logic gate in the preset variable when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by the single quantum logic gate;

The decomposition module 44 is used to decompose the double quantum logic gate with the number of control bits greater than or equal to 1 in the preset variable to obtain the quantum logic gate with the number of control bits less than 1;

The output module 46 is configured to output the target quantum circuit, wherein the target quantum circuit includes a quantum logic gate whose control bit number is less than 1, and the target quantum circuit supports a quantum chip instruction set.

Through the above device, when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by the single quantum logic gate, the control bit of the double quantum logic gate is stored in the preset variable; the control bit in the preset variable The double quantum logic gate whose number is greater than or equal to 1 is decomposed to obtain the quantum logic gate whose control bit number is less than 1; output the target quantum circuit, wherein, the target quantum circuit includes the quantum logic gate whose control bit number is less than 1, and the target quantum circuit Support quantum chip instruction set. Achieved the goal of converting all quantum logic gates in the quantum circuit that do not support the quantum chip instruction set into quantum logic gates supported by the quantum chip instruction set, thus achieving the technical effect of adapting the quantum circuit to any quantum chip instruction set , and then solve the technical problem that the conversion of the two-bit logic gate of the quantum circuit cannot be realized in the related technology.

In an optional embodiment, the above-mentioned device further includes a conversion module, which is used to convert the quantum logic gate in the quantum circuit to be converted before storing the control bits of the double quantum logic gate into preset variables, wherein the converted Quantum logic gates include double quantum logic gates and single quantum logic gates. The conversion module includes: a first decomposing unit, used for decomposing the form of the quantum logic gate into the combination form of the double quantum logic gate and the single quantum logic gate when the form of the quantum logic gate is larger than that of the double quantum logic gate.

In an optional embodiment, the decomposition module includes: a traversal unit for traversing the double quantum logic gates whose control bit number is greater than 1 or equal to 1 in the preset variable; a second decomposition unit for decomposing The double quantum logic gate whose control bit number is greater than 1 in the preset variable obtains the quantum logic gate whose control bit number is less than 1.

In this embodiment, the quantum circuits to be converted include quantum logic gates that do not support the quantum chip instruction set, that is, include two-bit logic gates or logic gates greater than two bits. The expression form of this embodiment is a piece of computer program, including the input quantum circuit to be converted and the quantum chip instruction set, and the output is the converted quantum circuit (that is, the target quantum circuit), including one or more sequentially arranged Quantum logic gates.

Optionally, the representation form of the input quantum circuit to be converted and the target quantum circuit may be a linked list, an array, a string of JavaScript Object Notation (JSON for short) and the like. In addition, quantum circuits are composed of quantum logic gates, where each quantum logic gate contains three pieces of information: an operation matrix, control bits, and a transpose-conjugate label.

Optionally, this embodiment also includes converting the quantum logic gates in the quantum circuit to be converted before storing the control bits of the double quantum logic gates in the preset variable, wherein the converted quantum logic gates include double quantum logic gates and single quantum logic gates. In the case that the form of the quantum logic gate is larger than the form of the double quantum logic gate, the form of the quantum logic gate is decomposed into the form of the combination of the double quantum logic gate and the single quantum logic gate. For example, the operation matrix is assumed to be given in the form of at most 4×4. If the matrix is larger than 4×4, for each such matrix, the decomposition algorithm is executed in advance to decompose it into a matrix of at most 4×4. The decomposition algorithm can be set according to the known technology that "arbitrary matrix can be divided into 2×2 matrix and 4×4 matrix combination”. Since any matrix can be divided into 2×2 matrix and 4×4 matrix combination, the 4× 4 matrices can be constructed through 2×2 and 4×4 matrices (actually, CNOT gates and single-bit quantum gates are universal gates, and any gate can be converted into a combination of these two types of gates).

The preset variable in this embodiment may be a custom ControlQubitVec vector used to indicate the control qubit vector, or may be other vectors.

Optionally, decompose the double quantum logic gate with the number of control bits greater than or equal to 1 in the preset variable in the following manner to obtain the quantum logic gate with the number of control bits less than 1: traverse the number of control bits in the preset variable greater than 1 or equal to A double quantum logic gate of 1; using a preset decomposition algorithm to decompose a double quantum logic gate with a control bit number greater than 1 in a preset variable, to obtain a quantum logic gate with a control bit number less than 1. For example: traverse all logic gates whose operation matrix is 4×4, and convert all logic gates whose operation matrix is not C-U into a combination of C-U quantum logic gates and single-qubit gates. After this step, all 4×4 quantum logic gates are C-U type operations. Traverse all the logic gates of ControlQubitVec.size()>1, execute the "multi-bit control gate decomposition algorithm", and replace the logic gates with the quantum circuits represented by the logic gates of ControlQubitVec.size()<=1 (actually converted into in the form of universal quantum logic gates). Then, traverse all logic gates with ControlQubitVec.size()==1.

Optionally, the quantum chip instruction set includes: a connection graph of the quantum chip, a single-bit operation supported by each vertex in the connection graph of the quantum chip, and a double-bit operation supported by each edge in the connection graph of the quantum chip.

Quantum logic gates in quantum circuits can include not only single-bit gates, but also two-bit gates and multi-bit gates. Each quantum logic gate can also have multiple control bits, as well as transpose conjugate labels. The generated quantum circuit is adapted according to the input quantum chip instruction set, and each quantum logic gate is an element contained in the instruction set, so it can be run on the chip.

It should be noted that the foregoing apparatus may be located in the terminal shown in FIG. 1 above, but is not limited thereto.

An embodiment of the present invention also provides a storage medium, in which a computer program is stored, wherein the computer program is set to execute the steps in any one of the above method embodiments when running.

Optionally, in this embodiment, the above-mentioned storage medium may be configured to store a computer program for performing the following steps:

S1, when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by the single quantum logic gate, storing the control bit of the double quantum logic gate into a preset variable;

S2, decomposing the double quantum logic gate with the number of control bits greater than or equal to 1 in the preset variable to obtain the quantum logic gate with the number of control bits less than 1;

S3, outputting a target quantum circuit, wherein the target quantum circuit includes a quantum logic gate with a control bit number less than 1, and the target quantum circuit supports a quantum chip instruction set.

Optionally, in this embodiment, the above-mentioned storage medium may include but not limited to: U disk, read-only memory (Read-Only Memory, ROM for short), random access memory (Random Access Memory, RAM for short), Various media that can store computer programs, such as removable hard disks, magnetic disks, or optical disks.

An embodiment of the present invention also provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

Optionally, the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.

Optionally, in this embodiment, the above-mentioned processor may be configured to execute the following steps through a computer program:

S1, when the operation of the double quantum logic gate in the quantum circuit to be converted is controlled by the single quantum logic gate, storing the control bit of the double quantum logic gate into a preset variable;

S2, decomposing the double quantum logic gate with the number of control bits greater than or equal to 1 in the preset variable to obtain the quantum logic gate with the number of control bits less than 1;

S3, outputting a target quantum circuit, wherein the target quantum circuit includes a quantum logic gate with a control bit number less than 1, and the target quantum circuit supports a quantum chip instruction set.

Optionally, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementation manners, and details are not repeated in this embodiment.

The serial numbers of the above embodiments of the present invention are for description only, and do not represent the advantages and disadvantages of the embodiments.

In the above-mentioned embodiments of the present invention, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed technical content can be realized in other ways. Wherein, the device embodiments described above are only illustrative. For example, the division of the units may be a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or may be Integrate into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of units or modules may be in electrical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes. .

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (12)

1. a kind of processing method of quantum wire characterized by comprising

It, will be described in the case that the operation of double Quantum logic gates in quantum wire to be converted is controlled by single Quantum logic gates The control bit of double Quantum logic gates is stored into design variables；

Double Quantum logic gates by control bit number in the design variables more than or equal to 1 are decomposed, and control ratio is obtained Quantum logic gates of the special number less than 1；

Export target quantum wire, wherein include the quantum logic of the control bit number less than 1 in the target quantum wire Door, and the target quantum wire supports quantum chip instruction set.

2. the method according to claim 1, wherein by the control bit storage of double Quantum logic gates to institute Before stating in design variables, the method also includes:

Convert the Quantum logic gates in the quantum wire to be converted, wherein the Quantum logic gates after conversion include that double quantum are patrolled Collect door and single Quantum logic gates.

3. according to the method described in claim 2, it is characterized in that, converting the Quantum logic gates in the quantum wire to be converted Include:

In the case where the form of the Quantum logic gates is greater than the form of double Quantum logic gates, by the Quantum logic gates Form be decomposed into the forms of double Quantum logic gates and single Quantum logic gates combination.

4. the method according to claim 1, wherein control bit number in the design variables to be greater than or wait Double Quantum logic gates in 1 are decomposed, and Quantum logic gates of the control bit number less than 1 are obtained, comprising:

It traverses control bit number in the design variables and is greater than 1 or double Quantum logic gates equal to 1；

Double Quantum logic gates that control bit number in the design variables is greater than 1 are decomposed using preset decomposition algorithm, are controlled Quantum logic gates of the bit number less than 1.

5. the method according to claim 1, wherein the Quantum logic gates include:

Operation matrix, control bit, transposition conjugation label.

6. the method according to claim 1, wherein the quantum chip instruction set includes:

The connection figure of quantum chip, the single-bit supported in the quantum chip connection figures with each vertex operate；The amount The dibit operation that each side is supported in sub- chip connection figures.

7. a kind of processing unit of quantum wire characterized by comprising

Memory module, what the operation for double Quantum logic gates in quantum wire to be converted was controlled by single Quantum logic gates In the case of, the control bit of double Quantum logic gates is stored into design variables；

Decomposing module is divided for double Quantum logic gates by control bit number in the design variables more than or equal to 1 Solution, obtains Quantum logic gates of the control bit number less than 1；

Output module, for exporting target quantum wire, wherein include control bit number in the target quantum wire less than 1 The Quantum logic gates, and the target quantum wire support quantum chip instruction set.

8. device according to claim 7, which is characterized in that described device further include:

Conversion module, for converting institute before storing the control bit of double Quantum logic gates into the design variables State the Quantum logic gates in quantum wire to be converted, wherein the Quantum logic gates after conversion include double Quantum logic gates and single amount Sub- logic gate.

9. device according to claim 8, which is characterized in that the conversion module includes:

First decomposition unit, for the form in the Quantum logic gates be greater than double Quantum logic gates form the case where Under, the form of the Quantum logic gates is decomposed into the form of double Quantum logic gates and single Quantum logic gates combination.

10. device according to claim 7, which is characterized in that the decomposing module includes:

Traversal Unit is greater than 1 or double Quantum logic gates equal to 1 for traversing control bit number in the design variables；

Second decomposition unit, for decomposing double amounts that control bit number in the design variables is greater than 1 using preset decomposition algorithm Sub- logic gate obtains Quantum logic gates of the control bit number less than 1.

11. a kind of storage medium, which is characterized in that be stored with computer program in the storage medium, wherein the computer Program is arranged to execute method described in any one of claim 1 to 6 when operation.

12. a kind of electronic device, including memory and processor, which is characterized in that be stored with computer journey in the memory Sequence, the processor are arranged to run the computer program to execute side described in any one of claim 1 to 6 Method.